CN206546416U - A kind of IC chip ageing tester based on mother baby plate - Google Patents
A kind of IC chip ageing tester based on mother baby plate Download PDFInfo
- Publication number
- CN206546416U CN206546416U CN201720220510.9U CN201720220510U CN206546416U CN 206546416 U CN206546416 U CN 206546416U CN 201720220510 U CN201720220510 U CN 201720220510U CN 206546416 U CN206546416 U CN 206546416U
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- China
- Prior art keywords
- chip
- daughter board
- aging
- motherboard
- tested
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000032683 aging Effects 0.000 title claims abstract description 93
- 238000012360 testing method Methods 0.000 claims abstract description 40
- 238000009434 installation Methods 0.000 claims abstract description 24
- 230000002093 peripheral effect Effects 0.000 claims abstract description 20
- 230000015556 catabolic process Effects 0.000 claims abstract description 14
- 238000006731 degradation reaction Methods 0.000 claims abstract description 14
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000007787 solid Substances 0.000 claims 1
- 238000011056 performance test Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- PRPINYUDVPFIRX-UHFFFAOYSA-N 1-naphthaleneacetic acid Chemical compound C1=CC=C2C(CC(=O)O)=CC=CC2=C1 PRPINYUDVPFIRX-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The utility model is related to a kind of IC chip ageing tester based on mother baby plate, and the device includes universal burn-in motherboard and multiple aging daughter boards；Universal burn-in motherboard is provided with multiple stations, station and is provided with the multiple spring needles arranged in array；Aging daughter board is mountable on a station of universal burn-in motherboard, and its front is provided with chip installation portion and is integrated with peripheral applications circuit；The multiple hard contacts arranged in array are installed on the back side of aging daughter board, wherein, a part for multiple hard contacts is connected with the pin of chip to be tested, and another part is connected with peripheral applications circuit；Contact pin on station matches and is in contact with the hard contact at the aging daughter board back side, so that aging daughter board is accessed into universal burn-in motherboard.The utility model can be applied to polytype IC chip and carry out the performance test after degradation and aging, effectively save testing cost, reduce test period.
Description
Technical field
The utility model is related to the degradation technical field of IC products, and in particular to a kind of based on mother baby plate
IC chip ageing tester.
Background technology
IC chip will typically pass through burn-in test before being produced in batches（Ensure the use longevity of chip
Life and reliability）And performance test（The batch production test of the function and performance of chip）, by both the above test it is integrated
Circuit chip can just be defined as non-defective unit.Traditional burn-in board is usually the multistation aging PCB with least 77 stations
Plate, each station is provided with special chip socket, the pin of chip to be tested is introduced into aging pcb board, to multiple cores to be tested
Piece carries out the powered degradation of HTHP.
However, the species of chip under test is various, it encapsulates pattern and the arrangement of pin is different, therefore for different types of
Chip under test is, it is necessary to customized different burn-in board.The design and manufacture cost of current burn-in board is higher, brings very high
Testing cost, for those, the monovalent simple product of relatively low and measurement circuit is more difficult receives.In addition, customized burn-in board
The early-stage preparations time is longer, increases test period, reduces testing efficiency.
Utility model content
For the shortcoming or deficiency of above-mentioned prior art, the technical problems to be solved in the utility model is to provide one kind and is based on
The IC chip ageing tester of mother baby plate, on the premise of test accuracy is ensured, can be applied to polytype
IC chip carry out the performance test after degradation and aging, so as to effectively save testing cost, reduction is surveyed
The examination cycle.
In order to solve the above technical problems, the utility model has following composition：
A kind of IC chip ageing tester based on mother baby plate, the device includes universal burn-in motherboard and multiple
Aging daughter board；Universal burn-in motherboard is provided with multiple stations, golden finger interface and power interface, station and is provided with array cloth
The multiple contact pins put, golden finger interface is used to be connected with degradation board；Aging daughter board is mountable to universal burn-in motherboard
A station on, its front is provided with chip installation portion and is integrated with peripheral applications circuit, and chip to be tested is installed on chip peace
Dress portion, peripheral applications circuit matches with the chip to be tested that chip installation portion is installed；It is provided with the back side of aging daughter board
The multiple hard contacts arranged in array, wherein, a part and the chip installation portion of multiple hard contacts install core to be tested
The pin of piece is electrically connected with, and another part is electrically connected with the peripheral applications circuit on aging daughter board front；Contact pin on station
Match and be in contact with the hard contact at the aging daughter board back side, so that aging daughter board is accessed into universal burn-in motherboard.
The contact pin is spring needle.
Chip to be tested is installed on the chip installation portion on aging daughter board in paster mode.
Chip to be tested is installed on the chip installation portion on aging daughter board with inserting mode, and the chip installation portion is provided with
One is used for the chip carrier socket of grafting chip to be tested.
Between the chip to be tested that all peripheral applications circuits and chip installation portion are installed on the aging daughter board,
It is electrically connected with by 0 Ohmic resistance.
The device also includes a chip and connects socket, and chip connection socket includes being provided with survey on a socket, socket
Test plate (panel), test board is provided with the multiple spring needles arranged in array, the hard contact at spring needle and the aging daughter board back side matches,
And be in contact, so that by by the chip access performance tester after aging.
The aging daughter board is fixed on universal burn-in motherboard by bolt, nut, and aging daughter board is provided with to be passed through for bolt
Through hole.
Compared with prior art, the utility model has the advantage of：
（1）Using the mother baby plate structure being made up of universal burn-in motherboard and aging daughter board, boss's daughter board is mountable to general
On one station of aging motherboard, chip to be tested is installed on the chip installation portion on aging daughter board；It is mountable to lead to using change
Whole burn-in board is changed in the prior art to substitute with the aging daughter board on aging motherboard, it is no longer necessary to according to different encapsulation
The whole burn-in board of the product subscription specific of pattern, considerably reduces testing cost, reduces test period, improve
Testing efficiency, is highly suitable for the burn-in test of a variety of different encapsulating products.
（2）The back side of aging daughter board is provided with multiple hard contacts, a portion hard contact with installed it is to be measured
The pin of examination chip is connected, and another part is connected with the peripheral applications circuit on aging daughter board front；On the one hand, setting
Hard contact is easy to be connected with the contact pin on universal burn-in motherboard station；On the other hand, after degradation terminates, periphery is made
Application circuit disconnects with chip, by the aging daughter board access performance tester with chip after aging, rapidly carries out aging
The performance test of chip afterwards.
Brief description of the drawings
Fig. 1：The structural representation of universal burn-in mother matrix in the utility model.
Fig. 2：The positive structure schematic of aging daughter board in the utility model.
Fig. 3：The structure schematic diagram of aging daughter board in the utility model.
Fig. 4：The cooperation schematic diagram of chip to be tested and aging daughter board in the utility model.
Fig. 5：The decomposing schematic representation of aging daughter board and universal burn-in motherboard in the utility model with chip to be tested.
Fig. 6：The structural representation that chip to be tested in the utility model aging daughter board is connected with peripheral applications circuit.
Fig. 7：The utility model chips connect the structural representation of socket.
Fig. 8：The structural representation of test board in the utility model chip connection socket.
Embodiment
The technique effect of design of the present utility model, concrete structure and generation is made furtherly below with reference to accompanying drawing
It is bright, to be fully understood from the purpose of this utility model, feature and effect.
As shown in Figures 1 to 8, a kind of IC chip ageing tester based on mother baby plate, including universal burn-in
Motherboard 10 and multiple aging daughter boards 20.
Universal burn-in motherboard 10 provided with it is multiple be used for install aging daughter board 20 station 11, for degradation board
The multiple contact pins arranged in array are installed on golden finger interface 12, power interface 13 and the LED light being connected, station 11
111；Wherein, golden finger 12, power interface 13 and LED light, to realize drive module, power supply and the work of degradation board
The functions such as the access that work is indicated.In specific embodiment, universal burn-in motherboard 10 is by epoxide resin material（FR5）What sheet material was made
Pcb board, epoxide resin material has high service life, it is ensured that universal burn-in motherboard can be repeatedly multiplexed.
Aging daughter board 20 is the pcb board of certain specification size, is mountable on a station 11 of universal burn-in motherboard 10, and
It is fixed in surrounding using bolt, nut on universal burn-in motherboard 10, the surrounding of boss's daughter board 20 is provided with what is passed through for bolt
Through hole 24.
The front of aging daughter board 20 is provided with chip installation portion 21 and is integrated with peripheral applications circuit, chip 30 to be tested
It is installed on chip installation portion 21；Peripheral applications circuit matches with the chip to be tested 30 that chip installation portion 21 is installed, specifically
For：According to the encapsulation pattern and pin arrangements of the chip to be tested installed, to collect the periphery that paired chip carries out degradation
Application circuit.For the integrated approach of peripheral applications circuit, it is the state of the art, will not be repeated here.
In the utility model, chip 30 to be tested can be installed on aging daughter board 20 by paster mode or inserting mode
Chip installation portion 21；When being installed using inserting mode, chip installation portion 21 is used for grafting chip 30 to be tested provided with one
Chip carrier socket.For with paster mode and the method with inserting mode chip, being well-known in the art, herein no longer
Repeat.
The multiple hard contacts 22 arranged in array are installed on the back side of aging daughter board 20, wherein, multiple hard contacts
The pin 31 that 22 part installs chip 30 to be tested with chip installation portion 21 is electrically connected with, another part and aging daughter board
Peripheral applications circuit on 20 fronts is electrically connected with；Fig. 4 and Fig. 5 are shown when installing chip to be tested in paster mode, metal
Contact 22 and the pin 31 and the connection of peripheral applications circuit of chip 30 to be tested.In the present embodiment, hard contact 22
Be made up of the good metal alloy compositions of contact performance, such as craft of gilding nickel billon or other be difficult oxide alloy material.
When aging daughter board 20 is installed on the station 11 of universal burn-in motherboard 10, contact pin 111 and aging on station 11
The hard contact 22 at the back side of daughter board 20 matches and is in contact, so that aging daughter board 20 is accessed into universal burn-in motherboard 10.Specifically
In embodiment, contact pin 111 is adopted as spring needle；It is using the advantage of spring needle：Both an oxidation can have been avoided contact with and caused to connect
Touch bad, the spring needle of this single-point can be rapidly changed, so that the use of universal burn-in motherboard when occurring single-point damage again
Life-span is significantly increased, and maintenance cost is greatly reduced.
As shown in fig. 6, peripheral applications circuit all on aging daughter board 20 and chip installation portion 21 installed it is to be tested
Between chip 30, it is electrically connected with by 0 Ohmic resistance 23.After degradation terminates, high temperature flatiron tip-off can be used to go
Fall 0 Ohmic resistance, realization quickly, without damage disconnects the peripheral applications circuit on aging daughter board 20 with chip 30 to be tested.
Test device of the present utility model also includes a chip and connects socket 40, for the aging daughter board 20 after grafting aging
So that the chip access performance tester after aging is carried out into performance test；As shown in Figure 7 and Figure 8, chip connection socket 40 is wrapped
Include and test board 411, test board are installed on the socket 41 and socket cover 42 being connected with performance testing apparatus, socket 41
411 are provided with the multiple spring needles 412 arranged in array, and the aging daughter board 20 after aging is installed on into chip connection socket 40
When, the spring needle 412 on test board 411 matches and is in contact with the hard contact 22 at the back side of aging daughter board 20, so that will be old
Chip access performance tester after change.When aging daughter board 20 is plugged in into chip connection socket 40, pass through aging daughter board 20
The hard contact 22 being connected with chip at the back side inputs the test signal of performance testing apparatus, and the chip after aging is carried out
Performance test, without developing a set of testing scheme again again, directly using the existing volume production of performance testing apparatus general at present
Test program, it is to avoid the wastes of huge financial resources, material resources and manpower.
Correspondingly, a kind of IC chip dynamic aging method of testing based on mother baby plate, comprises the following steps：
（1）For the chip to be tested of different types, matched peripheral applications circuit is integrated in aging daughter board
Front；And hard contact array is installed at the back side of aging daughter board；
（2）Chip to be tested is installed on to the chip installation portion of aging daughter board, and by the pin of chip to be tested and periphery
Application circuit is electrically connected with corresponding hard contact respectively；
（3）By the aging daughter board with chip to be tested, on the station for being installed on universal burn-in motherboard；
（4）Universal burn-in motherboard is connected with degradation board, to introduce degradation board by aging daughter board
Aging drive signal, carry out hot and humid dynamic aging test；
（5）After degradation terminates, aging daughter board is removed from universal burn-in motherboard, and by the periphery on aging daughter board
Application circuit disconnects with the chip after aging；
（6）Aging daughter board with chip after aging is connected with performance testing apparatus, to pass through the aging daughter board back side
Hard contact introduce performance testing apparatus test signal, carry out performance test.
According to the teaching of the present embodiment, other the utility model protection models can be achieved in those skilled in the art completely
Enclose interior technical scheme.
Claims (7)
1. a kind of IC chip ageing tester based on mother baby plate, it is characterised in that the device includes universal burn-in
Motherboard（10）With multiple aging daughter boards（20）；
Universal burn-in motherboard（10）It is provided with multiple stations（11）, golden finger interface（12）And power interface（13）, station（11）
On the multiple contact pins arranged in array are installed（111）, golden finger interface（12）For being connected with degradation board；
Aging daughter board（20）It is mountable to universal burn-in motherboard（10）A station（11）On, its front is provided with chip installation portion
（21）And peripheral applications circuit is integrated with, chip to be tested is installed on chip installation portion（21）, peripheral applications circuit and chip are pacified
Dress portion（21）The chip to be tested installed matches；
Aging daughter board（20）The back side on the multiple hard contacts arranged in array are installed（22）, wherein, multiple hard contacts
（22）A part and chip installation portion（21）The pin for installing chip to be tested is electrically connected with, another part and aging daughter board
（20）Peripheral applications circuit on front is electrically connected with；
Station（11）On contact pin（111）With aging daughter board（20）The hard contact at the back side（22）Match and be in contact, so that
By aging daughter board（20）Access universal burn-in motherboard（10）.
2. test device according to claim 1, it is characterised in that：The contact pin（111）For spring needle.
3. test device according to any one of claim 1 to 2, it is characterised in that：Chip to be tested is in paster mode
It is installed on aging daughter board（20）On chip installation portion（21）.
4. test device according to any one of claim 1 to 2, it is characterised in that：Chip to be tested is with inserting mode
It is installed on aging daughter board（20）On chip installation portion（21）, the chip installation portion（21）It is used for grafting provided with one to be tested
The chip carrier socket of chip.
5. test device according to any one of claim 1 to 2, it is characterised in that：The aging daughter board（20）Upper institute
Some peripheral applications circuits and chip installation portion（21）Between the chip to be tested installed, electrically connected by 0 Ohmic resistance
Connect.
6. test device according to any one of claim 1 to 2, it is characterised in that：The device also includes a chip and connected
Combination hub（40）, chip connection socket（40）Including a socket（41）, socket（41）On test board is installed（411）, survey
Test plate (panel)（411）It is provided with the multiple spring needles arranged in array（412）, spring needle（412）With aging daughter board（20）The gold at the back side
Belong to contact（22）Match and be in contact, so that by the chip access performance tester after aging.
7. test device according to claim 1, it is characterised in that：The aging daughter board（20）It is solid by bolt, nut
Due to universal burn-in motherboard（10）, aging daughter board（20）It is provided with the through hole passed through for bolt（24）.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720220510.9U CN206546416U (en) | 2017-03-08 | 2017-03-08 | A kind of IC chip ageing tester based on mother baby plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720220510.9U CN206546416U (en) | 2017-03-08 | 2017-03-08 | A kind of IC chip ageing tester based on mother baby plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206546416U true CN206546416U (en) | 2017-10-10 |
Family
ID=59994502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720220510.9U Withdrawn - After Issue CN206546416U (en) | 2017-03-08 | 2017-03-08 | A kind of IC chip ageing tester based on mother baby plate |
Country Status (1)
| Country | Link |
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| CN (1) | CN206546416U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106771987A (en) * | 2017-03-08 | 2017-05-31 | 上海鑫匀源科技有限公司 | A kind of IC chip ageing tester and method of testing based on mother baby plate |
| CN110632416A (en) * | 2019-09-12 | 2019-12-31 | 艾体威尔电子技术(北京)有限公司 | Device and method for detecting instant disconnection of probe |
| CN110994223A (en) * | 2019-11-13 | 2020-04-10 | 北京时代民芯科技有限公司 | An aging test socket for switching power supply circuits |
| CN112881898A (en) * | 2021-02-24 | 2021-06-01 | 李彩芬 | High-temperature aging test device for integrated circuit |
| CN113466771A (en) * | 2021-06-28 | 2021-10-01 | 上海华力集成电路制造有限公司 | Device and method for verifying aging board verification waveform |
| CN116068380A (en) * | 2023-03-01 | 2023-05-05 | 上海聚跃检测技术有限公司 | Chip package testing method and device |
-
2017
- 2017-03-08 CN CN201720220510.9U patent/CN206546416U/en not_active Withdrawn - After Issue
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106771987A (en) * | 2017-03-08 | 2017-05-31 | 上海鑫匀源科技有限公司 | A kind of IC chip ageing tester and method of testing based on mother baby plate |
| CN106771987B (en) * | 2017-03-08 | 2023-08-22 | 上海鑫匀源科技有限公司 | Integrated circuit chip burn-in test device and test method based on sub-mother board |
| CN110632416A (en) * | 2019-09-12 | 2019-12-31 | 艾体威尔电子技术(北京)有限公司 | Device and method for detecting instant disconnection of probe |
| CN110632416B (en) * | 2019-09-12 | 2022-02-01 | 艾体威尔电子技术(北京)有限公司 | Device and method for detecting instant disconnection of probe |
| CN110994223A (en) * | 2019-11-13 | 2020-04-10 | 北京时代民芯科技有限公司 | An aging test socket for switching power supply circuits |
| CN110994223B (en) * | 2019-11-13 | 2021-08-13 | 北京时代民芯科技有限公司 | An aging test socket for switching power supply circuits |
| CN112881898A (en) * | 2021-02-24 | 2021-06-01 | 李彩芬 | High-temperature aging test device for integrated circuit |
| CN113466771A (en) * | 2021-06-28 | 2021-10-01 | 上海华力集成电路制造有限公司 | Device and method for verifying aging board verification waveform |
| CN116068380A (en) * | 2023-03-01 | 2023-05-05 | 上海聚跃检测技术有限公司 | Chip package testing method and device |
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|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20171010 Effective date of abandoning: 20230822 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20171010 Effective date of abandoning: 20230822 |
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| AV01 | Patent right actively abandoned |