CN206270863U - CMOS data clearing device and computer - Google Patents

Abstract

The utility model provides a CMOS data clearing device and computer. The CMOS data clearing device comprises a reset signal output circuit, a delay unit, a switch circuit and a CMOS data clearing circuit which are electrically connected in sequence; the reset signal output circuit is used for outputting a reset signal to the delay unit; the delay unit is used for continuously sending a first trigger signal to the switch circuit within a time period after receiving the reset signal; the switch circuit is used for sending a second trigger signal to the CMOS data clearing circuit after receiving the first trigger signal; the CMOS data clearing circuit is used for clearing the CMOS data of the CMOS chip when receiving the second trigger signal. Utilize the utility model discloses a CMOS data clearing device clears away CMOS data, has avoided loaded down with trivial details operations such as the quick-witted case of dismantlement computer, provides convenience for the user.

Description

CMOS data clearing device and computer

technical field

The utility model relates to the field of computers, in particular to a CMOS data clearing device and a computer.

Background technique

When the user forgets the CMOS (Complementary Metal Oxide Semiconductor) password and cannot start the computer, he can clear the CMOS data in the CMOS chip by using the jumper on the motherboard, so as to restart the computer. In the prior art, the jumper method is often used to clear the CMOS data by hardware. This method needs to disassemble the case, find the jumper position for clearing the CMOS data, and then perform the jumper operation. Because the steps of disassembling the case are very cumbersome, it brings great inconvenience to the user. Big inconvenience.

Utility model content

The technical problem to be solved by the utility model is to provide a CMOS data clearing device and a computer in order to overcome the defects of complex operation and cumbersome steps of the prior art CMOS data clearing method.

The utility model solves the problems of the technologies described above through the following technical solutions:

A CMOS data clearing device, characterized in that the CMOS data clearing device comprises a reset signal output circuit, a delay unit, a switch circuit and a CMOS data clearing circuit electrically connected in sequence;

The reset signal output circuit is used to output a reset signal to the delay unit;

The delay unit is configured to continuously send the first trigger signal to the switch circuit within a period of time after receiving the reset signal;

The switch circuit is used to send a second trigger signal to the CMOS data clearing circuit after receiving the first trigger signal;

The CMOS data clearing circuit is used for clearing the CMOS data of the CMOS chip when receiving the second trigger signal.

Preferably, the delay unit includes any one of a 555 delay circuit or a single-chip microcomputer.

Preferably, the 555 delay circuit includes a 555 chip, a first resistor, a second resistor, a capacitor and a power supply;

One end of the first resistor is electrically connected to the trigger pin of the 555 chip, and the other end is electrically connected to the power supply;

One end of the second resistor is electrically connected to the trigger pin, the threshold pin and the discharge pin of the 555 chip, and the other end is electrically connected to the power supply;

One end of the capacitor is electrically connected to the trigger pin of the 555 chip, and the other end is grounded;

The reset terminal pin, power supply voltage pin and control voltage terminal pin of the 555 chip are all electrically connected to the power supply; the output terminal of the 555 chip is electrically connected to the input terminal of the switch circuit; the 555 The ground pin of the chip is grounded.

Preferably, the 555 delay circuit further includes a first diode, the anode of the first diode is electrically connected to the power supply, and the cathode is electrically connected to the control voltage terminal pin of the 555 chip.

Preferably, the second resistor is a sliding rheostat.

Preferably, the switch circuit includes an N-channel MOS field effect transistor, the gate of the N-channel MOS field effect transistor is electrically connected to the output terminal of the 555 chip, the source is grounded, and the drain is connected to the output terminal of the 555 chip. The reset terminal of the CMOS chip is electrically connected.

Preferably, the switch circuit further includes a second diode and two Zener diodes connected in reverse series;

One end of the two anti-series Zener diodes is electrically connected to the gate of the N-channel MOS field effect transistor, and the other end is electrically connected to the source of the N-channel MOS field effect transistor;

The anode of the second diode is electrically connected to the source of the N-channel MOS field effect transistor, and the cathode is electrically connected to the drain of the N-channel MOS field effect transistor.

Preferably, the switch circuit includes an NPN transistor, the base of the NPN transistor is electrically connected to the output terminal of the 555 chip through a third resistor, the emitter is grounded, and the collector is connected to the reset terminal of the CMOS chip. electrical connection.

Preferably, the first trigger signal is at high level, and the second trigger signal is at low level.

The utility model also includes a computer, which includes a reset function key and a CMOS chip. Electrically connected, the output end of the CMOS data clearing circuit is electrically connected to the reset end of the CMOS chip;

The reset function key is used to generate the reset signal.

The positive progressive effect of the utility model is that: the CMOS data clearing device of the utility model can trigger the CMOS chip to directly clear the CMOS data of the computer after receiving the reset signal. Therefore, the CMOS data clearing device of the utility model is used to clear the CMOS data, avoiding complicated operations such as dismantling the chassis of the computer, and providing convenience for the user.

Description of drawings

FIG. 1 is a schematic structural diagram of a CMOS data erasing device according to Embodiment 1 of the present invention.

FIG. 2 is a schematic structural diagram of a CMOS data erasing device according to Embodiment 2 of the present invention.

FIG. 3 is a schematic structural diagram of a CMOS data erasing device according to Embodiment 3 of the present invention.

FIG. 4 is a schematic structural diagram of a CMOS data erasing device according to Embodiment 4 of the present invention.

detailed description

A preferred embodiment is given below, and the utility model is described more clearly and completely in conjunction with the accompanying drawings.

Example 1

As shown in FIG. 1 , the CMOS data clearing device of this embodiment includes a reset signal output circuit 1 , a delay unit 2 , a switch circuit 3 and a CMOS data clearing circuit 4 which are electrically connected in sequence. The reset signal output circuit 1 is used to output the reset signal to the delay unit 2; after the delay unit 2 receives the reset signal, within a period of time (usually 10s-15s, that is, the time required to clear the CMOS data in the CMOS chip) Continuously send the first trigger signal to the switch circuit 3; the switch circuit 3 sends the second trigger signal to the CMOS data clearing circuit 4 after receiving the first trigger signal; the CMOS data clearing circuit 4 is ready when receiving the second trigger signal Clear the CMOS data in the CMOS chip.

In this embodiment, if the CMOS data needs to be cleared, the CMOS chip can be triggered to directly clear the CMOS data of the computer only by outputting the reset signal through the reset signal output circuit. Utilizing the CMOS data clearing device of this embodiment to clear CMOS data avoids cumbersome operations such as dismantling the chassis of the computer and provides convenience for users.

Example 2

On the basis of Embodiment 1, the delay unit of this embodiment is a 555 delay circuit. Specifically, as shown in FIG. 2 , the 555 delay circuit includes a 555 chip 21 , a first resistor R1 , a second resistor R2 , a capacitor C1 and a power supply VDD. One end of the first resistor R1 is electrically connected to the trigger pin TR of the 555 chip 21, and the other end is electrically connected to the power supply VDD; one end of the second resistor R2 is respectively connected to the trigger pin TR and the threshold pin TH of the 555 chip It is electrically connected to the discharge terminal pin D, and the other end is electrically connected to the power supply VDD; one end of the capacitor C1 is electrically connected to the trigger terminal pin TR of the 555 chip 21, and the other end is grounded; the reset terminal pin RESET of the 555 chip, the power supply voltage The pin VCC and the control voltage terminal pin CT are both electrically connected to the power supply VDD, the output terminal OUT is electrically connected to the input terminal of the switch circuit, the ground pin GND is grounded, and the trigger terminal pin TR is connected to the output terminal of the reset signal output circuit 1 electrical connection.

When the computer crashes, usually by pressing the reset function key to restart the computer without power interruption, because of its function, the position of the reset function key is generally hidden, so as to avoid misoperation, and the reset function key used The number of times is also less, so this embodiment can use the reset function key (of course, it can also be other keys) to generate a reset signal. Since the reset function key needs to realize two functions, it can be distinguished by the length of the pressing time, for example: short press (1s-2s) the reset function key to realize the restart function; long press (10s-15s) the reset function key to generate a reset signal .

The working principle of the CMOS data clearing device of the present embodiment is described below: the input terminal of the reset signal output circuit is electrically connected with the reset function key of the computer. High level, at this time the delay unit outputs low level, and does not clear CMOS data. When the reset function key is pressed for a long time, the reset function key generates a reset signal, that is, the pin of the reset function key outputs a low level to the reset signal output circuit 1, and the reset signal output circuit 1 outputs a low level to the trigger terminal pin TR, At this time, the capacitor C1 is discharged, and when the voltage value across the capacitor C1 drops below 2/3 of the power supply VDD, the 555 delay circuit outputs a high level (this is the first trigger signal) to the switch circuit, and the switch circuit The CMOS data in the CMOS chip can be cleared by outputting a low level (at this time, the second trigger signal) to the CMOS data clearing circuit. When the reset function key is released, the capacitor C1 starts to charge again. When the voltage across the capacitor C1 is higher than 2/3 of the power supply VDD, the delay unit outputs a low level, and the CMOS data is not cleared at this time.

The duration during which the delay unit sends the first trigger signal (that is, the time period during which the delay unit outputs a high level) can be adjusted by adjusting the value of the second resistor R2 and the capacitor C1. In order to facilitate the adjustment of the time period, the The second resistor R2 is set as a sliding rheostat.

In this embodiment, the 555 delay circuit can also include a first diode D1, the anode of the first diode D1 is electrically connected to the power supply VDD, and the cathode is electrically connected to the control voltage terminal pin CT of the 555 chip 21, thus The time for the delay unit to output high level can be extended. Wherein the first diode can be a switching diode whose model is IN4148. It should be noted that the delay unit can also be implemented in other forms, such as a single-chip microcomputer, and is not limited to the 555 delay circuit in this embodiment.

Example 3

On the basis of Embodiment 2, the switching circuit of this embodiment includes an N-channel MOS field effect transistor, as shown in Figure 3, the gate of the N-channel MOS field effect transistor is electrically connected to the output terminal of the 555 chip, The source is grounded, and the drain is electrically connected to the reset terminal RTC_RST_N of the CMOS chip.

In this embodiment, in order to stabilize and protect the switch circuit, the switch circuit further includes a second diode D2 and two reverse-series zener diodes D3; one end of the two reverse-series zener diodes is connected to N The gate of the channel MOS field effect transistor is electrically connected, and the other end is electrically connected to the source of the N channel MOS field effect transistor; the anode of the second diode is electrically connected to the source electrode of the N channel MOS field effect transistor connected, and the cathode is electrically connected to the drain of the N-channel MOS field effect transistor.

The CMOS data clearing circuit includes a fourth resistor R4 and a capacitor C2. One end of the capacitor C2 is grounded, the other end is electrically connected to the fourth resistor R4, the reset terminal RTC_RST_N of the CMOS chip, and the drain of the N-channel MOS field effect transistor, and the other end of the fourth resistor R4 is electrically connected to the built-in power supply VRTC of the motherboard.

Embodiment 2 has explained that when the CMOS data needs to be cleared, the delay unit outputs a high level, at this time the N-channel MOS type field effect transistor is turned on, and the reset terminal RTC_RST_N of the CMOS chip is grounded (that is, RTC_RST_N is powered off) The CMOS data can be cleared.

Example 4

Embodiment 4 is basically the same as Embodiment 3, as shown in Figure 4, the difference is that the switching circuit of this embodiment is realized by an NPN transistor, and the base of the NPN transistor is electrically connected to the output terminal of the 555 chip, in order to prevent The signal control terminal (that is, the base) of the NPN transistor is directly grounded, the base is electrically connected to the output terminal of the 555 chip through the third resistor R3, the emitter of the NPN transistor is grounded, and the collector is electrically connected to the reset terminal RTC_RST_N of the CMOS chip. connect. At this time, one end of the capacitor C2 in the CMOS data clearing circuit is grounded, and the other end is electrically connected to the fourth resistor R4, the reset terminal RTC_RST_N of the CMOS chip, and the collector of the NPN transistor. The function of clearing CMOS data can also be realized by using the clearing of CMOS data in this embodiment.

The utility model also includes a computer, which includes the CMOS data clearing device, the reset function key and the CMOS chip in any of the above-mentioned embodiments, the input end of the reset signal output circuit is electrically connected with the reset function key, and the output end of the CMOS data clearing circuit It is electrically connected with the reset terminal of the CMOS chip; the reset function key is used to generate the reset signal.

Although the specific implementation of the utility model has been described above, those skilled in the art should understand that this is only an example, and the protection scope of the utility model is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principle and essence of the present utility model, but these changes and modifications all fall within the protection scope of the present utility model.

Claims (10)

1. A CMOS data clearing device is characterized in that, said CMOS data clearing device comprises a reset signal output circuit, a delay unit, a switch circuit and a CMOS data clearing circuit electrically connected successively; The reset signal output circuit is used to output a reset signal to the delay unit; The delay unit is configured to continuously send the first trigger signal to the switch circuit within a period of time after receiving the reset signal; The switch circuit is used to send a second trigger signal to the CMOS data clearing circuit after receiving the first trigger signal; The CMOS data clearing circuit is used for clearing the CMOS data of the CMOS chip when receiving the second trigger signal. 2. The CMOS data clearing device according to claim 1, wherein the delay unit comprises any one of a 555 delay circuit or a single-chip microcomputer. 3. CMOS data clearing device as claimed in claim 2, is characterized in that, described 555 time-delay circuits comprise 555 chips, the first resistance, the second resistance, electric capacity and power supply; One end of the first resistor is electrically connected to the trigger pin of the 555 chip, and the other end is electrically connected to the power supply; One end of the second resistor is electrically connected to the trigger pin, the threshold pin and the discharge pin of the 555 chip, and the other end is electrically connected to the power supply; One end of the capacitor is electrically connected to the trigger pin of the 555 chip, and the other end is grounded; The reset terminal pin, power supply voltage pin and control voltage terminal pin of the 555 chip are all electrically connected to the power supply; the output terminal of the 555 chip is electrically connected to the input terminal of the switch circuit; the 555 The ground pin of the chip is grounded. 4. CMOS data clearing device as claimed in claim 3, is characterized in that, described 555 delay circuits also comprise first diode, and the anode of described first diode is electrically connected with described power supply, and cathode It is electrically connected with the control voltage terminal pin of the 555 chip. 5. The CMOS data erasing device according to claim 3, wherein the second resistor is a sliding rheostat. 6. The CMOS data erasing device according to claim 3, wherein the switch circuit comprises an N-channel MOS field effect transistor, and the gate of the N-channel MOS field effect transistor is connected to the 555 chip The output terminal is electrically connected, the source is grounded, and the drain is electrically connected to the reset terminal of the CMOS chip. 7. The CMOS data erasing device as claimed in claim 6, wherein the switch circuit further comprises a second diode and two reverse-series Zener diodes; One end of the two anti-series Zener diodes is electrically connected to the gate of the N-channel MOS field effect transistor, and the other end is electrically connected to the source of the N-channel MOS field effect transistor; The anode of the second diode is electrically connected to the source of the N-channel MOS field effect transistor, and the cathode is electrically connected to the drain of the N-channel MOS field effect transistor. 8. CMOS data clearing device as claimed in claim 3, is characterized in that, described switch circuit comprises NPN type transistor, and the base of described NPN type transistor is electrically connected with the output end of described 555 chip by the 3rd resistor, The emitter is grounded, and the collector is electrically connected to the reset terminal of the CMOS chip. 9. The CMOS data erasing device according to any one of claims 1-8, wherein the first trigger signal is at a high level, and the second trigger signal is at a low level. 10. A kind of computer, comprise reset function key and CMOS chip, it is characterized in that, described computer also comprises CMOS data clearing device as described in any one in claim 1-9, the input end of described reset signal output circuit It is electrically connected with the reset function key, and the output end of the CMOS data clearing circuit is electrically connected with the reset end of the CMOS chip; The reset function key is used to generate the reset signal.