CN206211974U - Straw vote device circuit - Google Patents
Straw vote device circuit Download PDFInfo
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- CN206211974U CN206211974U CN201621080389.6U CN201621080389U CN206211974U CN 206211974 U CN206211974 U CN 206211974U CN 201621080389 U CN201621080389 U CN 201621080389U CN 206211974 U CN206211974 U CN 206211974U
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- 239000010902 straw Substances 0.000 title claims abstract description 26
- 239000013078 crystal Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 238000007600 charging Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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Abstract
The utility model provides straw vote device circuit, and high precision, small power consumption, speed is fast.Including the amplifying unit being connected between supply voltage and output port, and the comparing unit and tail circuit unit for being connected to output port and grounding ports in turn；Described comparing unit includes tie point and the second branch road；Tie point includes n+1 n fet transistor, and the drain terminal of n fet transistors is all connected with output port out, and source is grounded through tail circuit unit, the wherein n input signal of source connection n of n fet transistors, the source ground connection of another n fet transistor；Second branch road includes n+1 n fet transistor, the drain terminal of n fet transistors is all connected with output port out_n, source is grounded through tail circuit unit, the wherein n input inverted signal of source connection n of n fet transistors, the source connection supply voltage of another n fet transistor.
Description
Technical field
The utility model is related to circuit design field, specially straw vote device circuit.
Background technology
Computer and various electronic equipments are widely used in the various aspects of the modern life, and it needs to process and transmits
Data volume it is increasing.From 8 earliest machine systems, 64 bit processors till now.With the increase of system bit wide, system
Power consumption is also increasing.Accordingly in order to reduce power consumption, many algorithms are proposed.One kind of most common of which is meter
The number of " 0 " or " 1 " in transmitting procedure is calculated, data keep constant if " 0 " is in the great majority, otherwise then data are all taken
Instead.And it is accomplished by circuit of voting " 0 " or " 1 " quantity is calculated.
Ballot circuit is divided into two major classes at present：Digital polling device circuit and straw vote device circuit.It is as shown in Figure 1 current
Conventional 8 straw vote circuits；Wherein, x0/x1/...x7 is 8 bit, x0_n/x1_n/ ... x7_n for needing ballot
It is that x0/x1/ ... x7 is negated, en is the enable signal of circuit.
Its operation principle is：1st, x0/x1/ .../x7/x0_n/x1_n/ .../x7_n any one be " 1 ", then its connection
Transistor is opened；Often one transistor of opening just has electric current and flows through；2nd, by comparing the size of current of the left and right sides, then can be with
" 1 " is more over there to judge left and right sides input signal；If the 3, left side " 1 " is more, illustrate x0/x1/ .../x7 in " 1 " account for mostly
Number；If the 4, right side " 1 " is more, illustrate x0_n/x1_n/ .../x7_n in " 1 " be in the great majority, " 0 " accounts for greatly in x0/x1/ .../x7
It is most.
It is all even number data (8/16 .../64) that generally we need the data that compare, thus occur " 0 " and
The number of " 1 " situation as many.In this case, conventional straw vote device all can be by changing left side or right side at present
The size of certain road transistor is so as to allow its electric current and normal through different.Two when can so make " 0 ", " 1 " same case or so
The electric current of side is different so as to the result for being needed.
But the above method needs designer accurately to adjust the size of transistor, and due to difficult in process of production
Exempt to have error.So cause normal straw vote device precision not at present to be very high, or even can an error has occurred.
Utility model content
For problems of the prior art, the utility model provides a kind of straw vote device circuit, high precision, power consumption
Small, speed is fast.
The utility model is to be achieved through the following technical solutions：
Straw vote device circuit, including the amplifying unit between supply voltage and output port is connected to, and connect successively
It is connected on the comparing unit and tail circuit unit of output port and grounding ports；
Described comparing unit includes tie point and the second branch road；
Tie point includes n+1 n-fet transistor, and the drain terminal of n-fet transistors is all connected with output port out, source
It is grounded through tail circuit unit, the wherein n input signal of source connection n of n-fet transistors, another n-fet crystal
The source ground connection of pipe；
Second branch road includes n+1 n-fet transistor, and the drain terminal of n-fet transistors is all connected with output port out_n, source
End is grounded through tail circuit unit, the wherein n input inverted signal of source connection n of n-fet transistors, another n-fet
The source connection supply voltage of transistor.
Preferably, each source for being used for the n-fet transistors for connecting input signal is in series with electric capacity, electricity in comparing unit
Resistance or current source.
Preferably, in comparing unit each be used for connect input inverted signal n-fet transistors source be in series with electric capacity,
Resistance or current source.
Preferably, described tail circuit unit includes tail circuit n-fet transistors；The grid end of tail circuit n-fet transistors
The enable signal en of connection circuit work, source ground connection, drain terminal connection comparing unit.
Preferably, described comparing unit includes that first amplifies branch road and the second amplification branch road；
First amplifies branch road includes that n+1 source connects a p-fet transistors of supply voltage, and n+1 drain terminal
The 2nd p-fet transistors of connection output port out；The drain terminal of the first p-fet transistors and the source of the 2nd p-fet transistors
Connect one to one；Input signal of the grid end of the individual 2nd p-fet transistors of n respectively with n is connected, another the 2nd p-fet
The grid end ground connection of transistor；
Second amplifies branch road includes that n+1 source connects the 3rd p-fet transistors of supply voltage, and n+1 drain terminal
The 4th p-fet transistors of connection output port out_n, the drain terminal of the 3rd p-fet transistors and the source of the 4th p-fet transistors
End connects one to one；The grid end of n the 3rd p-fet transistor is connected with the input inverted signal of n respectively, another the 2nd p-
The grid end connection supply voltage of fet transistors；
The grid end of the first p-fet transistors and the 3rd p-fet transistors is connected with output port out.
Preferably, described comparing unit compares p-fet transistors including first, second, third and fourth, and first and second compares
N-fet transistors；
First and second source for comparing p-fet transistors is all connected with supply voltage, and drain terminal is all connected with first and compares n-fet crystalline substances
The drain terminal of body pipe, the first grid end connection for comparing p-fet transistors enables signal en, and second compares the grid end of p-fet transistors
The drain terminal of n-fet transistors is compared in connection second；The first source connection output port out for comparing n-fet transistors, grid end connects
Connect the second drain terminal for comparing n-fet transistors；
The source connection supply voltage of third and fourth comparing p-fet transistors, drain terminal is all connected with second and compares n-fet crystal
The drain terminal of pipe, the 4th grid end connection for comparing p-fet transistors enables signal en, and the 3rd grid end for comparing p-fet transistors connects
Connect the first drain terminal for comparing n-fet transistors；The second source connection output port out_n for comparing n-fet transistors, grid end connects
Connect the first drain terminal for comparing n-fet transistors.
Compared with prior art, the utility model has following beneficial technique effect：
The utility model, and will be increased by the one group of path of each side increase in existing straw vote circuit
Path is opened side using the control of grid end all the time, and opposite side is closed all the time, when input " 0 ", " 1 " quantity phase simultaneously as
Above-mentioned increased path is so there is the electric current difference of path all the way left and right；Ballot can be rapidly performed by judge, high precision,
Small power consumption, speed is fast.
Further, by the setting in different amplifying units, enable to only be retained as discharging on integrated circuit leading to
The n-fet pipe paths on road, it is ensured that while precision, reduce circuit overall volume.
Further, circuit is reduced by the series capacitance under n-fet transistors or resistance or current source to work
When electric current, reduce its operating power consumption.
Brief description of the drawings
Fig. 1 is a kind of 8 straw vote circuit structure diagrams of the prior art.
Fig. 2 is the straw vote circuit structure diagram described in the utility model example 1.
Fig. 3 is the straw vote circuit structure diagram described in the utility model example 2.
Fig. 4 is the straw vote circuit structure diagram described in the utility model example 3.
In figure：X0/x1 .../x7 is input signal；X0_n/x1_n/ .../x7_n is negated for x0/x1/ .../x7.
Specific embodiment
The utility model is described in further detail with reference to specific embodiment, described is to the utility model
Explanation rather than restriction.
Example 1
The utility model is as shown in Fig. 2 by taking the input signal of 8 as an example, that is, n=8；Wherein, enabling signal en is
Circuit operating switch, en=1 starts working, and en=0 closes circuit；Output port out is exported for circuit comparative result；Output end
Mouth out_n is negated for out.
The input signal of ballot will be needed：
The grid end mouthful of x0/x1/ ... x7 connection n-fet N0/N1 ... N7 and p-fet P8/P9 .../P15；
The drain terminal connection circuit output port out of n-fet N0/N1 ... N7 and p-fet P8/P9 ... P15；
The source of p-fet P8/P9 ... P15 connects the drain terminal of p-fet P0/P1 ... P7 respectively；
The source of p-fet P0/P1 ... P7 is connected to supply voltage；
The input inverted signal of ballot will be needed：X0_n/x1_n/ ... x7_n connection n-fet N0 '/N1 ' ... N7 ' and p-fet
The grid end mouthful of P8 '/P9 ' .../P15 '；
The drain terminal connection circuit output port out_n of n-fet N0 '/N1 ' ... N7 ' and p-fet P8 '/P9 ' ... P15 '；
The source of p-fet P8 '/P9 ' ... P15 ' connects the drain terminal of p-fet P0 '/P1 ' ... P7 ' respectively；
The source of p-fet P0 '/P1 ' ... P7 ' is connected to supply voltage；
The grid end of p-fet P0/P1 ... P7/P0 '/P1 ' ... P7 ' is connected to output port out；
The enable signal en of circuit work is connected to the grid end of tail circuit n-fet；
The drain terminal of tail circuit n-fet is connected to the source of all input n-fet (N0/N1 ... N7/N0 '/N1 ' ... N7 ')；
The source of tail circuit n-fet is connected to ground terminal.
The utility model realizes Heng Guan, p-fet by increased two groups of paths, the grid end ground connection of one of which n-fet Nd
The grid end of Pd1 meets out, and the grid end ground connection correspondence of p-fet Pd2 realizes Heng Guan；Another group of grid termination power electricity of n-fet Nd '
Pressure realizes that perseverance is opened, and p-fet Pd1 ' grid ends meet out, and the grid end of p-fet Pd2 ' connects supply voltage correspondence and realizes that perseverance is opened.
Straw vote circuit described in the present embodiment operationally, due to each side increasing by one group of current path；
But the path of both sides charges to output port out all the time on one side, other side is discharged to output port out_n all the time, such as Fig. 2
Shown left side is closed, and right side is opened；It is left by Fig. 2 circuits if there is 4 " 1 " 4 " 0 " in input data x0/x1 .../x7
Side has 5 paths to give out chargings 4 electric discharges, and right side has 4 paths to give out_n chargings 5 electric discharges；Out and out_n voltages are not
Equally judge more than 1 or more than 0,0 number of the number more than or equal to 1 if the voltage of the voltage more than out_n of out, such as
The voltage of fruit out less than out_n voltage then 0 number less than 1 number；Because the utility model straw vote device need not
Electric current is judged by adjusting transistor size, so precision is very high.
Example 2
Straw vote circuit described in Case-based Reasoning 1 can further be optimized to it, as shown in figure 3, only with
N-fet transistor paths.
Need the input signal of ballot：The grid end mouthful of x0/x1/ ... x7 connection n-fet N0/N1 ... N7；
Need the input inverted signal of ballot：The grid end of x0_n/x1_n/ ... x7_n connection n-fet N0 '/N1 ' ... N7 '；
Fig. 3 is only retained as the n-fet paths of discharge path, and output signal out/ is determined by the number of discharge path
The voltage of out_n.
Example 3
Straw vote circuit described in Case-based Reasoning 2 can further be optimized to it, as shown in figure 4, we can
To reduce the operating current of straw vote device, following circuit can be optimized to, an electricity of being connected under each n-fet transistor
Hold；Or a resistance of being connected under each n-fet transistor；Or a current source of being connected under each n-fet transistor；Or each n-
Any one under fet transistors in series electrical perhaps resistance or current source.
Claims (6)
1. straw vote device circuit, it is characterised in that including the amplifying unit being connected between supply voltage and output port, with
And it is connected to the comparing unit and tail circuit unit of output port and grounding ports in turn；
Described comparing unit includes tie point and the second branch road；
Tie point includes n+1 n-fet transistor, and the drain terminal of n-fet transistors is all connected with output port out, and source is passed through
Tail circuit unit is grounded, the wherein n input signal of source connection n of n-fet transistors, another n-fet transistor
Source is grounded；
Second branch road includes n+1 n-fet transistor, and the drain terminal of n-fet transistors is all connected with output port out_n, and source is equal
It is grounded through tail circuit unit, the wherein n input inverted signal of source connection n of n-fet transistors, another n-fet crystal
The source connection supply voltage of pipe.
2. straw vote device circuit according to claim 1, it is characterised in that each is used to connect and is input into comparing unit
The source of the n-fet transistors of signal is in series with electric capacity, resistance or current source.
3. straw vote device circuit according to claim 1, it is characterised in that each is used to connect and is input into comparing unit
The source of the n-fet transistors of inverted signal is in series with electric capacity, resistance or current source.
4. straw vote device circuit according to claim 1, it is characterised in that described tail circuit unit includes tail circuit
N-fet transistors；The enable signal en of the grid end connection circuit work of tail circuit n-fet transistors, source ground connection, drain terminal connection
Comparing unit.
5. straw vote device circuit according to claim 1, it is characterised in that described comparing unit includes that first amplifies
Branch road and second amplifies branch road；
First amplifies branch road includes that n+1 source connects a p-fet transistors of supply voltage, and n+1 drain terminal connection
The 2nd p-fet transistors of output port out；The drain terminal of the first p-fet transistors and the source of the 2nd p-fet transistors are one by one
Correspondence connection；The n grid end of the 2nd p-fet transistors is connected respectively at the input signal of n, another the 2nd p-fet crystal
The grid end ground connection of pipe；
Second amplifies branch road includes that n+1 source connects the 3rd p-fet transistors of supply voltage, and n+1 drain terminal connection
The 4th p-fet transistors of output port out_n, the drain terminal of the 3rd p-fet transistors and the source one of the 4th p-fet transistors
One correspondence connection；The grid end of n the 3rd p-fet transistor is connected with the input inverted signal of n respectively, another the 2nd p-fet
The grid end connection supply voltage of transistor；
The grid end of the first p-fet transistors and the 3rd p-fet transistors is connected with output port out.
6. straw vote device circuit according to claim 1, its feature including first and second with, described comparing unit,
3rd, four compare p-fet transistors, and first and second compares n-fet transistors；
First and second source for comparing p-fet transistors is all connected with supply voltage, and drain terminal is all connected with first and compares n-fet transistors
Drain terminal, first compare p-fet transistors grid end connection enable signal en, second compare p-fet transistors grid end connection
Second drain terminal for comparing n-fet transistors；The first source connection output port out for comparing n-fet transistors, grid end connection the
Two drain terminals for comparing n-fet transistors；
The source connection supply voltage of third and fourth comparing p-fet transistors, drain terminal is all connected with second and compares n-fet transistors
Drain terminal, the 4th grid end connection for comparing p-fet transistors enables signal en, and the 3rd compares the grid end connection the of p-fet transistors
One drain terminal for comparing n-fet transistors；The second source connection output port out_n for comparing n-fet transistors, grid end connection the
One drain terminal for comparing n-fet transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621080389.6U CN206211974U (en) | 2016-09-26 | 2016-09-26 | Straw vote device circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621080389.6U CN206211974U (en) | 2016-09-26 | 2016-09-26 | Straw vote device circuit |
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| Publication Number | Publication Date |
|---|---|
| CN206211974U true CN206211974U (en) | 2017-05-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621080389.6U Withdrawn - After Issue CN206211974U (en) | 2016-09-26 | 2016-09-26 | Straw vote device circuit |
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| CN (1) | CN206211974U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106301353A (en) * | 2016-09-26 | 2017-01-04 | 西安紫光国芯半导体有限公司 | A kind of straw vote device circuit |
-
2016
- 2016-09-26 CN CN201621080389.6U patent/CN206211974U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106301353A (en) * | 2016-09-26 | 2017-01-04 | 西安紫光国芯半导体有限公司 | A kind of straw vote device circuit |
| CN106301353B (en) * | 2016-09-26 | 2024-05-03 | 西安紫光国芯半导体有限公司 | Analog voter circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 4/F, Building A, Tengfei Innovation Center, No. 38 Gaoxin 6th Road, Xi'an City, Shaanxi Province, 710075 Patentee after: Xi'an Ziguang Guoxin Semiconductor Co.,Ltd. Country or region after: China Address before: 4/F, Building A, Tengfei Innovation Center, No. 38 Gaoxin 6th Road, Xi'an City, Shaanxi Province, 710075 Patentee before: XI''AN UNIIC SEMICONDUCTORS Co.,Ltd. Country or region before: China |
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| CP03 | Change of name, title or address | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20170531 Effective date of abandoning: 20240503 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20170531 Effective date of abandoning: 20240503 |
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| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |