CN206162517U - Preprocessing circuit based on FPGA realizes JESD204B interface - Google Patents

Abstract

The utility model relates to the technical field of medical equipment, in particular to a preprocessing circuit based on an FPGA to realize a JESD204B interface, including an FPGA chip, a 100MHz differential signal crystal oscillator, a 125MHz differential signal crystal oscillator, and a DDR3 SDRAM module. The 100MHz crystal oscillator and the 125MHz crystal oscillator are respectively It is connected to the clock pin of FPGA, and the DDR3 SDRAM module is connected to the high-speed IO interface of the FPGA chip; inside the FPGA is a multi-channel selection unit, a SERDES interface processing unit, a multi-channel synchronous detection unit, and a multi-channel descrambling code processing unit. Unit, multi-channel data reorganization unit, DDR3 SDRAM control unit, PCIE interface processing unit. This circuit can meet the needs of data transmission with different capacities, and provide effective data to the back-end equipment for further data analysis and processing.

Description

Realize the preprocessing circuit of JESD204B interface based on FPGA

technical field

The utility model relates to the technical field of data communication, in particular to a preprocessing circuit for realizing a JESD204B interface based on FPGA.

Background technique

JESD204B is a new industry standard for internal high-speed interconnection of data converters and logic devices. It is an interface for high-speed data acquisition and is currently mainly used for the connection between ADCs and FPGAs. It can support multi-channel synchronous and serial data transmission up to 12.5Gb/s. In order to realize the processing of the JESD204B interface, it is not only expensive to choose a dedicated chip, but also the function is not flexible enough to meet the special application requirements.

Utility model content

The purpose of this utility model is to overcome the deficiency of above-mentioned technology, and provide a kind of preprocessing circuit based on FPGA to realize JESD204B interface.

In order to achieve the above object, the utility model adopts the following technical solutions:

A preprocessing circuit based on FPGA to realize JESD204B interface is characterized in that: comprising 1 FPGA chip, 1 100MHz differential signal crystal oscillator, 1 125MHz differential signal crystal oscillator, 1 piece of DDR3 SDRAM module group, described 100MHz crystal oscillator and 125MHz crystal oscillator respectively It is connected with the clock pin of FPGA, and the DDR3SDRAM module is connected with the high-speed IO interface of the FPGA chip; inside the FPGA is a multi-channel selection unit, a SERDES interface processing unit, a multi-channel synchronous detection unit, and a multi-channel descrambling code processing unit , multi-channel data reorganization unit, DDR3SDRAM control unit, and PCIE interface processing unit to complete the data reception of the JESD204B interface and the data transmission of the PCIE interface.

Preferably, the DDR3 SDRAM module adopts the MT8JTF12864HZ-1G6G1 chip of Micron Company.

Preferably, the FPGA chip is an XC7VX485T chip of Xilinx Company.

The beneficial effects of the utility model are: compared to the prior art, the high-speed ADC device of the wireless communication system connects the multi-channel JESD204B signal to the JESD204B signal input terminal of the circuit through an external interface, and the circuit realizes that the input is 1 to 8 single The channel is 5G effective signal, the selection and combination of the channel signal with the highest transmission bandwidth of 40G, completes the preprocessing of the acquisition signal under different transmission bandwidth, and sends the processed data through the PCIE interface of this circuit, and can be connected through the PCIE interface Into the host computer and other back-end processing equipment. It can meet the needs of data collection and transmission with different capacities, and provide effective data to the back-end equipment for further data analysis and processing.

Description of drawings

Figure 1 is the overall connection circuit diagram of the hardware;

Figure 2 is a circuit diagram of the internal functional modules of the FPGA chip.

detailed description

The specific implementation of the utility model will be described in detail below in conjunction with the accompanying drawings and preferred embodiments.

In describing the present invention, it should be understood that the terms "central", "longitudinal", "transverse", "front", "rear", "left", "right", "vertical", "horizontal" , "top", "bottom", "inner", "outer" and other indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the utility model and simplifying the description, rather than indicating or It should not be construed as limiting the invention by implying that a referenced device or element must have a particular orientation, be constructed, and operate in a particular orientation.

Referring to Figure 1 and Figure 2, a preprocessing circuit based on FPGA to realize JESD204B interface, the preprocessing circuit is used to realize the reception of 1 to 8 JESD204B channel signals, and complete the transmission of PCIE interface data. FPGA chip is composed of multi-channel selection unit, SERDES interface processing unit, multi-channel synchronous detection unit, multi-channel descrambling code processing unit, multi-channel data reorganization unit, DDR3SDRAM control unit, PCIE interface processing unit, and completes the data reception of JESD204B interface Data transmission with PCIE interface.

The multi-channel selection unit mainly completes the selection of 1 to 8 JESD204B channel signals. The JESD204B interface can process up to 8 parallel JESD204B signals, receive channel selection instructions through the SPI interface, and then send the analyzed channel selection enable signal to the multi-channel synchronization The detection unit and the multi-channel data recombination unit are used as judgment signals.

The SERDES interface unit is connected to 8 JESD204B channel input signals, calls the high-speed SERDES IP core inside the FPGA, and mainly completes the serial-to-parallel conversion of each channel and the decoding processing of 8B10B data. The single-channel 5G signal is decoded from 8B10B data into 4G effective data, and then converted into 32-bit parallel data with a clock frequency of 125MHz.

The multi-channel synchronous detection unit includes 8 channel synchronous detection subunits, which respectively perform synchronous detection on each channel. In the initial state, each channel searches the byte synchronization character K28.5 in the code stream of the channel, and enters the byte synchronization state of the code group after searching for 4 synchronization characters continuously. Then search the channel synchronization start character K28.0 in the channel code stream to enter the channel synchronization state. Then continue to search for the channel synchronization end character K28.3, enter the normal data receiving state, start to receive effective sampling data streams, and provide a single-channel initialization completion signal at the same time. According to the synchronization completion status of each channel, combined with the channel selection enable signal to judge, a system initialization completion signal is generated. When all the channel judgment signals jump to the effective level within a certain period of time, it marks the completion of the synchronization status of each channel in the system, otherwise When the channel enters the idle state, the system resets again, and each channel continues to search for flag characters in the code stream for status judgment.

In the normal data receiving state, the multi-channel storage FIFO is controlled to read and write data, and the data alignment operation of the effective channel is completed. The multi-channel storage FIFO is composed of 8 sub-unit FIFOs. The FIFO read and write enable signal is generated by the multi-channel synchronous detection unit. The initialization signal of each channel is used as the write enable signal, and the system initialization completion number is used as the read enable signal to control the data read and write operations of each FIFO respectively to ensure that the FIFO reads data Synchronously align data for each channel of the system.

The multi-channel descrambling code processing unit includes 8 channel descrambling code processing sub-units to complete 32-bit parallel descrambling code processing of each channel signal, and the scrambling code sequence is X15+X14+1. The input is a 32-bit parallel self-synchronizing scrambling signal, and the output is a 32-bit parallel descrambling signal.

The multi-channel data reorganization unit completes the recombination of 8 channel signals. According to the channel selection enable signal, a maximum of 8 channels of 256-bit parallel signals and a minimum of 1 channel of 32-bit parallel signals are rearranged in order to restore the data of the original collected signals. The multi-channel reorganization unit controls the code rate adjustment FIFO to complete the buffer processing of data in different clock domains. The code rate adjustment FIFO is composed of dual-port RAM, the write clock is 125MHz, the read clock is 200MHz, and the 200MHz clock is passed through the digital lock by the 100MHz clock inside the FPGA. Phase loop (DPLL) module frequency multiplication generation. The multi-channel data reorganization unit generates read and write control instructions to realize the transition processing of data from the 125MHz clock domain to the 200MHz clock domain.

The DDR3SDRAM control unit completes the control of the external DDR3SDRAM storage module. The storage capacity of the storage module is 1GB. It mainly completes the cache processing of sending and receiving data to increase the cache data capability of the PCIE interface. The written data is the output signal of the multi-channel data reorganization unit, and the read signal is sent to the PCIE interface processing unit.

The PCIE interface processing unit mainly includes a PCIE IP core control subunit and a chained DMA data processing subunit. The PCIE IP core control subunit completes the read and write control of the PCIE data frame, the chained DMA data processing subunit responds in time to the commands sent by the host computer, configures the status register and collects data in the chained DMA mode for PCIE data Framing. The above is only a preferred embodiment of the utility model, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the utility model, some improvements and modifications can also be made, these improvements and Retouching should also be regarded as the scope of protection of the present utility model.

Claims (3)

1. a kind of pretreatment circuit that JESD204B interfaces are realized based on FPGA, it is characterised in that：Including 1 fpga chip, 1 100MHz differential signal crystal oscillators, 1 125MHz differential signal crystal oscillators, 1 piece of DDR3SDRAM module, the 100MHz crystal oscillators and 125MHz crystal oscillators are connected respectively with the clock pins of FPGA, and the DDR3SDRAM modules connect with the high-speed I/O interface of fpga chip Connect；By multi-center selection unit, SERDES interface processing units, multi-channel synchronous detector unit, multichannel inside the FPGA Descrambling code processing unit, multi-channel data recomposition unit, DDR3SDRAM control units, PCIE interface processing units composition, complete The data receiver of JESD204B interfaces and the data is activation of PCIE interfaces.

2. a kind of pretreatment circuit that JESD204B interfaces are realized based on FPGA according to claim 1, it is characterised in that： The DDR3SDRAM modules adopt the MT8JTF12864HZ-1G6G1 chips of Micron companies.

3. a kind of pretreatment circuit that JESD204B interfaces are realized based on FPGA according to claim 1, it is characterised in that： The fpga chip adopts the XC7VX485T chips of Xilinx companies.