CN205881909U - Novel normal pass type III -V heterojunction field effect transistor - Google Patents

Abstract

The utility model provides a novel normally-off type III-V heterojunction field effect transistor, comprising a substrate material layer, a second semiconductor layer, a dielectric template layer, a drain electrode, a source electrode, a first dielectric layer, and a second dielectric layer And the gate electrode, the second semiconductor layer and the first semiconductor layer body are combined to form a heterojunction channel, the dielectric template layer is arranged on the first semiconductor layer body and n windows are formed at equal intervals, and the first semiconductor layer body is along the n n windows are grown to form n raised parts; the raised parts make the first semiconductor layer exceed the critical thickness so as to form a two-dimensional electron gas 2DEG in the projection area of the raised parts. Compared with the prior art, the utility model uses a specially designed barrier layer to obtain a discontinuous channel, and the gate electrode completely covers the channel between the source and drain electrodes, thereby realizing the complete two-dimensional electron gas of the channel. Control can avoid the "current collapse" effect of the device; at the same time, the device can obtain higher breakdown voltage and cut-off frequency at the same time.

Description

A Novel Normally-Off III-V Heterojunction Field-Effect Transistor

technical field

The utility model relates to the technical field of semiconductor devices, in particular to a novel normally-off type III-V heterojunction field effect transistor.

Background technique

Binary or ternary compounds (even multi-component compounds) composed of some III and V elements have spontaneous polarization and piezoelectric polarization effects. When they are combined to form a heterojunction (such as AlGaN/GaN), it will A high-concentration two-dimensional electron gas (2DEG) is formed at the interface of the heterojunction, and the device with the 2DEG at the heterojunction interface as the conductive mechanism is called a heterojunction field effect transistor (HFET), which can also be called a high electron Mobility Transistors (HEMTs).

HFET devices have the characteristics of high electron mobility, high device operating frequency and high efficiency. It has very important application prospects in the field of microwave power emitter transmission and power electronics. However, so far, there is a natural shortcoming in HFET devices. Taking AlGaN/GaN HFET as an example, due to the strong spontaneous polarization and piezoelectric polarization, the heterojunction interface is formed without any external voltage. With a high concentration of 2DEG, the HFET device is naturally normally on (depleted). The defects of HFET devices limit the application of devices in logic circuits and power electronic circuits. The former requires normally-off and normally-on logic complements, while the latter requires normally-off devices for safety and energy-saving considerations. .

In the prior art, in order to realize a normally-on HFET device, there are usually the following ways to obtain it:

Under-gate channel F ion implantation technology: that is, negative ions of F are implanted into the barrier layer under the gate, and the channel electrons under the gate are depleted by negative potential to realize the positive threshold of the device (enhanced type).

Groove gate technology: Use dry etching technology to thin the barrier layer under the gate. When the thickness is lower than the critical thickness, the 2DEG under the gate will be depleted. 2DEG is re-induced only when the gate voltage is higher than a certain voltage. An enhanced device is realized.

The device using the P-AlGaN layer, this device adds a layer of P-AlGaN layer under the gate, due to the equalization of the energy band, the 2DEG of the channel is depleted.

The above several technologies have different disadvantages. Among them, the F ion implantation technology has problems in terms of reliability and obtaining a large threshold, the trench gate technology has great difficulties in process control, and the P-AlGaN technology has difficulties in material growth and device switching. Disadvantages such as low frequency.

In addition, in existing devices, since the gate electrode only covers part of the channel, the gate voltage cannot control the channel between the gate and drain electrodes. When the device changes from the "off" state to the "on" state, due to the "virtual gate effect", the channel between the gate and the drain cannot be opened in time, resulting in an increase in channel resistance, thereby forming a "current collapse" effect.

Therefore, in view of the above-mentioned defects existing in the current prior art, it is necessary to conduct research to provide a solution to solve the defects existing in the prior art.

Utility model content

In view of this, the object of the present invention is to provide a novel normally-off III-V heterojunction field effect transistor to solve the above problems.

A novel normally-off type III-V heterojunction field effect transistor, comprising a substrate material layer, a second semiconductor layer, a dielectric template layer, a drain electrode, a source electrode, a first dielectric layer, a second dielectric layer and a gate electrode, in,

forming the second semiconductor layer on the substrate material layer, and forming a drain electrode and a source electrode on the second semiconductor layer;

The first semiconductor layer includes a body and n raised portions grown along the body, where n≥1;

The second semiconductor layer and the first semiconductor layer body are combined to form a heterojunction channel, and the two ends of the heterojunction channel are respectively connected to the drain electrode and the source electrode; the thickness of the first semiconductor layer body is not greater than the critical thickness for forming two-dimensional electron gas 2DEG on the heterojunction channel, so that the natural two-dimensional electron gas 2DEG in the heterojunction channel is depleted;

The dielectric template layer is disposed on the first semiconductor layer body and forms n windows at equal intervals, and the first semiconductor layer body grows along the n windows to form the n protrusions; the protrusions Partially make the first semiconductor layer exceed the critical thickness to form a two-dimensional electron gas 2DEG in the projected area of the raised portion, and form n equally spaced two-dimensional electron gas 2DEG regions on the heterojunction channel;

The surface of the first semiconductor layer is also provided with a first dielectric layer, the gate electrode is provided on the first dielectric layer, the gate electrode covers the entire channel length, and the two edges of the gate electrode extend beyond The drain electrode and the source electrode are close to the edge of the channel side, and the second dielectric layer is provided between the gate electrode and the drain electrode and the source electrode.

Preferably, the protruding parts are distributed continuously or divided into m parts along the growth direction thereof, where m≥1.

Preferably, the second dielectric layer is only located at an edge portion where the gate electrode overlaps with the drain electrode and the source electrode.

Preferably, an insertion layer for improving the mobility of two-dimensional electron gas at the heterojunction interface is further provided between the first semiconductor layer and the second semiconductor layer, and the insertion layer is an AlN layer.

Preferably, the first semiconductor layer is an AlGaN layer; the second semiconductor layer is a GaN layer.

Preferably, the first semiconductor layer is an AlN layer, and the second semiconductor layer is a GaN layer.

Preferably, the first dielectric layer is Si ₃ N ₄ grown in situ when growing heterostructure materials, and its thickness is 5-25 nm.

Preferably, the dielectric template layer is a SiO ₂ layer grown by LPCVD.

Preferably, the second dielectric layer is a SiO ₂ layer.

Preferably, the edge of the second dielectric layer towards the channel side exceeds the length of the drain electrode and the source electrode respectively by 0.5 μm.

Compared with the prior art, the new normally-off III-V heterojunction field effect transistor provided by the utility model uses a specially designed barrier layer to obtain a discontinuous channel, and uses a high gate voltage to re-induce 2DEG, thereby realizing Normally off device with stable performance. And according to the performance requirements of the device, flexible and diverse design schemes can be adopted.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a novel normally-off III-V heterojunction field effect transistor of the present invention.

Fig. 2 is the utility model new normally-off type III-V heterojunction field effect transistor, when n=2, m=1, the first

Left side view of the semiconductor and second semiconductor parts and the dielectric template part.

Fig. 3 is a new normally-off type III-V heterojunction field effect transistor of the utility model, when n=2, m=1, the first

Front view of the semiconductor and second semiconductor parts and the dielectric template part.

Fig. 4 is a novel normally-off type III-V heterojunction field effect transistor of the present invention, when n=2, m=1, the first

Top view of the semiconductor and second semiconductor portions and the dielectric template portion.

Label description:

Substrate material layer 1, second semiconductor layer 2, first semiconductor layer body 3, raised portion 4 of the first semiconductor layer, two-dimensional electron gas 5, dielectric template 6, first dielectric layer 7, second dielectric layer 8, Gate electrode 9 , source electrode 10 , drain electrode 11 .

detailed description

The following are specific embodiments of the utility model and in conjunction with the accompanying drawings, the technical solution of the utility model is further described, but the utility model is not limited to these embodiments.

Aiming at the defects existing in the prior art, the applicant conducted in-depth research on the structure of the HFET device in the prior art, and the applicant found that the barrier layer of the conventional device, that is, the thickness of the first semiconductor layer exceeds the critical thickness, so the In the case of any external voltage, due to the piezoelectric polarization and spontaneous polarization of the material system, there is a high concentration of two-dimensional electron gas 2DEG at the heterojunction interface, that is, the interface between the first semiconductor and the second semiconductor. In order to obtain a normally-off device, special processes such as trench gate and F ion implantation doping must be used. These processes have the disadvantage of being difficult to control accurately. In addition, the groove gate structure has damage to the device channel due to the etching process used in the process. Therefore, there is damage to the performance of the device. There must be hidden dangers. The F injection process is difficult to precisely control, and there are hidden dangers in terms of reliability.

In order to overcome the above shortcomings, the utility model proposes a novel normally-off type III-V heterojunction field effect transistor, as shown in Fig. 1, Fig. 2, Fig. 3 and Fig. 4, wherein Fig. 1 is a schematic cross-sectional view of the device, and Fig. 2- to FIG. 4 are three views of the first semiconductor, the second semiconductor, and the dielectric template when n=2, m=1, wherein FIG. 2 is a left view, FIG. 3 is a front view, and FIG. 4 is a top view. The utility model's new normally-off type III-V heterojunction field effect transistor comprises a substrate material layer 1, a second semiconductor layer 2, a first semiconductor layer body 3, a raised portion 4 of the first semiconductor layer, and a two-dimensional electron gas 5 , a dielectric template 6, a first dielectric layer 7, a second dielectric layer 8, a gate electrode 9, a source electrode 10, and a drain electrode 11.

Wherein, the second semiconductor layer 2 is formed on the substrate material layer 1, the drain electrode 11 and the source electrode 10 are constructed on the second semiconductor layer 2, and the first semiconductor layer body 3 is formed on the second semiconductor layer 2. A semiconductor layer body 3 is combined with the second semiconductor layer 2 to form a heterostructure; the drain electrode 11 and the source electrode 10 are connected through a channel formed between the first semiconductor layer body 3 and the second semiconductor layer 2; the first The semiconductor layer has a larger forbidden band width than the second semiconductor layer; the thickness of the body 3 of the first semiconductor layer is not greater than the critical thickness for forming a two-dimensional electron gas 2DEG on the heterostructure.

Construct a dielectric template layer 6 on the first semiconductor layer body 3, and form n windows at equal intervals on the dielectric template layer 6, and the first semiconductor layer body 3 grows along the n windows to form the n protrusions 4. The raised portion causes the first semiconductor layer to exceed the critical thickness so as to form a two-dimensional electron gas 2DEG in the projection area of the raised portion, and form n equally spaced two-dimensional electron gas on the heterojunction channel 2DEG region.

If there is only the first semiconductor layer body 3, the heterostructure is not enough to generate two-dimensional electron gas 2DEG; The total thickness of exceeds the critical thickness capable of generating the two-dimensional electron gas 2DEG, so the two-dimensional electron gas 2DEG exists at the heterojunction interface below the first semiconductor protruding portion 4 . Furthermore, at the heterojunction interface, a discontinuous two-dimensional electron gas 2DEG is distributed. Due to the discontinuity of the two-dimensional electron gas 2DEG, when there is no gate voltage, the conductive channel is not formed and the HFET device is normally off. Only when the gate voltage is greater than the threshold voltage, the two-dimensional electron gas 2DEG at the heterojunction interface will continue to form a conductive channel.

With the above-mentioned technical solution, the gate electrode of the device realizes full coverage of the channel between the source and the drain, so when the device is working, the gate voltage can completely control the channel and realize the instantaneous switching of the channel, so the channel can be maximized Avoid the "current collapse" effect.

In addition, although the gate electrode of this device is covered between the source and drain electrodes, since the two-dimensional electron gas in the raised part of the first semiconductor often exists, the equivalent gate length of the device is only The length of the starting part, so the device obtains a higher cut-off frequency. At the same time, since the breakdown voltage of the device is positively correlated with the length between the source and drain electrodes, the device can obtain a higher breakdown voltage at the same time.

The surface of the first semiconductor layer is also provided with a first dielectric layer 7, on which a gate electrode 9 is provided, the gate electrode 9 covers the entire channel length and the two edges of the gate electrode 9 extend beyond the drain electrode 11 and the source electrode 11 respectively. The electrode 10 is close to the edge of the channel side, and the second dielectric layer 8 is provided between the gate electrode 9 , the drain electrode 11 and the source electrode 10 . Due to the use of a channel structure completely covered by the gate electrode, complete control of the gate voltage on the channel 2DEG is realized, thereby realizing a device without current collapse effect.

In a preferred implementation manner, in the direction perpendicular to the connection between the source and drain electrodes, the raised portion 4 of the first semiconductor layer may be continuously distributed, or may be divided into m parts. The dielectric layer template 6 is discontinuous in the direction between the source and drain electrodes.

In a preferred embodiment, the second dielectric layer 8 is only located at the edge portion where the gate electrode 9 overlaps with the drain electrode 11 and the source electrode 10 . The purpose of the second dielectric layer 8 is to prevent the electrical connection between the gate electrode 9 and the drain electrode 11 and the source electrode 10, but the second dielectric layer 8 will affect the gate capacitance, thereby affecting the gate control capability and amplification capability. This structure makes the second dielectric layer 8 only cover the overlapping edge portion of the gate electrode 9 and the drain electrode 11 and the source electrode 10, compared with the second dielectric layer completely covering the first dielectric layer, under the premise of achieving good electrical isolation , can ensure a larger gate capacitance, have a larger device transconductance, and make the device have a greater gate control capability and amplification capability. Preferably, the thickness of the second dielectric layer should be as small as possible. Thus, under the orthographic projection of the gate, there is very little second dielectric layer, minimizing the reduction in gate capacitance.

At the same time, the realization process of the enhanced III-V heterojunction field effect transistor of the utility model is basically the same as that of the prior art HFET device, without additionally increasing the complexity of the device process. The device of the present utility model can be realized through the following main process steps: (1) substrate material growth: on a suitable substrate material (such as Si substrate), grow a corresponding buffer layer, a second semiconductor layer, a selective The insertion layer, the first semiconductor layer body 3 and the dielectric template layer 6 are grown. (2) Perform photolithography and etching on the dielectric template layer to form growth windows for the raised portion 4 of the first semiconductor layer. (3) Growing the raised portion 4 of the first semiconductor layer. (4) Source-drain electrode structure. (5) Growth of the first dielectric layer. (4) Growth of the second dielectric layer and selective etching. (5) Gate electrode structure. (6) Passivation and packaging.

With the above technical solution, a normally-off device can be realized; and, since the channel material of the device is grown without the etching process used in the trench gate device, it will not cause damage to the heterojunction interface, thereby having Helps improve device performance.

Embodiment 1: The novel normally-off III-V heterojunction field effect transistor of this embodiment includes the following parts: the substrate material includes Si material and a low-temperature AlN buffer layer grown thereon, and the second semiconductor layer is a GaN material layer (about 2 μm in thickness), the first part of the first semiconductor layer is an AlGaN layer (about 3 nm in thickness), and an AlN insertion layer (about 1 nm in thickness) is provided between the first semiconductor layer and the first part of the second semiconductor layer, Used to improve the electrical properties of 2DEG. The dielectric template layer is a SiO ₂ layer grown by LPCVD (low pressure chemical vapor deposition method). The length in the direction in which the source and drain electrodes are connected is 100 μm. The first dielectric layer is an in-situ grown Si3N4 layer with a thickness of about 10nm, and the second dielectric layer is hfO ₂ with a thickness of 100nm. Both source and drain electrodes are formed by Ti/Al/Ni/Au (20/120/50/200nm) through metal deposition and high temperature thermal annealing. The distance between the source and drain electrodes was 2.5 μm. The length of the edge of the second dielectric layer toward the center of the channel beyond the source and drain electrodes is 0.5 μm. The gate electrode uses Ni/Au (50/150nm).

Embodiment 2: The novel normally-off III-V heterojunction field effect transistor of this embodiment includes the following parts: the substrate material includes SiC material and a low-temperature AlN buffer layer grown thereon, and the second semiconductor layer is a GaN material layer (about 2 μm in thickness), and the first part of the first semiconductor layer is an AlN layer (about 3 nm in thickness). The dielectric template layer is a _SiO2 layer grown by LPCVD, on which the value of the window is n=2, m=3, the length of the window along the direction connecting the source and drain electrodes is 0.5 μm, and the length along the direction perpendicular to the connecting direction of the source and drain electrodes is The length is 20 μm. The first dielectric layer is an in-situ grown Si ₃ N ₄ layer with a thickness of about 10 nm, and the second dielectric layer is hfO ₂ with a thickness of 100 nm. Both source and drain electrodes are formed by Ti/Al/Ni/Au (20/120/50/200nm) through metal deposition and high temperature thermal annealing. The distance between the source and drain electrodes was 2.5 μm. The length of the edge of the second dielectric layer toward the center of the channel beyond the source and drain electrodes is 0.5 μm. The gate electrode uses Ni/Au (50/150nm).

The descriptions of the above embodiments are only used to help understand the method and core idea of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the utility model, some improvements and modifications can also be made to the utility model, and these improvements and modifications also fall into the protection of the claims of the utility model. within range. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined in this application may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to these embodiments shown in this application, but will conform to the broadest scope consistent with the principles and novel features disclosed in this application.

Claims (9)

1. a novel normally-off III-V HFET, it is characterised in that include substrate material layer, the first semiconductor layer, the second semiconductor layer, medium template layer, drain electrode, source electrode, first medium layer, second dielectric layer and gate electrode, wherein,

Described substrate material layer is formed described second semiconductor layer, described second semiconductor layer constructs drain electrode and source electrode；

Described first semiconductor layer includes body and n the bossing formed along this this bulk-growth, and n is more than or equal to 1；

Described second semiconductor layer and the first semiconductor layer body are combined together to form hetero-junctions raceway groove, and these hetero-junctions raceway groove two ends connect described drain electrode and source electrode respectively；The thickness of described first semiconductor layer body is not more than the critical thickness forming two-dimensional electron gas 2DEG on hetero-junctions raceway groove, makes two-dimensional electron gas 2DEG natural in described hetero-junctions raceway groove depleted；

Described medium template layer is arranged on described first semiconductor layer body and forms n window at equal intervals, and described first semiconductor layer body forms described n bossing along described n window growth；Described bossing makes described first semiconductor layer beyond critical thickness thus form two-dimensional electron gas 2DEG in the view field of described bossing, forms n equally spaced two-dimensional electron gas 2DEG region on described hetero-junctions raceway groove；

Described first semiconductor layer surface is additionally provided with first medium layer, described first medium layer is provided with described gate electrode, described gate electrode covers two edges extensions of whole channel length and described gate electrode and exceedes described drain electrode and the source electrode edge near raceway groove side respectively, is provided with described second dielectric layer between described gate electrode and described drain electrode, source electrode.

Novel normally-off III-V HFET the most according to claim 1, it is characterised in that described bossing is continuous distribution or is divided into m part along its direction of growth, m is more than or equal to 1.

Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterised in that described second dielectric layer is only located at described gate electrode and described drain electrode and the marginal portion of the crossover of source electrode.

Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterized in that, being additionally provided with to improve the interposed layer of the mobility of the two-dimensional electron gas of heterojunction boundary between described first semiconductor layer and the second semiconductor layer, described interposed layer is AlN layer.

Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterised in that described first semiconductor layer is AlGaN layer；Described second semiconductor layer is GaN layer.

Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterised in that described first semiconductor layer is AlN layer, described second semiconductor layer is GaN layer.

Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterised in that the Si of growth in situ when described first medium layer is growth heterogeneous structure material₃N₄, its thickness is 5～25nm.

Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterised in that described medium template layer is SiO₂Layer.

Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterised in that described second dielectric layer is SiO₂Layer.