CN205844515U - Ultra wide-band linear frequency modulated signals based on PLL produces circuit and radio communication device - Google Patents

Abstract

The utility model discloses a PLL-based ultra-wideband linear frequency modulation signal generation circuit and a wireless communication device. The ultra-wideband linear frequency modulation signal generation circuit includes a phase-locked loop chip, and the phase-locked loop chip is connected with the output end of a temperature-compensated crystal oscillator. The crystal oscillator is used to provide a jittering fixed reference clock for the phase-locked loop chip; the output end of the phase-locked loop chip is connected to the input end of the loop filter, and the output end of the loop filter is connected to the input end of the voltage-controlled oscillator; The output terminal of the voltage-controlled oscillator is connected with the power distribution circuit; the power distribution circuit outputs two power division signals, one is connected with the amplifier circuit, and the other is fed back to the RF signal input terminal of the phase-locked loop chip; the output terminal of the amplifier circuit is connected with the The input end of the pass filter is connected, and the output end of the band pass filter outputs a chirp signal. The utility model effectively reduces the complexity and cost of the system under the condition of ensuring the linearity and performance of the linear frequency modulation signal.

Description

PLL-based ultra-wideband chirp signal generation circuit and wireless communication device

technical field

The utility model belongs to the field of radar broadband frequency sources, in particular to a PLL-based ultra-wideband linear frequency modulation signal generating circuit and a wireless communication device.

Background technique

The ultra-wideband through-wall radar uses the ultra-wideband signal generated by the transmitter to obtain a very high one-bit distance resolution. After the receiver demodulates the echo reflected by the target behind the wall, the signal processing part uses related processing algorithms to Target detection, localization and even imaging.

At present, the system adopted by wall-penetrating radar includes linear frequency modulation (LFM) signal, impulse pulse (Impulse) signal, step frequency (SF) signal and so on. UWB chirp signal has large instantaneous bandwidth, high range resolution and high moving target detection characteristics, so it is a signal form widely used in pulse compression radar, synthetic aperture radar and other systems.

The most direct method of generating linear frequency modulation signal is DDS, which has the characteristics of high linearity, but the working frequency band is low, and generally rarely exceeds GHz. The voltage-controlled oscillator VCO can generate sweeping frequency signals with a wide range, but the linearity of the generated chirp signal is limited by the low linearity of the VCO itself, which requires a complex nonlinear calibration system. At present, the advantages and disadvantages of DDS and VCO can be well combined through the phase-locked loop. The output signal not only ensures the high linearity of DDS, but also realizes the wide-range frequency sweep of VCO. However, the circuit structure is complex and the spurious suppression is poor.

Utility model content

In order to solve the shortcomings of the prior art, the utility model provides a PLL-based ultra-wideband chirp signal generating circuit and a wireless communication device. The utility model can directly output high linearity and low spurious linear frequency modulation signals through the control of the phase-locked loop circuit without using the DDS, thereby effectively reducing the complexity and cost of system design.

In order to achieve the above object, the utility model adopts the following technical solutions:

A PLL-based ultra-wideband chirp signal generation circuit, including a phase-locked loop chip, the phase-locked loop chip is connected to the output of a temperature-compensated crystal oscillator, and the temperature-compensated crystal oscillator is used to provide a jitter fixed reference for the phase-locked loop chip clock;

The output end of the phase-locked loop chip is connected to the input end of the loop filter, and the output end of the loop filter is connected to the input end of the voltage-controlled oscillator; the output end of the voltage-controlled oscillator is connected to the power distribution The circuit is connected; the power distribution circuit outputs two power division signals, one of which is connected with the amplifying circuit, and the other is fed back to the radio frequency signal input terminal of the phase-locked loop chip;

The output end of the amplifying circuit is connected with the input end of the band-pass filter, and the output end of the band-pass filter outputs a chirp signal.

The loop filter adopts an active proportional integral filter, which is used to improve the anti-interference performance of the whole circuit.

The bandpass filter is an S-band bandpass filter. A band-pass filter is added to filter out high-frequency harmonics, and the out-of-band harmonic suppression of the output signal of the ultra-wideband voltage-controlled oscillator is completed.

The amplifying circuit includes an amplifying chip, the output end of the amplifying chip is connected to the power supply through an inductance element, and the connection point between the inductance element and the power supply is also connected to three capacitors connected in parallel.

A wireless communication device includes the PLL-based ultra-wideband chirp signal generating circuit.

The beneficial effects of the utility model are:

The utility model can directly output high linearity and low stray chirp signals through phase-locked loop circuit control voltage-controlled oscillator without using DDS, effectively reducing system design complexity and cost. Under the condition of ensuring the linearity and performance of the chirp signal, the complexity and cost of the system are effectively reduced.

Description of drawings

Fig. 1 is the ultra-wideband chirp signal generation circuit diagram based on PLL of the utility model;

Fig. 2 is the circuit diagram that phase-locked loop chip of the present utility model is connected with temperature-compensated crystal oscillator;

Fig. 3 is the loop filter circuit diagram of the utility model;

Fig. 4 is the voltage controlled oscillator circuit diagram of the present utility model;

Fig. 5 is a combined circuit diagram of the power distribution circuit, the low-noise amplifier circuit and the band-pass filter of the present invention.

detailed description

The preferred embodiments of the utility model will be described in detail below in conjunction with the accompanying drawings, so that the advantages and characteristics of the utility model can be more easily understood by those skilled in the art, so that the protection scope of the utility model can be defined more clearly .

Fig. 1 is the UWB chirp signal generation circuit diagram based on PLL of the present utility model, as shown in the figure, the UWB chirp signal generation circuit based on PLL includes a phase-locked loop chip, and the phase-locked loop chip and temperature-compensated crystal oscillator The output terminals are connected, and the temperature-compensated crystal oscillator is used to provide a jittering fixed reference clock for the phase-locked loop chip;

The output end of the phase-locked loop chip is connected to the input end of the loop filter, and the output end of the loop filter is connected to the input end of the voltage-controlled oscillator; the output end of the voltage-controlled oscillator is connected to the power distribution The circuit is connected; the power distribution circuit outputs two power division signals, one of which is connected with the amplifying circuit, and the other is fed back to the radio frequency signal input terminal of the phase-locked loop chip;

The output end of the amplifying circuit is connected with the input end of the band-pass filter, and the output end of the band-pass filter outputs a chirp signal.

In this embodiment, as shown in Figure 2, the phase-locked loop chip uses HMC703LP4E.

As shown in Figure 3, the loop filter uses an active proportional integral filter, which is realized by OP184ES.

As shown in Fig. 4, the voltage-controlled oscillator is realized by V600ME14-LF voltage-controlled oscillator of Z-Communications Company.

As shown in Figure 5, the band-pass filter is an S-band band-pass filter, which is realized by LFCN-3800.

The amplifying circuit includes an amplifying chip, the output terminal of the amplifying chip is connected to the power supply through an inductance element, and the connection point between the inductance element and the power supply is also connected to three capacitors connected in parallel. Wherein, the amplifying chip adopts a low-noise amplifying chip. The low noise amplifier chip in this embodiment adopts ADL5601.

The PLL-based ultra-wideband linear frequency modulation signal generation circuit of the present utility model is divided into three parts:

(1) Frequency sweep signal source part: This part uses the HMC703 phase-locked loop chip with frequency sweep function, external V600ME14 voltage-controlled oscillator and loop filter to form a phase-locked loop circuit. 2-4GHz linear frequency sweep can be realized by configuring HMC703 registers. HMC703LP4E controls the built-in current-type charge pump to output ladder-shaped modulation current according to the RF reference signal input by the feedback loop and the external reference crystal oscillator. After filtering by the active loop filter, it becomes the modulation voltage to control the ultra-wideband voltage-controlled oscillation. The device performs the output of the frequency sweep signal. All the control signals of the phase-locked loop circuit are generated by the digital control board, and the resistor network is used to complete the power distribution. Through the preliminary simulation design verification of the loop filter parameters, the output signal has the best phase noise performance, as shown in Figure 2-Figure 4.

(2) Power distribution part: Since the introduction of radio frequency devices will bring insertion loss, the low-noise amplifier ADL5601 is used here to amplify the signal power to meet the transmission power requirements of the transmitter, as shown in Figure 5.

(3) Filtering channel selection part: the voltage-controlled oscillator output signal frequency is 2-4GHz, and harmonics will be generated in the range of 4-8GHz. As shown in Figure 5, by adding a band-pass filter to filter out high-frequency harmonics, the out-of-band harmonic suppression of the output signal of the ultra-wideband voltage-controlled oscillator is completed.

The phase-locked loop chip, loop filter, band-pass filter, voltage-controlled oscillator and low-noise amplifier chip of the utility model can also be realized by using other types of chips.

The utility model also provides a wireless communication device, including the PLL-based ultra-wideband linear frequency modulation signal generating circuit.

The utility model can directly output high linearity and low stray chirp signals through phase-locked loop circuit control voltage-controlled oscillator without using DDS, effectively reducing system design complexity and cost. Under the condition of ensuring the linearity and performance of the chirp signal, the complexity and cost of the system are effectively reduced.

Although the specific implementation of the utility model has been described above in conjunction with the accompanying drawings, it does not limit the protection scope of the utility model. Those skilled in the art should understand that on the basis of the technical solution of the utility model, those skilled in the art do not need to Various modifications or deformations that can be made with creative efforts are still within the protection scope of the present utility model.

Claims (5)

1. A PLL-based UWB chirp generating circuit, characterized in that, comprises a phase-locked loop chip, and the phase-locked loop chip is connected to the output end of the temperature-compensated crystal oscillator, and the temperature-compensated crystal oscillator is used for phase-locked The ring chip provides a jitter fixed reference clock; The output end of the phase-locked loop chip is connected to the input end of the loop filter, and the output end of the loop filter is connected to the input end of the voltage-controlled oscillator; the output end of the voltage-controlled oscillator is connected to the power distribution The circuit is connected; the power distribution circuit outputs two power division signals, one of which is connected with the amplifying circuit, and the other is fed back to the radio frequency signal input terminal of the phase-locked loop chip; The output end of the amplifying circuit is connected with the input end of the band-pass filter, and the output end of the band-pass filter outputs a chirp signal. 2. The ultra-wideband chirp signal generation circuit based on PLL as claimed in claim 1, wherein the loop filter adopts an active proportional integral filter. 3. The ultra wideband chirp signal generation circuit based on PLL as claimed in claim 1, characterized in that, the band-pass filter is an S-band band-pass filter. 4. the ultra-wideband chirp signal generation circuit based on PLL as claimed in claim 1, is characterized in that, described amplifying circuit comprises amplifying chip, and the output end of described amplifying chip is connected with power supply by an inductive element, inductive element and The junction of the power supply is also connected to three capacitors connected in parallel. 5. A wireless communication device, characterized in that it comprises the PLL-based ultra-wideband chirp signal generation circuit according to any one of claims 1-4.