CN205828393U - A kind of high density gated diode for electrostatic discharge (ESD) protection - Google Patents
A kind of high density gated diode for electrostatic discharge (ESD) protection Download PDFInfo
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- CN205828393U CN205828393U CN201620749938.8U CN201620749938U CN205828393U CN 205828393 U CN205828393 U CN 205828393U CN 201620749938 U CN201620749938 U CN 201620749938U CN 205828393 U CN205828393 U CN 205828393U
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- 239000002184 metal Substances 0.000 claims abstract description 46
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims abstract description 34
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 239000013078 crystal Substances 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 239000011159 matrix material Substances 0.000 abstract description 8
- 238000009826 distribution Methods 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 5
- 230000002028 premature Effects 0.000 abstract description 3
- 230000003068 static effect Effects 0.000 description 8
- 238000013461 design Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000005457 optimization Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
This utility model provides a kind of high density gated diode for electrostatic discharge (ESD) protection, at least includes: N well region, p+ district, n+ district and polysilicon gate；Described p+ district and n+ district are formed in described N well region, and described p+ district and n+ district are spaced formation array structure；Described polysilicon gate is formed at the N well region surface between described p+ district and n+ district.Described gated diode also includes the first metal layer and the second metal level, is electrically connected with described p+ district and described n+ district respectively；Described the first metal layer and the second metal level form metal layout routing network symmetrically.Diode of the present utility model can be respectively formed effective ESD electric current release channel in its surrounding, and the arrangement mode of p+/n+ can improve the effective girth in unit are.It addition, utilize metal line network symmetrically, each unit in matrix can be made to have uniform Electric Field Distribution, thus realize uniformly releasing of ESD electric current, prevent hot-spot from causing device premature failure.
Description
Technical field
This utility model relates to semiconductor device, particularly relates to a kind of highly dense for electrostatic discharge (ESD) protection
Degree gated diode.
Background technology
In integrated circuit (Integrated Circuits), static discharge (ESD, Electrostatic
Discharge) reliability effect of chip be can not be ignored, along with nanotechnology is commonly used, external environment condition, human body, machinery,
The static discharges such as radiation field are more significantly to IC destructive influences, and ESD is prevented in manufacture process by industry in the design of IC
Protect and done substantial amounts of research and practice.
Excellent ESD device needs relatively low cut-in voltage and the speed of response faster.Owing to diode (Diode) is held concurrently
Standby above-mentioned superperformance, is commonly used in ESD protection, and especially in 28nm processing procedure, diode passes the imperial examinations at the provincial level foot gently in ESD design
Weight.Diode is a two ends passive device, and its two ends are respectively positive pole and negative pole, and circuit symbol is as it is shown in figure 1, operation principle is
ESD electric current flows to negative pole from positive pole, thus realizes releasing of ESD electric current.
Traditional STI diode as a example by P+/NW diode, its structure as shown in Figures 2 and 3, profile such as Fig. 4 institute
Showing, there is polysilicon gate density (poly density) wretched insufficiency in this traditional shallow trench isolation (STI) diode.And show
It is not enough that some gated diodes (gate diode) can be effectively improved poly density, and its lower conducting resistance becomes
The prioritizing selection of high speed ESD device, is illustrated in figure 5 the gated diode (as a example by P+/NW diode) of finger-like (finger),
Fig. 6 is the profile of Fig. 5.This diode possesses the conducting resistance (unit perimeter) lower than STI diode, in CMOS technology
In have a strongest compatibility, design is convenient.But, in 28nm processing procedure, poly density must is fulfilled for the requirement ability of DFM
Ensureing the stability that device manufactures, the gated diode of finger-like (finger) often occurs finger two ends electricity under ESD electric field
Field distribution is uneven, and causes the uneven phenomenon of CURRENT DISTRIBUTION, easily occurs that device hot-spot causes component failure.
Therefore, along with reducing of chip area, in effective area, how to realize gated diode ESD current drain ability
Maximization become important problem.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is that providing a kind of protects for static discharge
The high density gated diode protected, is used for solving the problems such as CURRENT DISTRIBUTION in prior art is uneven, electrostatic protection ability is low.
For achieving the above object and other relevant purposes, this utility model provides a kind of highly dense for electrostatic discharge (ESD) protection
Degree gated diode, described gated diode at least includes: N well region, p+ district, n+ district and polysilicon gate；
Described p+ district and n+ district are formed in described N well region, and described p+ district and n+ district are spaced formation array junctions
Structure；
Described polysilicon gate is formed at the N well region surface between described p+ district and n+ district.
The structure of a kind of optimization of the high density gated diode of electrostatic discharge (ESD) protection it is used for as this utility model, described
Polysilicon gate includes some the first polysilicon gates in X direction and some the second polysilicon gates along Y-direction, described first
Polysilicon gate and the second polysilicon gate are orthogonal.
The structure of a kind of optimization of the high density gated diode of electrostatic discharge (ESD) protection it is used for as this utility model, described
Gated diode also includes that the first metal layer and the second metal level, described p+ district are electrically connected with the first metal layer by connecting hole, institute
State n+ district to be electrically connected by connecting hole and the second metal level.
The structure of a kind of optimization of the high density gated diode of electrostatic discharge (ESD) protection it is used for as this utility model, described
The first metal layer and the second metal level form uniform metal layout routing network.
The structure of a kind of optimization of the high density gated diode of electrostatic discharge (ESD) protection it is used for as this utility model, described
N well region is formed in P type substrate.
The structure of a kind of optimization of the high density gated diode of electrostatic discharge (ESD) protection it is used for as this utility model, described
P+ district and n+ district are all square structure.
As it has been described above, the high density gated diode for electrostatic discharge (ESD) protection of the present utility model, at least include: N trap
District, p+ district, n+ district and polysilicon gate；Described p+ district and n+ district are formed in described N well region, and described p+ district and n+ are interval
Array structure is formed every arrangement；Described polysilicon gate is formed at the N well region surface between described p+ district and n+ district.Described grid two
Pole pipe also includes that the first metal layer and the second metal level, described p+ district are electrically connected with the first metal layer by connecting hole, described n+ district
It is electrically connected by connecting hole and the second metal level；Described the first metal layer and the second metal level form uniform metal placement-and-routing net
Network.Diode of the present utility model can be respectively formed effective ESD electric current release channel, and the arrangement side of p+/n+ in its surrounding
Formula can improve the effective girth in unit are.It addition, utilize metal line network symmetrically, can make in matrix every
Individual unit has uniform Electric Field Distribution, thus realizes uniformly releasing of ESD electric current, prevents hot-spot from causing device too early
Lost efficacy.
Accompanying drawing explanation
Fig. 1 is shown as the electrode schematic symbol diagram of diode.
Fig. 2 is shown as the one of which structure top view of STI diode in prior art.
Fig. 3 is shown as the another kind of structure top view of STI diode in prior art.
Fig. 4 is shown as the generalized section of STI diode in prior art.
Fig. 5 is shown as the structure top view of gated diode in prior art.
Fig. 6 is shown as the generalized section of gated diode in prior art.
Fig. 7 is shown as the structure top view of the gated diode of the present invention.
Fig. 8 is shown as the structure top view arranged after metal line of the gated diode of the present invention.
Element numbers explanation
1,1A N well region
2,2A p+ district
3,3A n+ district
4,4A polysilicon gate
41 first polysilicon gates
42 second polysilicon gates
5 the first metal layers
6 second metal levels
7A P type substrate
8A STI
9 connecting holes
Detailed description of the invention
By particular specific embodiment, embodiment of the present utility model being described below, those skilled in the art can be by this
Content disclosed by description understands other advantages of the present utility model and effect easily.
Refer to accompanying drawing.It should be clear that structure depicted in this specification institute accompanying drawings, ratio, size etc., the most only in order to coordinate
Content disclosed in description, understands for those skilled in the art and reads, and being not limited to this utility model can be real
The qualifications executed, therefore do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the tune of size
Whole, under not affecting effect that this utility model can be generated by and the purpose that can reach, all should still fall in this utility model institute
In the range of the technology contents disclosed obtains and can contain.Meanwhile, in this specification cited as " on ", D score, "left", "right",
The term of " middle " and " one " etc., is merely convenient to understanding of narration, and is not used to limit the enforceable scope of this utility model,
Being altered or modified of its relativeness, is changing under technology contents without essence, when being also considered as the enforceable category of this utility model.
As it is shown in fig. 7, this utility model provides a kind of high density gated diode for electrostatic discharge (ESD) protection, described grid
Pole diode at least includes N well region 1, p+ district 2, n+ district 3 and polysilicon gate 4.
Wherein, district 3 of described p+ district 2 and n+ is formed in described N well region 1, and district 3 of described p+ district 2 and n+ is spaced
Form array structure；Described polysilicon gate 4 is formed at N well region 1 surface between district 3 of described p+ district 2 and n+.
Described N well region 1 is then formed in a P type substrate (diagram).Doping process is passed through in described P type substrate
Described N well region 1 can be formed.
In order to preferably describe the structure of polysilicon gate 4, it is divided into the first polysilicon gate 41 and the second polysilicon by described
Grid 42.Specifically, described polysilicon gate 4 includes that some articles of the first polysilicon gates 41 in X direction and some articles are along the of Y-direction
Two polysilicon gates 42, described first polysilicon gate 41 and the second polysilicon gate 42 are orthogonal.
It should be noted that accompanying drawing 7 show only the battle array that district 3 of described p+ district 2 and n+ is spaced the five elements five row of formation
Array structure, however, it should know, array structure is not limited to the five elements five row, and according to design needs, other line numbers and columns also exist
In protection domain of the present utility model.Preferably, district 3 of described p+ district 2 and n+ is all square structure.
Gated diode of the present utility model uses for the CMOS process design of 28nm, grid length (gate length)
1.8V device minimum feature, by p+/n+ Heterogeneous Permutation, makes the surrounding of gated diode can be formed with the static discharge of effect
Electric current release channel.It addition, the area of p+/n+ has accomplished the size optimized, improve the effective girth in unit are.With
Time, the density (Poly density) of polysilicon gate can also meet DFM requirement, it is not necessary to adds unnecessary virtual polysilicon gate again
(poly dummy)。
Further, as described in Figure 8, described gated diode also includes the first metal layer 5 and the second metal level 6, described p
+ district 2 is electrically connected with the first metal layer 5 by connecting hole 9, and described n+ district 3 is electrically connected by connecting hole and the second metal level 6.Described
Insulant (diagram) isolation can be passed through between one metal level 5 and the second metal level 6.Described connecting hole is filled with
The connecting hole of conductive material, is produced in insulant.
Further, as shown in Figure 8, described the first metal layer 5 and the second metal level 6 form hardware cloth symmetrically
Office's routing network.This utility model utilizes routing network symmetrically and the metal layout method of symmetry so that in matrix
Each gated diode unit can obtain uniform Electric Field Distribution, it is achieved uniformly releasing of static discharge current, prevents local
Overheated and cause device premature failure, improve the usefulness of electrostatic discharge (ESD) protection.
Table 1 compared for gated diode (Fig. 5) and this utility model matrix type grid of finger-like in prior art (finger)
Effective girth of gated diode in pole diode (Fig. 7).
Table 1
Such as table 1 it can be seen that verified by 28nm domain (layout), at the active area (Active of unit are
Area, AA) in, the girth of matrix type gated diode is than effective Zhou Chang great 16% of fingered gate diode.Therefore, matrix
The static discharge current relieving capacity of type gated diode is remarkably reinforced, and by the optimization of layout design, static discharge electricity
Stream uniformity is improved.
Therefore, matrix type gated diode of the present utility model more can utilize effective area, obtains maximizing perimeter value,
Releasing of static discharge current can be preferably realized in ESD protects.
In sum, the high density gated diode for electrostatic discharge (ESD) protection of the present utility model, at least include: N trap
District, p+ district, n+ district and polysilicon gate；Described p+ district and n+ district are formed in described N well region, and described p+ district and n+ are interval
Array structure is formed every arrangement；Described polysilicon gate is formed at the N well region surface between described p+ district and n+ district.Described grid two
Pole pipe also includes the first metal layer and the second metal level, is electrically connected with described p+ district and described n+ district respectively；Described the first metal layer
Metal layout routing network symmetrically is formed with the second metal level.Diode of the present utility model can be respectively formed in its surrounding
Effectively ESD electric current release channel, and the arrangement mode of p+/n+ can improve the effective girth in unit are.It addition, it is sharp
With metal line network symmetrically, each unit in matrix can be made to have uniform Electric Field Distribution, thus realize ESD electricity
Uniformly releasing of stream, prevents hot-spot from causing device premature failure.
So, this utility model effectively overcomes various shortcoming of the prior art and has high industrial utilization.
Above-described embodiment only illustrative principle of the present utility model and effect thereof are new not for limiting this practicality
Type.Above-described embodiment all can be carried out by any person skilled in the art under spirit and the scope of the present utility model
Modify or change.Therefore, art has usually intellectual such as without departing from the essence disclosed in this utility model
All equivalences completed under god and technological thought are modified or change, and must be contained by claim of the present utility model.
Claims (6)
1. the high density gated diode for electrostatic discharge (ESD) protection, it is characterised in that described gated diode at least wraps
Include: N well region, p+ district, n+ district and polysilicon gate；
Described p+ district and n+ district are formed in described N well region, and described p+ district and n+ district are spaced formation array structure；
Described polysilicon gate is formed at the N well region surface between described p+ district and n+ district.
High density gated diode for electrostatic discharge (ESD) protection the most according to claim 1, it is characterised in that: described many
Crystal silicon grid include some the first polysilicon gates in X direction and some the second polysilicon gates along Y-direction, described more than first
Crystal silicon grid and the second polysilicon gate are orthogonal.
High density gated diode for electrostatic discharge (ESD) protection the most according to claim 1, it is characterised in that: described grid
Pole diode also includes that the first metal layer and the second metal level, described p+ district are electrically connected with the first metal layer by connecting hole, described n
+ district is electrically connected by connecting hole and the second metal level.
High density gated diode for electrostatic discharge (ESD) protection the most according to claim 3, it is characterised in that: described
One metal level and the second metal level form metal layout routing network symmetrically.
High density gated diode for electrostatic discharge (ESD) protection the most according to claim 1, it is characterised in that: described N
Well region is formed in P type substrate.
High density gated diode for electrostatic discharge (ESD) protection the most according to claim 1, it is characterised in that: described p+
District and n+ district are all square structure.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620749938.8U CN205828393U (en) | 2016-07-15 | 2016-07-15 | A kind of high density gated diode for electrostatic discharge (ESD) protection |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620749938.8U CN205828393U (en) | 2016-07-15 | 2016-07-15 | A kind of high density gated diode for electrostatic discharge (ESD) protection |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110518008A (en) * | 2018-05-22 | 2019-11-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of ESD protective device and preparation method thereof, electronic device |
| CN110867482A (en) * | 2018-08-28 | 2020-03-06 | 中芯国际集成电路制造(上海)有限公司 | An ESD protection device and electronic device for IC chips |
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| US11789006B2 (en) | 2019-03-12 | 2023-10-17 | Oxford Nanopore Technologies Plc | Nanopore sensing device, components and method of operation |
| US12121894B2 (en) | 2017-11-29 | 2024-10-22 | Oxford Nanopore Technologies Plc | Microfluidic device |
| US12140563B2 (en) | 2007-12-19 | 2024-11-12 | Oxford Nanopore Technologies Plc | Formation of layers of amphiphilic molecules |
| US12350637B2 (en) | 2012-10-26 | 2025-07-08 | Oxford Nanopore Technologies Plc | Formation of array of membranes and apparatus therefor |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12140563B2 (en) | 2007-12-19 | 2024-11-12 | Oxford Nanopore Technologies Plc | Formation of layers of amphiphilic molecules |
| US11561216B2 (en) | 2012-02-13 | 2023-01-24 | Oxford Nanopore Technologies Plc | Apparatus for supporting an array of layers of amphiphilic molecules and method of forming an array of layers of amphiphilic molecules |
| US11913936B2 (en) | 2012-02-13 | 2024-02-27 | Oxford Nanopore Technologies Plc | Apparatus for supporting an array of layers of amphiphilic molecules and method of forming an array of layers of amphiphilic molecules |
| US12350637B2 (en) | 2012-10-26 | 2025-07-08 | Oxford Nanopore Technologies Plc | Formation of array of membranes and apparatus therefor |
| US11596940B2 (en) | 2016-07-06 | 2023-03-07 | Oxford Nanopore Technologies Plc | Microfluidic device |
| US12121894B2 (en) | 2017-11-29 | 2024-10-22 | Oxford Nanopore Technologies Plc | Microfluidic device |
| CN110518008A (en) * | 2018-05-22 | 2019-11-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of ESD protective device and preparation method thereof, electronic device |
| CN110867482A (en) * | 2018-08-28 | 2020-03-06 | 中芯国际集成电路制造(上海)有限公司 | An ESD protection device and electronic device for IC chips |
| CN110867482B (en) * | 2018-08-28 | 2023-09-26 | 中芯国际集成电路制造(上海)有限公司 | An ESD protection device and electronic device for IC chips |
| US11789006B2 (en) | 2019-03-12 | 2023-10-17 | Oxford Nanopore Technologies Plc | Nanopore sensing device, components and method of operation |
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