CN205563133U - Digital PLL phase -locked loop simulation system of high Q value that rebounds - Google Patents

Abstract

The utility model relates to a rebound high-Q value digital PLL phase-locked loop simulation system, which is characterized in that it includes a central processing unit, a time constant generator, a frequency divider, a detection amplifier, an integrator, a simulation excitation source generator, and a frequency stability test instrument and frequency multiplier; compared with the existing technology, the beneficial effects of the utility model are: the utility model is simple in structure, reasonable in design, can effectively improve the accuracy of simulation calculation, and adopts program control at the same time, with a high degree of automation and relatively easy to use Convenience, improve the simulation performance of the simulation system.

Description

Bounce high Q value digital PLL phase-locked loop simulation system

technical field

The utility model relates to the field of simulation systems, in particular to a rebound high-Q value digital PLL phase-locked loop simulation system.

Background technique

The so-called system simulation is to establish a simulation model that can describe the system structure or behavior process and has a certain logical or quantitative relationship based on the purpose of system analysis and on the basis of analyzing the nature and relationship of each element of the system. , based on which experiments or quantitative analysis are carried out to obtain various information required for correct decision-making. A phase-locked loop is a feedback control circuit, referred to as a phase-locked loop (PLL, Phase-Locked Loop). The characteristic of the phase-locked loop is: the frequency and phase of the internal oscillation signal of the loop are controlled by an externally input reference signal. Because the phase-locked loop can automatically track the frequency of the output signal to the frequency of the input signal, the phase-locked loop is usually used in a closed-loop tracking circuit. During the working process of the phase-locked loop, when the frequency of the output signal is equal to the frequency of the input signal, the output voltage and the input voltage maintain a fixed phase difference, that is, the phase of the output voltage and the input voltage is locked, which is phase-locked The origin of the name of the ring. A phase-locked loop is usually composed of three parts: a phase detector (PD, Phase Detector), a loop filter (LF, Loop Filter) and a voltage-controlled oscillator (VCO, Voltage Controlled Oscillator); the phase detector in the phase-locked loop is also called It is a phase comparator, its function is to detect the phase difference between the input signal and the output signal, and convert the detected phase difference signal into a uD(t) voltage signal output, which is filtered by a low-pass filter to form a voltage-controlled oscillation The control voltage uC(t) of the oscillator controls the frequency of the oscillator output signal.

The calculation accuracy of the existing simulation system is low. When simulating a complex system, it is difficult to realize it on the circuit, and the accuracy is not easy to guarantee. When there are many logical judgment links in the system, the simulation is more difficult and the penetration rate is low.

Utility model content

The purpose of the utility model is to provide a bounce-back high-Q digital PLL phase-locked loop simulation system in order to overcome the deficiencies of the prior art.

The utility model is realized through the following technical solutions:

A rebound high-Q digital PLL phase-locked loop simulation system includes a central processing unit, a time constant generator, a frequency divider, a detection amplifier, an integrator, a simulation excitation source generator, a frequency stability tester and a frequency multiplier; The frequency divider is connected with a detection amplifier, and the detection amplifier is connected with an integrator, and the integrator is connected with a central controller; the central controller is connected with a simulation excitation source generator, a frequency multiplier, a frequency stability tester and a time A constant generator; the simulation excitation source generator is connected with a frequency stability tester, and the frequency multiplier is connected with a simulation excitation source generator and a frequency divider; the time constant generator is connected with a detection amplifier and an integrator respectively.

Furthermore, F0 in the simulation system signal transfer diagram is the original frequency of the high stability reference source, , Respectively, the frequency division frequency of the high stability reference source and the output frequency of the simulation excitation generator. , , , , are the errors of the high-stable reference source, the detection amplifier, the integrator, the simulated excitation generator and the output of the frequency multiplier, respectively. M is the multiplication factor, is the frequency discrimination slope of the detector amplifier, is the voltage-controlled slope of the simulated excitation generator. 1/(1+STh) is the loop transfer function of the equivalent RC filter, where S is the complex Fourier frequency , Th is the RC time constant. A and Ti are the magnification factor and time constant of the integrator respectively. Here, in order to realize the simulation in Figure 1, we added a time constant generator module, which is composed of resistance and capacitance multi-stage series-parallel circuits to generate different The RC time constant of , and applied to Th of the detection amplifier and Ti of the integrator in Figure 1.

In the integrator in Figure 1, in order to simplify the simulation situation, we intentionally set the magnification factor A of the integrator to infinity, and when A is very large, we can approximately know that the transfer function of the integrator is 1/STi. definition:

(1)

Then the open-loop gain of the simulation system in Figure 1 is:

(2)

The steady-state output frequency of the simulated excitation source generator can be expressed as:

(3)

After the system reaches a steady state in the loop, it usually has G(s)>1, so formula (3) can be written as:

(4)

It can be seen from formula (4) that in an ideal state, the steady-state output frequency of the simulation excitation source generator should be equal to the high-stable reference source after frequency division

Rate values have a doubling relationship:

(5)

Concrete parameter among the utility model is:

1. Multiple relationship

In order to realize the multiple relationship between the steady-state output frequency of the simulated excitation source generator and the high-stable reference source frequency value theoretically expressed in Figure 1 and formula (5), and the above relationship is a dynamic balance, we need to pass Figure 1 The central processing unit in the system is used to coordinate the work of the whole system. Here, the parameter of this task is temporarily defined as X, which will be elaborated later.

2. Time constant

Formula (5) and the setting of the above X parameters are theoretical, because in the actual PLL phase-locked loop formed in Figure 1, due to the frequency difference of the high-stable reference source itself and the errors of each part of the PLL loop, There is always a certain deviation between the output frequency of Figure 1 and its nominal value. This deviation may be caused by the deviation and aging of the simulation excitation generator end, the zero point drift of the integrator, and the phase change of the frequency multiplier. all The long-term drift of the item may cause the aging phenomenon of the output frequency and become additional noise.

In order to reduce the error of the above-mentioned electronic circuit part, the open-loop gain G(s) should be increased as much as possible. For the convenience of simulation, we unified the , , , , Each error is set to a fixed value. In order to improve the performance of the simulation system in Figure 1, theoretically speaking, the open-loop gain G(s) should be made as large as possible, so that the numerator in formula (2) becomes larger, but in fact G0 should have a limit. It is generally believed that the damping coefficient of the system should not be less than 0.5, then

(6)

So for the sake of convenience, we set G0=1 and make Th=Ti at the same time. The way to do it is:

(1) Set the detection amplifier, simulation excitation generator and frequency multiplier separately through the central controller in Figure 1 , , M, make equal to 1;

(2) Set the time constant Th=Ti corresponding to the detection amplifier and the integrator respectively through the central controller in Fig. 1 .

After the above settings, the open-loop gain of the simulation system in Figure 1 expressed by formula (2) is:

(7)

3. Q value of simulation system

Decreasing the time constant Th, according to formula (7) does increase the open-loop gain of the simulation system, which is beneficial to the system performance, which also increases the loop filter bandwidth fh at the same time. Figure 1. The high-stable reference source is equivalent to a frequency discriminator. When its long-term drift can be ignored, we assume that its power-law spectral noise formula is:

(8)

In theory, the loop in Figure 1 works in a linear state. If it can be considered that the simulated excitation generator is completely uncorrelated with the power spectral density of the high-stable reference source (Sy(f)OSC and Sy(f)REF), the system output in Figure 1 The power spectral density can be expressed as:

(9)

By definition, we have , therefore, substituting (8) into (9), we can see , when the averaging period of the simulation is very short, ,Have

(10)

When the averaging period of the simulation is extremely long ,Have

(11)

Obviously, the entire loop is a high-pass filter for the simulation excitation generator; it is a low-pass filter for the high-stable reference source; its filtering characteristics are determined by the high-end cut-off frequency fh of the loop filter. The extreme case of (10) is , the extreme case of (11) is . It can be seen that if fh is too large, the short-term stability of the output signal of the simulation system in Figure 1 will deteriorate; if fh is too small, the long-term stability of the output signal of the simulation system in Figure 1 will deteriorate. After the system in Figure 1 is closed-loop, we cannot know the loop bandwidth of the system, that is, the high-end cutoff frequency fh. We use the Q value to characterize the stable signal of the output signal of the simulation system in Figure 1, and pass the frequency stability test in Figure 1 The simulation test results that characterize the Q value of the system can be obtained by measuring with an instrument, so as to indirectly reflect the selection of the loop bandwidth, that is, the value of the high-end cut-off frequency fh.

Compared with the existing technology, the beneficial effects of the utility model are: the utility model is simple in structure, reasonable in design, can effectively improve the simulation calculation accuracy, and adopts program control at the same time, has a higher degree of automation, is more convenient to use, and improves the performance of the simulation system. Analog performance.

Description of drawings

Fig. 1 is the structural representation of the utility model;

Fig. 2 is the utility model simulation system circuit diagram;

Fig. 3 is the judgment figure of simulation system signal in the utility model;

Fig. 4 is the simulation system strategy pre-judgment trend figure in the utility model embodiment;

Fig. 5 is a trend diagram of strategy prediction of the simulation system in another embodiment of the present invention.

detailed description

In order to make the purpose, technical solution and advantages of the utility model clearer, the utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model, and are not intended to limit the utility model.

Please refer to Fig. 1-5, Fig. 1 is the structure diagram of the present utility model, Fig. 2 is the circuit diagram of the emulation system of the present utility model, Fig. 3 is the signal judgment diagram of the emulation system in the present utility model, Fig. 4 is the simulation in the embodiment of the present utility model The system strategy prediction trend diagram, Fig. 5 is the optical frequency shift-light intensity test curve in another embodiment of the present utility model.

A rebound high-Q digital PLL phase-locked loop simulation system includes a central processing unit, a time constant generator, a frequency divider, a detection amplifier, an integrator, a simulation excitation source generator, a frequency stability tester and a frequency multiplier; The frequency divider is connected with a detection amplifier, and the detection amplifier is connected with an integrator, and the integrator is connected with a central controller; the central controller is connected with a simulation excitation source generator, a frequency multiplier, a frequency stability tester and a time A constant generator; the simulation excitation source generator is connected with a frequency stability tester, and the frequency multiplier is connected with a simulation excitation source generator and a frequency divider; the time constant generator is connected with a detection amplifier and an integrator respectively.

The mode that realizes each parameter adopts in the utility model is:

Multiple relationship strategy:

In the system in Figure 1, the preset frequency bands of our simulation system model are as follows:

(1) In order to realize the simulation response of the high frequency band, we choose a high frequency and high stability reference source, and the signal frequency obtained after the frequency division processing in Figure 1 is 50.****MHz. The **** of the decimal places (reserved to four digits) is random. For the convenience of explanation, we take ****=1234 in the implementation of this patent, that is, in Figure 1 is 50.1234MHz;

(2) The initialization simulation excitation generator set by the central controller outputs a 10MHz frequency signal;

(3), the initial frequency multiplier output signal frequency set by the central controller and The theoretical value is the same, that is, also 50.1234MHz;

(4) The output signal frequency of the simulation excitation generator is linked to the output signal frequency of the frequency multiplier.

The circuit structure to realize the above model is shown in Figure 2:

The processor is located in the central controller module in Figure 1, and the XTAL terminal of the processor is connected to the frequency signal of the same clock source as the RefClk terminal of DDS1 and DDS2 in Figure 2 to ensure time synchronization. On the basis of the external clock input terminal (XTAL) as the clock reference during operation, the processor generates three square wave signals with adjustable phase relationship, one of which is sent to the FSK key frequency modulation input port of DDS1 to realize frequency modulation 1. One channel of synchronous reference signal is used for synchronous phase detection, and one channel of judgment signal is used for lock detection of the phase locked loop in FIG. 1 . Based on the external clock reference input terminal (RefClk) of DDS1 as the reference clock during operation, through the serial timing communication between the processor and DDS1, DDS1 controls the high and low of the FM square wave signal according to the square wave key sent by the processor at the FSK end. The level state selects the multiplier modulation value preset frequency input by the processor in the internal frequency control register (F1, F0) as the output, thereby generating a modulated frequency signal 50.1234MHz±△f output. The preset frequency difference △f is determined by the values in the two frequency control registers F1 and F0. Specifically, considering that the radio frequency signal is 50.1234MHz (the 4th decimal place is precise), we take △f=100Hz. Similar to the above-mentioned principle of the processor controlling DDS1 to generate frequency multiplication modulation signals, the processor transmits the same frequency division value to DDS2 through the serial communication sequence to generate a 50.1234MHz frequency signal output without modulation. The 50.1234MHz frequency signal obtained by DDS2 is sent to the external clock reference input terminal (RefClk) of DDS3, which is used as the reference clock when DDS3 works. According to the serial timing communication, the processor transmits the corresponding initialization output frequency (10MHz) value to DDS3, so as to obtain the frequency signal output of the simulation excitation source generator. Since the external reference time base of DDS3 adopts the frequency multiplication signal generated by DDS2, in this scheme, when the central controller in the closed loop in Figure 1 obtains the corresponding phase detection signal information, it will modify the corresponding DDS2 multiplier The frequency of the frequency modulation signal will also cause the frequency of the DDS3 output signal to change, which replaces the traditional method of changing the output frequency value of the local oscillator through the D/A voltage-controlled crystal oscillator, and then changing the system output frequency. It is worth noting that the direct digital synthesis method is adopted for the output frequency signal, which makes it act as a synthesizer with high stability in a certain application range. Users can easily modify the frequency value of the DDS3 output signal through the user input port in Figure 2 according to the requirements in practical applications.

Time constant setting strategy

From the foregoing scheme, we can see that we set Equal to 1, while making Th=Ti. According to the multiple relationship strategy above, we make the signal frequency output by the simulation excitation source generator 10MHz, and the frequency after frequency division of the high stability reference source is selected as 50.1234MHz, according to the formula (5) , you can get M=5. It can be seen from the above multiple relationship strategy that we did not use the traditional method of changing the system output frequency value through the D/A voltage-controlled crystal oscillator in the design of the simulation system in Figure 1, so in Figure 1 The voltage control slope of the simulation excitation generator is unknown, we can only use is equal to 1 and obtained by M=5 * =1/5 conclusion. In the specific implementation process, according to Figure 1, we can only perform detection amplifiers through the central controller. value setting. Since the time constant in the simulation system is only determined by Th, according to Figure 1, we realize the setting of the detection time constant Th and integration time constant Ti of the detection amplifier and integrator through the control of the central controller to the time constant generator, and make Th=Ti.

Simulation system Q value strategy

In Figure 2, we generate three-way square wave signals through the processor: synchronous reference signal, keyed FM signal, and judgment signal, so that the frequency of the synchronous reference signal is equal to the frequency of the keyed FM signal, and there is a certain phase delay difference; at the same time Make the judgment signal frequency N (the value of N can be between 8 and 20) times the frequency of the synchronization reference signal or the frequency of the keying FM signal, and have a certain phase delay difference. Specifically, we take the frequency of the synchronous reference signal to be equal to the frequency of the keyed FM signal to be 169 Hz, and the phase difference between the two is 160 degrees; at the same time, we take the frequency N of the judgment signal to be 8 times, and the phase difference with the synchronous reference signal is 90 degrees.

The specific judgment basis is shown in Figure 3:

In Figure 3, the judging signal, synchronous reference signal, and keyed FM signal are square wave digital signals with a fixed frequency and phase relationship; the enable signal is either 1 or 0, so it can be regarded as a square wave without a fixed frequency Digital signal; the phase detection signal is generated by the integrator in Figure 1, which is a changing DC signal, so it can be regarded as an analog signal without a fixed frequency.

According to the principle of Figure 3 combined with Figure 1, we set a certain rising edge of the judgment signal as the trigger judgment start, complete 10 judgments before the arrival of the next rising edge, and then trigger the next group of 10 times when the next rising edge arrives. second judgment. Since we know the frequency of the judgment signal in Figure 3 in advance, that is, we know the time T between two adjacent rising edges, a group of 10 time intervals for judgment can be evenly distributed.

In Fig. 1, the central controller judges the phase detection signal delivered by the integrator according to the above-mentioned trigger judgment conditions, and when the magnitude of the analog DC signal is in the non-enabled strip area shown in Fig. 3, the central controller outputs the The enabling signal in Figure 3 is 0, and the frequency stability measuring instrument in Figure 1 does not work; when the magnitude of its analog DC signal is outside the non-enabled band area shown in Figure 3, the central controller outputs the enabling signal in Figure 3 The energy signal is 1, and the frequency stability measuring instrument in Figure 1 starts to work; the simulation Q value is actually the simulation test result value output by the frequency stability measuring instrument in Figure 1 when it is working, and it reflects the performance of the output signal of the simulation system in Figure 1.

During the entire simulation process, the central controller initializes all the desired setting values at the beginning, and these parameters will no longer change. During dynamic simulation, only the detector amplifier parameters The value of the time constant Th of the detector amplifier must be dynamically set by the central controller module, and the criterion for judging whether these two parameters are reasonable is the simulated Q value. we give The value takes a range of 1-10, and we also take a value of 1-10 for Th. At the beginning of the simulation of the system in Figure 1, in addition to setting the initial setting values of each channel, we will The corresponding Q value is obtained by simulating the full range of Th value and Th value. The Q value is between L and H, defined as L=1 to H=100 (the larger the Q value, the better), we define the Q value during this simulation time The data is the "modeled area".

During the dynamic simulation process, the system is carried out according to the principle shown in Figure 3 in most cases. In addition, we implement the "rebound" and "high Q" properties of the following two strategy evaluation systems. First, we compress the Q value obtained above, and take the Q value range (L=25 to L=50) to define it as the strategy value area Q1 , central controller setting value and Th value, and the time of sampling Q value are synchronized, and make setting Values and Th values change in opposite directions:

The first case: the next setting value (denoted as K2) compared with this time The value (denoted as K1) is increased (that is, K2>K1), then the next time the Th value (denoted as T2) is set to be smaller than the current Th value (denoted as T1) (that is, T2<T1).

Second case: next time setting value (denoted as K2) compared with this time The value (denoted as K1) is reduced (that is, K2<K1), then the next time the Th value (denoted as T2) is set to increase compared with the current Th value (denoted as T1) (that is, T2>T1).

One point that needs to be explained is: the central controller performs simulation according to the above two situations at any time. With the above operating mechanism, we have the following two strategies:

Embodiment 1: According to the above simulation, the "modeling area" of the Q value of the system is obtained first, as shown in FIG. 4 , and then the system randomly enters the above-mentioned first situation or the second situation. When the simulated Q value of the system is greater than H, that is, at point O in Figure 4, no matter whether the system is in the first situation or the second situation at this time, we will put the system in the first situation state, that is, increase value while decreasing the Th value, and making the parameter of increasing trend The value change is increased to 2 times the original value, that is, the next setting The value is 2*(K2-K1) of the change in the first case above, and the setting change value of Th value is the original (T2-T1), which we define as the third case. The simulation system has been simulating according to the fourth situation, as shown in Figure 4, the simulation result will theoretically follow the virtual strategy pre-judgment trend line in the figure to a certain H1 until the Q value drops, then we restore the original settings,

Embodiment 2: According to the above simulation, the "modeling area" of the Q value of the system is first obtained, as shown in FIG. 5 , and then the system randomly enters the above-mentioned first situation or the second situation. When the simulated Q value of the system appears at L1=25, and the Q value rises for three consecutive times, and rises to more than 33 (point O in Figure 5), no matter the system is in the first situation or the second In the first case, we will put the system in the second case state, which reduces Increase the Th value at the same time, and increase the change of the parameter Th value of the increasing trend to double the original value, that is, the next time the Th value is set to be 2*(T2-T1) of the change in the second case above, and at the same time The setting change value of is the original (K2-K1), which we define as the third case. The simulation system has been simulating according to the third situation, as shown in Figure 5, the simulation result will theoretically follow the virtual strategy pre-judgment trend line in the figure to a certain H1 until the Q value drops, then we restore the original settings.

The above descriptions are only preferred embodiments of the present utility model, and are not intended to limit the present utility model. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present utility model shall be included in this utility model. within the scope of protection of utility models.

Claims (7)

1. bounce-back high q-factor digital P LL phaselocked loop analogue system, it is characterised in that: include that central processing unit, time constant occur Device, frequency divider, detector amplifier, integrator, simulation excitation source generator, frequency stabilization tester and doubler；Described frequency divider is even Being connected to detector amplifier, described detector amplifier connects integrator, and described integrator connects central controller；Described central authorities Controller connects simulation excitation source generator, doubler, frequency stabilization tester and time constant generator；Described simulation excitation source Generator connects frequency stabilization tester, and described doubler connects simulation excitation source generator and frequency divider；Described time constant Generator connects with detector amplifier, integrator respectively.

Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: the described time Constant generator is made up of resistance and condenser type multistage connection in series-parallel loop.

Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: described central authorities Time constant Th=Ti that controller is respectively provided with detector amplifier, integrator is corresponding.

Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: described central authorities Controller is respectively provided with detector amplifier, simulation excitation generator, doubler、, M, make Equal to 1.

Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: described central authorities The initialization simulation excitation generator output 10MHz frequency signal that controller is arranged.

Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: described central authorities Controller arrange initialization doubler output signal frequency withTheoretical value is identical, is the most also 50.1234MHz.

Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: simulation excitation Generator output signal frequency and doubler output signal frequency have linkage connection.