CN205320045U - Ultra -low power consumption clock circuit with high stability - Google Patents
Ultra -low power consumption clock circuit with high stability Download PDFInfo
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- CN205320045U CN205320045U CN201620065678.2U CN201620065678U CN205320045U CN 205320045 U CN205320045 U CN 205320045U CN 201620065678 U CN201620065678 U CN 201620065678U CN 205320045 U CN205320045 U CN 205320045U
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Abstract
The utility model discloses an ultra -low power consumption clock circuit with high stability, including clock oscillation circuit and supply circuit, supply circuit is the power supply of clock oscillation circuit, supply circuit includes N type the first transistor and second transistor, P type third transistor and first electric capacity, N type the first transistor and P type third transistor connect between power V_DD and ground after establishing ties, the offset voltage load termination clock oscillation circuit's of N type the first transistor power input end, the offset voltage load termination reference voltage of P type third transistor, N type second crystal pipe connector constitutes negative feedback circuit between the offset voltage loading end of power V_DD and N type the first transistor. The utility model discloses insensitive to power, technology angle and temperature variation, clock frequency is stable, the circuit low power dissipation, and simple structure, it is with low costs.
Description
Technical field
This utility model belongs to clock circuit field, more particularly to a kind of high stability super low-power consumption clock circuit of clock frequency.
Background technology
Clock circuit produces as clock oscillating circuit accurately exactly. Clock circuit application is very extensive, such as the clock circuit of the clock circuit of computer, the clock circuit of electronic watch and MP3, MP4. In digital display circuit, the quality of clock source directly determines whether stablizing of this systematic function. And the quality of clock source depends primarily on when environmental factors changes such as supply voltage, temperature and process corner, whether clock frequency is stable.
Utilize the clock source signals that quartz oscillator obtains, such as publication: CN201607626U, superior voltage and temperature characterisitic is had due to quartz crystal oscillator, can stably work, so the quality of clock source signals is good, but its cost is high, and power consumption is big, and it is difficult to integrate into chip internal, hinder the Highgrade integration of chip. and present IC design trends towards high integration, chip area is little, the feature such as low in energy consumption, therefore, require that the circuit that designer uses structure simpler is to obtain clock signal, utilize switching tube and electric capacity composition clock circuit, for reducing cost and the power consumption of system, the integrated level of raising system is by helpful, but it is to supply voltage, temperature and technique change are more sensitive, clock frequency is unstable, extensive use cannot be obtained, and in order to obtain stable clock frequency, existing way is to increase various auxiliary circuit, such as publication: CN101443666B, its temperature detected according to the temperature sensor on integrated circuit, Open loop temperature compensation is realized by regulable control word, higher clock accuracy can be realized by carrying out regulable control word for flow-route and temperature. although obtaining frequency stable, the clock signal that precision is high, but its structure is complicated, and components and parts are many so that cost and power consumption are high.
Summary of the invention
The purpose of this utility model is in that to provide a kind of that power supply, process corner and variations in temperature is insensitive for solving the problems referred to above, and simple in construction, what cost was low has the super low-power consumption clock circuit of high stability.
For this, the utility model discloses a kind of super low-power consumption clock circuit with high stability, including clock oscillation circuit and power supply circuits, described power supply circuits are that clock oscillation circuit is powered, described power supply circuits include N-type the first transistor and transistor seconds, P type third transistor and the first electric capacity, described N-type the first transistor and the series connection of P type third transistor are followed by between power supply V_DD and ground, the bias voltage of described N-type the first transistor loads the power input of termination clock oscillation circuit, the bias voltage of described P type third transistor loads termination reference voltage, the 3rd reference current is accessed between described power supply V_DD and N-type first crystal, described first electric capacity is in parallel with N-type the first transistor and P type third transistor, described N-type transistor seconds is connected between the bias voltage loading end of power supply V_DD and N-type the first transistor, constitute negative-feedback circuit, the bias voltage loading end of described N-type transistor seconds is connected on the node between the 3rd reference current and N-type the first transistor.
Further, described N-type the first transistor is N-type metal-oxide-semiconductor or NPN audion.
Further, described N-type transistor seconds is N-type metal-oxide-semiconductor or NPN audion.
Further, described P type third transistor is P type metal-oxide-semiconductor or PNP triode.
Further, described clock oscillation circuit includes charge-discharge circuit and the hysteresis circuitry being connected with charge-discharge circuit, described charge-discharge circuit includes the first reference current IBIAS1, second reference current IBIAS2, second electric capacity, 4th N-type metal-oxide-semiconductor and the 5th P type metal-oxide-semiconductor, described first reference current IBIAS1, 5th P type metal-oxide-semiconductor, 4th N-type metal-oxide-semiconductor and the second reference current IBIAS2 are sequentially connected in series and are followed by between bias voltage loading end and the ground of N-type the first transistor, the top crown of described second electric capacity is connected on the node between the 4th N-type metal-oxide-semiconductor and the 5th P type metal-oxide-semiconductor, the bottom crown ground connection of described second electric capacity, the grid of described 4th N-type metal-oxide-semiconductor and the 5th P type metal-oxide-semiconductor connects clock signal output terminal.
Further, described clock oscillation circuit includes charge-discharge circuit and the hysteresis circuitry being connected with charge-discharge circuit, described charge-discharge circuit includes the first reference current IBIAS1, resistance R1, second electric capacity, 4th N-type metal-oxide-semiconductor and the 5th P type metal-oxide-semiconductor, described first reference current IBIAS1, 5th P type metal-oxide-semiconductor, 4th N-type metal-oxide-semiconductor and resistance R1 are sequentially connected in series and are followed by between bias voltage loading end and the ground of N-type the first transistor, the top crown of described second electric capacity is connected on the node between the 4th N-type metal-oxide-semiconductor and the 5th P type metal-oxide-semiconductor, the bottom crown ground connection of described second electric capacity, the grid of described 4th N-type metal-oxide-semiconductor and the 5th P type metal-oxide-semiconductor connects clock signal output terminal.
Advantageous Effects of the present utility model:
This utility model makes full use of the characteristic of semiconductor device and is designed so that supply voltage is from 1.2V to 3V, and temperature changes to 120 DEG C from-40 DEG C simultaneously, lower than under several μ w, power all can guarantee that clock frequency stably exports, frequency changes less than 12%, and namely that power supply, process corner and variations in temperature is insensitive, circuit structure is simple, without external devices, power consumption and cost are low, and application is convenient, and the frequency range covered is wide, all applicable from a few about KHz to 20M, applied widely.
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams of this utility model embodiment one;
Fig. 2 is the supply voltage variation diagram with supply voltage of this utility model embodiment one;
The supply voltage that Fig. 3 is this utility model embodiment one varies with temperature figure;
Fig. 4 is the circuit theory diagrams of this utility model embodiment two;
Fig. 5 is the circuit theory diagrams of this utility model embodiment three;
Fig. 6 is the circuit theory diagrams of this utility model embodiment four.
Detailed description of the invention
In conjunction with the drawings and specific embodiments, this utility model is further illustrated.
Embodiment one:
As shown in Figure 1, a kind of super low-power consumption clock circuit with high stability, including clock oscillation circuit and power supply circuits, described power supply circuits provide power supply V_sup for clock oscillation circuit, described power supply circuits include N-type the first transistor and transistor seconds, P type third transistor and electric capacity C1 (the first electric capacity), in the present embodiment, N-type the first transistor and N-type transistor seconds are N-type metal-oxide-semiconductor MN1 and MN7, P type third transistor is P type metal-oxide-semiconductor MP1, the source electrode of described N-type metal-oxide-semiconductor MN1 and P type metal-oxide-semiconductor MP1 is connected, the drain electrode of N-type metal-oxide-semiconductor MN1 meets power supply V_DD, the grounded drain of P type metal-oxide-semiconductor MP1, the grid (bias voltage loading end) of described N-type metal-oxide-semiconductor MN1 meets the power input V_sup of clock oscillation circuit, power supply V_sup is provided for clock oscillation circuit, the grid (bias voltage loading end) of P type metal-oxide-semiconductor MP1 meets reference voltage V _ BIAS, different size of power supply V_sup can be obtained by adjusting reference voltage V _ BIAS, the 3rd reference current IBIAS3 is accessed between the drain electrode of described power supply V_DD and N-type metal-oxide-semiconductor MN1, described electric capacity C1 and N-type metal-oxide-semiconductor MN1 and P type metal-oxide-semiconductor MP1 is in parallel, effect is to make circuit stability, the drain electrode of described N-type metal-oxide-semiconductor MN7 meets power supply V_DD, the source electrode of N-type metal-oxide-semiconductor MN7 connects the grid of N-type metal-oxide-semiconductor MN1, the grid (bias voltage loading end) of N-type metal-oxide-semiconductor MN7 connects the drain electrode of N-type metal-oxide-semiconductor MN1, constitute negative-feedback circuit, when power supply V_DD is changed, power supply V_sup is held essentially constant.
Described clock oscillation circuit includes charge-discharge circuit and the hysteresis circuitry being connected with charge-discharge circuit, it includes the first reference current IBIAS1, second reference current IBIAS2, electric capacity C2 (the second electric capacity), N-type metal-oxide-semiconductor MN2-MN6 and P type metal-oxide-semiconductor MP2-MP6, described first reference current IBIAS1, P type metal-oxide-semiconductor MP2 (the 5th P type metal-oxide-semiconductor), N-type metal-oxide-semiconductor MN2 (the 4th N-type metal-oxide-semiconductor) and the second reference current IBIAS2 is sequentially connected in series and is followed by between grid and the ground of N-type metal-oxide-semiconductor MN1, the top crown of described electric capacity C2 is connected on the node V_1 between P type metal-oxide-semiconductor MP2 and N-type metal-oxide-semiconductor MN2, the bottom crown ground connection of described electric capacity C2, the grid (control end) of described N-type metal-oxide-semiconductor MN2 and P type metal-oxide-semiconductor MP2 meets clock signal output terminal clock, constitute charge-discharge circuit, P type metal-oxide-semiconductor MP3, MP4 and N-type metal-oxide-semiconductor MN3, MN4 is sequentially connected in series and is followed by between power supply V_sup and ground, P type metal-oxide-semiconductor MP3, MP4 and N-type metal-oxide-semiconductor MN3, the grid of MN4 connects the top crown of electric capacity C2, the source electrode of P type metal-oxide-semiconductor MP5 meets power supply V_sup, the drain electrode of P type metal-oxide-semiconductor MP5 connects the drain electrode of P type metal-oxide-semiconductor MP3, the grid of P type metal-oxide-semiconductor MP5 meets clock signal output terminal clock, the source ground of N-type metal-oxide-semiconductor MN5, the drain electrode of N-type metal-oxide-semiconductor MN5 connects the drain electrode of N-type metal-oxide-semiconductor MN4, the grid of N-type metal-oxide-semiconductor MN5 meets clock signal output terminal clock, the drain electrode of N-type metal-oxide-semiconductor MN6 and P type metal-oxide-semiconductor MN6 is connected, the source electrode of P type metal-oxide-semiconductor MP6 meets power supply V_sup, the source ground of N-type metal-oxide-semiconductor MN6, the grid of N-type metal-oxide-semiconductor MN6 and P type metal-oxide-semiconductor MP6 is connected on the node V_2 between P type metal-oxide-semiconductor MP4 and the drain electrode of N-type metal-oxide-semiconductor MN3, node between the drain electrode of N-type metal-oxide-semiconductor MN6 and P type metal-oxide-semiconductor MP6 is that clock signal output terminal clock constitutes hysteresis circuitry.
Operation principle is sketched:
When V_1 is low level, V_2 is high level, and clock signal output terminal clock is low level, and now P type metal-oxide-semiconductor MP2 opens, and N-type metal-oxide-semiconductor MN2 turns off, and electric capacity C2 is charged by the first reference current IBIAS1. And owing to clock signal output terminal clock is low-voltage, P type metal-oxide-semiconductor MP5 opens and by P type metal-oxide-semiconductor MP3 source electrode and drain short circuit, N-type metal-oxide-semiconductor MN5 turns off, and now the pipe sizes of P type metal-oxide-semiconductor MP4, P type metal-oxide-semiconductor MP5, N-type metal-oxide-semiconductor MN3 and N-type metal-oxide-semiconductor MN4 determines the forward threshold voltage V of this clock oscillation circuit+. When V_1 is high level, V_2 is low level, and clock signal output terminal clock is high level, and now P type metal-oxide-semiconductor MP2 turns off, and N-type metal-oxide-semiconductor MN2 opens, and electric capacity C2 is discharged by the second reference current IBIAS2. And owing to clock signal output terminal clock voltage is high level, N-type metal-oxide-semiconductor MN5 opens and by N-type metal-oxide-semiconductor MN4 source electrode and drain short circuit, P type metal-oxide-semiconductor MP5 turns off, and now the pipe sizes of P type metal-oxide-semiconductor MP3, P type metal-oxide-semiconductor MP4, N-type metal-oxide-semiconductor MN3 and N-type metal-oxide-semiconductor MN5 determines the reverse threshold voltage V of this clock oscillation circuit-. The hysteresis voltage of this circuit is VTH=V+-V-, during real work, circuit is exactly ceaselessly to capacitor charge and discharge, thus producing clock signal. Due to the delay V of circuit itself during real workTHCan change along with the change in voltage of the power supply V_sup of clock oscillation circuit. The ratio of the first reference current IBIAS1 and the second reference current IBIAS2 determines the dutycycle of clock signal simultaneously.
N-type metal-oxide-semiconductor MN1 and MN2 constitutes negative-feedback circuit so that still ensure that during the change in voltage of power supply V_DD that power supply V_sup is basically unchanged (as in figure 2 it is shown, when power supply V_DD voltage changes to 3V from 1.2V, power supply V_sup just changes about 0.26mV). Thus ensureing the hysteresis voltage V of circuitTHWithout change so that the frequency of clock will not be followed the change of power supply V_DD voltage and be changed.
N-type metal-oxide-semiconductor MN1 and P type metal-oxide-semiconductor MP1 series connection, clock oscillation circuit can be followed by change according to same trend when variations in temperature or process deviation, such as, when temperature raises, the voltage of power supply V_sup declines, (Fig. 3 illustrates that temperature is from-40 DEG C to 120 DEG C as shown in Figure 3, the situation of change of power supply V_sup), provide suitable V for clock oscillation circuitTH, thus there is the effect of temperature-compensating and technique deviation compensation so that frequency tends towards stability, thus obtaining accurate clock signal.
In the present embodiment, the switching tube of the same model of power supply circuits and clock oscillation circuit preferably selects same batch, so can avoid the diversity that different batches process deviation brings so that variation tendency is more consistent, and clock frequency is more stable.
Embodiment two:
As shown in Figure 4, the present embodiment and embodiment one are distinctive in that: the second reference current IBIAS2 of embodiment one is replaced to resistance R1, the function of resistance R1 is identical with the second reference current IBIAS2, can adjust the dutycycle of clock signal by regulating the size of resistance R1. Operation principle is referred to embodiment one.
Embodiment three:
As shown in Figure 5, the present embodiment and embodiment one are distinctive in that: in the present embodiment, described the first transistor is NPN audion NPN1, third transistor is PNP triode PNP1, the emitter stage of described NPN audion NPN1 and PNP triode PNP1 is connected, the colelctor electrode of NPN audion NPN1 meets power supply V_DD, the grounded collector of PNP triode PNP1, the base stage (bias voltage loading end) of described NPN audion NPN1 meets the power input V_sup of clock oscillation circuit, power supply V_sup is provided for clock oscillation circuit, the base stage (bias voltage loading end) of NPN audion PNP1 meets reference voltage V _ BIAS, different size of power supply V_sup can be obtained by adjusting reference voltage V _ BIAS, the 3rd reference current IBIAS3 is accessed between the colelctor electrode of described power supply V_DD and NPN audion NPN1, described electric capacity C1 and NPN audion NPN1 and PNP triode PNP1 is in parallel, make circuit stability, the drain electrode of described N-type metal-oxide-semiconductor MN7 is at power supply V_DD, the source electrode of N-type metal-oxide-semiconductor MN7 connects the base stage of NPN audion NPN1, the grid (bias voltage loading end) of N-type metal-oxide-semiconductor MN7 connects the colelctor electrode of NPN audion NPN1, constitute negative-feedback circuit, when power supply V_DD is changed, power supply V_sup is held essentially constant.Its operation principle is referred to embodiment one.
Embodiment four:
As shown in Figure 6, the present embodiment and embodiment three are distinctive in that: described transistor seconds is NPN audion NPN2. the emitter stage of described NPN audion NPN1 and audion PNP1 is connected, the colelctor electrode of NPN audion NPN1 meets power supply V_DD, the grounded collector of PNP triode PNP1, the base stage (bias voltage loading end) of described NPN audion NPN1 meets the power input V_sup of clock oscillation circuit, power supply V_sup is provided for clock oscillation circuit, the base stage (bias voltage loading end) of PNP triode PNP1 meets reference voltage V _ BIAS, different size of power supply V_sup can be obtained by adjusting reference voltage V _ BIAS, the 3rd reference current IBIAS3 is accessed between the colelctor electrode of described power supply V_DD and NPN audion NPN1, described electric capacity C1 and NPN audion NPN1 and PNP triode PNP1 is in parallel, the effect of electric capacity C1 is to make circuit stability, the colelctor electrode of described NPN audion NPN2 is at power supply V_DD, the emitter stage of NPN audion NPN2 connects the base stage of NPN audion NPN1, the base stage (bias voltage loading end) of NPN audion NPN2 connects the colelctor electrode of NPN audion NPN1, constitute negative-feedback circuit, when power supply V_DD is changed, power supply V_sup is held essentially constant. its operation principle is referred to embodiment one.
Certainly, in other embodiments, first, second and third transistor of power supply circuits can respectively N-type metal-oxide-semiconductor, NPN audion, P type metal-oxide-semiconductor or N-type metal-oxide-semiconductor, NPN audion, PNP triode or NPN audion, NPN audion, P type metal-oxide-semiconductor or N-type metal-oxide-semiconductor, N-type metal-oxide-semiconductor, PNP triode or NPN audion, N-type metal-oxide-semiconductor, P type metal-oxide-semiconductor etc., its connected mode is referred to above-described embodiment, and this no longer describes in detail.
Certainly, in other embodiments, the power supply circuits of embodiment three and embodiment four can also be combined with the clock oscillation circuit of embodiment two respectively, obtain new clock circuit, or the power supply circuits in above-mentioned other embodiments are combined with the clock oscillation circuit of embodiment one or embodiment two respectively the clock circuit that composition is new.
In sum, this utility model adopts pass open pipe and electric capacity to form the clock circuit that power supply, process corner and variations in temperature is insensitive, the characteristic making full use of semiconductor device is designed, make supply voltage from 1.2V to 3V, temperature changes to 120 DEG C from-40 DEG C simultaneously, lower than under several μ w, power all can guarantee that clock frequency stably exports, frequency changes less than 12%, circuit structure is simple, it is not necessary to external devices, and power consumption and cost are low, application is convenient, and the frequency range covered is extensively, all applicable from a few about KHz to 20M, applied widely.
Although specifically showing in conjunction with preferred embodiment and describing this utility model; but those skilled in the art should be understood that; in the spirit and scope of the present utility model limited without departing from appended claims; this utility model can be made a variety of changes in the form and details, be protection domain of the present utility model.
Claims (6)
1. a super low-power consumption clock circuit with high stability, including clock oscillation circuit and power supply circuits, described power supply circuits are that clock oscillation circuit is powered, it is characterized in that: described power supply circuits include N-type the first transistor and transistor seconds, P type third transistor and the first electric capacity, described N-type the first transistor and the series connection of P type third transistor are followed by between power supply V_DD and ground, the bias voltage of described N-type the first transistor loads the power input of termination clock oscillation circuit, the bias voltage of described P type third transistor loads termination reference voltage, the 3rd reference current is accessed between described power supply V_DD and N-type first crystal, described first electric capacity is in parallel with N-type the first transistor and P type third transistor, described N-type transistor seconds is connected between the bias voltage loading end of power supply V_DD and N-type the first transistor, constitute negative-feedback circuit, the bias voltage loading end of described N-type transistor seconds is connected on the node between the 3rd reference current and N-type the first transistor.
2. the super low-power consumption clock circuit with high stability according to claim 1, it is characterised in that: described N-type the first transistor is N-type metal-oxide-semiconductor or NPN audion.
3. the super low-power consumption clock circuit with high stability according to claim 1, it is characterised in that: described N-type transistor seconds is N-type metal-oxide-semiconductor or NPN audion.
4. the super low-power consumption clock circuit with high stability according to claim 1, it is characterised in that: described P type third transistor is P type metal-oxide-semiconductor or PNP triode.
5. the super low-power consumption clock circuit with high stability according to any one of claim 1-4, it is characterized in that: described clock oscillation circuit includes charge-discharge circuit and the hysteresis circuitry being connected with charge-discharge circuit, described charge-discharge circuit includes the first reference current IBIAS1, second reference current IBIAS2, second electric capacity, 4th N-type metal-oxide-semiconductor and the 5th P type metal-oxide-semiconductor, described first reference current IBIAS1, 5th P type metal-oxide-semiconductor, 4th N-type metal-oxide-semiconductor and the second reference current IBIAS2 are sequentially connected in series and are followed by between bias voltage loading end and the ground of N-type the first transistor, the top crown of described second electric capacity is connected on the node between the 4th N-type metal-oxide-semiconductor and the 5th P type metal-oxide-semiconductor, the bottom crown ground connection of described second electric capacity, the grid of described 4th N-type metal-oxide-semiconductor and the 5th P type metal-oxide-semiconductor connects clock signal output terminal.
6. the super low-power consumption clock circuit with high stability according to any one of claim 1-4, it is characterized in that: described clock oscillation circuit includes charge-discharge circuit and the hysteresis circuitry being connected with charge-discharge circuit, described charge-discharge circuit includes the first reference current IBIAS1, resistance R1, second electric capacity, 4th N-type metal-oxide-semiconductor and the 5th P type metal-oxide-semiconductor, described first reference current IBIAS1, 5th P type metal-oxide-semiconductor, 4th N-type metal-oxide-semiconductor and resistance R1 are sequentially connected in series and are followed by between bias voltage loading end and the ground of N-type the first transistor, the top crown of described second electric capacity is connected on the node between the 4th N-type metal-oxide-semiconductor and the 5th P type metal-oxide-semiconductor, the bottom crown ground connection of described second electric capacity, the grid of described 4th N-type metal-oxide-semiconductor and the 5th P type metal-oxide-semiconductor connects clock signal output terminal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620065678.2U CN205320045U (en) | 2016-01-22 | 2016-01-22 | Ultra -low power consumption clock circuit with high stability |
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| CN201620065678.2U CN205320045U (en) | 2016-01-22 | 2016-01-22 | Ultra -low power consumption clock circuit with high stability |
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| CN201620065678.2U Withdrawn - After Issue CN205320045U (en) | 2016-01-22 | 2016-01-22 | Ultra -low power consumption clock circuit with high stability |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105515550A (en) * | 2016-01-22 | 2016-04-20 | 英麦科（厦门）微电子科技有限公司 | Ultra-low power consumption clock circuit with high stability |
| CN109362311A (en) * | 2018-09-30 | 2019-02-22 | 天津市宝坻区青青蔬菜种植专业合作社 | A kind of supply of data volume nutrient solution root system and light-supplementing system |
-
2016
- 2016-01-22 CN CN201620065678.2U patent/CN205320045U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105515550A (en) * | 2016-01-22 | 2016-04-20 | 英麦科（厦门）微电子科技有限公司 | Ultra-low power consumption clock circuit with high stability |
| CN105515550B (en) * | 2016-01-22 | 2017-12-29 | 英麦科（厦门）微电子科技有限公司 | A kind of super low-power consumption clock circuit with high stability |
| CN109362311A (en) * | 2018-09-30 | 2019-02-22 | 天津市宝坻区青青蔬菜种植专业合作社 | A kind of supply of data volume nutrient solution root system and light-supplementing system |
| CN109362311B (en) * | 2018-09-30 | 2024-02-23 | 天津市宝坻区青青蔬菜种植专业合作社 | Data volume nutrient solution root system supply and light filling system |
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