CN205068388U - Receive DPHY serial signal's two frequency dividing circuit - Google Patents

Abstract

The utility model provides a two-frequency division circuit for receiving DPHY serial signals, receiving the output signal of DPHY, and performing two-frequency division processing on it, including: a DPHY receiver, two differential registers and at least four differential transponders ; The phases of the clock signals of the two differential registers are opposite; one data signal output end of the two differential registers is respectively connected to the corresponding data signal input end in reverse phase; the other data signal output ends of the two differential registers are connected to at least four The data signal input terminals of the two differential transponders are connected. Use the DPHY receiver, two differential registers and at least four differential transponders to divide the DPHY output signal by two, thereby increasing the rate at which the FPGA receives DPHY serial data, which can meet the speed requirements of various verification platforms for DPHY , and the implementation is simple, safe and reliable.

Description

A frequency division circuit for receiving DPHY serial signals

technical field

The utility model relates to the field of integrated circuits, in particular to a two-frequency division circuit for receiving DPHY serial signals.

Background technique

The MIPI (Mobile Industry Processor Interface, Mobile Industry Processor Interface) DPHY standard is a protocol for mobile application communication proposed by the MIPI Alliance. Due to serial transmission, high bandwidth, and simple sending and receiving, it is widely used in various mobile devices such as image sensors. With the continuous improvement of the transmission rate (datarate) (currently the highest commercial rate has reached 2.5Gbps), both sending and receiving are facing severe challenges, especially for the FPGA receiving end.

The current common way for FPGA to receive DPHY data is to use LVDS (Low-VoltageDifferentialSignaling low-voltage differential signal) interface, serial clock or enter FPGAPLL (PhaseLockedLogic, phase-locked loop), PLL output sampling clock to drive LVDS interface to sample serial data, or Direct sampling of incoming serial data. However, the LVDS interface of the FPGA is limited by physics and technology, and can only receive data with a serial rate not exceeding 1.6Gbps. The utility model provides a circuit for dividing the frequency of the DPHY serial data and the serial clock by two, which can significantly improve the rate of the DPHY serial data received by the FPGA.

Utility model content

The purpose of the utility model is to provide a two-frequency division circuit for receiving DPHY serial signals, so as to improve the rate of DPHY serial data received by FPGA.

In order to achieve the above object, the utility model provides a frequency division circuit for receiving DPHY serial signals, which is characterized in that it includes a DPHY receiver, two differential registers and at least four differential transponders;

The input terminal of the DPHY receiver receives the serial output signal of the DPHY and separates the differential data signal, and the differential data signal output terminal of the DPHY receiver outputs the differential data signal and is respectively compared with the data of the two differential registers. The signal input terminal is connected, and the clock signal output terminal of the DPHY receiver is respectively connected to the clock signal input terminals of the two differential registers and makes the phases of the clock signals of the two differential registers opposite;

One of the multiple data signal output terminals of each differential register is connected inversely to a corresponding data signal input terminal, and the data signal output terminal is used as the clock signal output terminal of the differential register, and at the same time The data signal output terminal is connected to the data signal input terminal of one of the differential transponders, and the other data signal output terminals of each differential register are respectively connected to the data signal input terminals of other differential transponders.

Preferably, in the above-mentioned divide-by-two circuit for receiving DPHY serial signals, there is a first node on the connection wire between the differential data signal output terminal of the DPHY receiver and the data signal input terminals of the two differential registers , the first node is set close to the differential register.

Preferably, in the above-mentioned divide-by-two circuit for receiving DPHY serial signals, a first resistor and a second resistor are also included; one end of the first resistor is connected to the first node, and the other end is connected to a first node. A pull-up voltage connection; one end of the second resistor is connected to the first node, and the other end is connected to the ground.

Preferably, in the above-mentioned divide-by-two circuit for receiving DPHY serial signals, there is a second node on a wire connected inversely to a data signal output terminal of the two differential registers and its corresponding data signal input terminal , the second node is set close to the data signal input end of the differential register.

Preferably, in the above-mentioned divide-by-two circuit for receiving DPHY serial signals, a third resistor and a fourth resistor are also included; one end of the third resistor is connected to the second node, and the other end is connected to a first Two pull-up voltage connections; one end of the fourth resistor is connected to the second node, and the other end is connected to the ground.

Preferably, the above-mentioned divide-by-two circuit for receiving DPHY serial signals further includes a seventh resistor, one end of the seventh resistor is connected to the second node, and the other end is connected to a fourth pull-up voltage .

Preferably, in the above-mentioned divide-by-two circuit for receiving DPHY serial signals, the fourth pull-up voltage is provided by a power supply capable of sinking current.

Preferably, in the above-mentioned divide-by-two circuit for receiving DPHY serial signals, there is a third node, and the third node is set close to the differential transponder.

Preferably, in the above-mentioned divide-by-two circuit for receiving DPHY serial signals, a fifth resistor and a sixth resistor are also included; one end of the fifth resistor is connected to the third node, and the other end is connected to a first Three pull-up voltage connections; one end of the sixth resistor is connected to the third node, and the other end is connected to the ground.

Preferably, in the above-mentioned divide-by-two circuit for receiving DPHY serial signals, an eighth resistor is further included, one end of the eighth resistor is connected to the third node, and the other end is connected to a fifth pull-up voltage , the fifth pull-up voltage is provided by a power source capable of sinking current.

In the two-frequency division circuit for receiving DPHY serial signals provided by the utility model, a DPHY receiver, two differential registers and at least four differential transponders are used to perform two-frequency division processing on the output signal of DPHY, including the Both the data output signal and the clock output signal of DPHY are divided by two, thereby increasing the rate at which FPGA receives DPHY serial data, which can meet the requirements of various verification platforms for the speed of DPHY, and the implementation is simple, safe and reliable.

Description of drawings

Fig. 1 is the schematic diagram of the two frequency division circuit in the utility model embodiment one;

FIG. 2 is a schematic structural diagram of a DPHY receiver in Embodiment 1 of the present invention;

3 is a schematic structural diagram of the first differential register in Embodiment 1 of the present invention;

4 is a schematic structural diagram of a second differential register in Embodiment 1 of the present invention;

5 is a connection diagram between the differential data signal output terminals DHP0_M, DHN0_M and the first differential register and the second differential register of the DPHY receiver in Embodiment 1 of the present utility model;

6 is a connection diagram between the clock signal output terminal of the DPHY receiver and the first differential register and the second differential register in Embodiment 1 of the present invention;

7 is a connection diagram of the data signal output terminals DHP0_SP, DHN0_SP of the first differential register and a differential transponder in Embodiment 1 of the present utility model;

FIG. 8 is a timing diagram of a two-frequency division circuit in Embodiment 1 of the present utility model;

FIG. 9 is a schematic structural diagram of the first differential register in Embodiment 2 of the present invention;

FIG. 10 is a schematic structural diagram of the second differential register in Embodiment 2 of the present invention;

11 is a connection diagram of the data signal output terminals DHP0_SP, DHN0_SP of the first differential register and a differential transponder in Embodiment 2 of the present invention;

In the figure: 100-DPHY receiver; 201-first differential register; 202-second differential register; 300-differential transponder.

detailed description

The specific embodiment of the utility model will be described in detail below in conjunction with the schematic diagram. According to the following description combined with the claims, the advantages and features of the utility model will be more clear. It should be noted that the drawings are all in very simplified form and use imprecise ratios, which are only used to facilitate and clearly assist the purpose of illustrating the embodiment of the present utility model.

Embodiment one

An embodiment of the present invention provides a two-frequency division circuit for receiving DPHY serial signals, which is used to receive serial output signals of DPHY, and the two-frequency division circuit performs two frequency divisions on the serial output signals of DPHY, including The serial data and the serial clock are divided by two, and then the divided serial data and serial clock are sent to the FPGA chip.

Specifically, as shown in Figure 1, it includes: a DPHY receiver, two differential registers, and at least four differential transponders; the DPHY receiver is used to receive the serial output signal of the DPHY, and output from the serial A differential data signal and a single-ended signal are separated from the signal, the differential data signal is output from the differential data signal output end of the DPHY receiver, and the single-ended signal is directly connected to the FPGA chip. Of course, in other embodiments of the present invention, the single-ended signal can also be detected by a dual-voltage LVCMOS transceiver, and then sent to the FPGA chip.

The serial data signal and the serial clock signal of the DPHY are respectively output as an LVDS differential signal through two signal lines p and n, and that is to say, each output terminal of the DPHY has two signal lines, which are the same as Each signal input terminal of the DPHY receiver connected to the output terminal of the DPHY also has two signal lines. The DPHY has multiple data signal output terminals and a clock signal output terminal, therefore, the DPHY receiver also has multiple data signal input terminals and a clock signal input terminal. For example, as shown in Figure 2, the DPHY receiver has 4 data signal input ports for receiving the data signals output by the DPHY, which are DHP0, DHN0, DHP1, DHN1, DHP2, DHN2 and DHP3, DHN3, and One clock signal input terminal CHP, CHN is used to receive the clock signal output by the DPHY. The differential signal output terminals of the DPHY receiver corresponding to these signal input terminals are: 4 data signal output terminals: DHP0_M, DHN0_M, DHP1_M, DHN1_M, DHP2_M, DHN2_M and DHP3_M, DHN3_M, and 1 clock signal output terminal CHP_M, CHN_M. In this embodiment, the DPHY receiver uses the MC20901 chip. In other embodiments of the present invention, other chips can also be used, as long as the single-ended signal and the differential signal can be separated and the conversion of the voltage standard can be realized. . The 1.2V large signal output by the DPHY can be separated by the DPHY receiver, and of course it can also be detected and output by a common single-ended dual-voltage signal transceiver, such as the SN74AVC2T45 chip.

The differential data signal output terminals of the DPHY receiver are respectively connected to the data signal input terminals of the two differential registers, and the clock signal output terminals of the DPHY receiver are respectively connected to the clock signal input terminals of the two differential registers , and make the phases of the clock signal input ends of the two differential registers opposite.

Specifically, in the embodiment of the present utility model, two differential registers are included, namely the first differential register and the second differential register, and each data signal output terminal of the DPHY receiver is the data of the first differential register When the signal input terminal is connected, it is also connected to the data signal input terminal of the second differential register, so that the data output signal of the DPHY receiver is frequency-divided by two, that is, the frequency-divided data output signal is obtained. In this embodiment, the two differential registers are both SY10EP451L chips. Likewise, in other embodiments of the present utility model, the differential register includes and is not limited to the SY10EP451L chip, as long as the functions are the same.

Continuing from the above example, DHP0_M, DHN0_M, DHP1_M, DHN1_M, DHP2_M, DHN2_M and DHP3_M, DHN3_M are respectively connected to the data signal input terminals of the first differential register and the second differential register.

Preferably, the connection between the DPHY receiver and the two differential registers adopts a four-resistor network to realize conversion from LVDS to LVPECL (LowVoltagePositiveEmitter-CoupleLogic), that is, in the DPHY receiver Four resistors are arranged between the two differential registers, and the output signal of the DPHY receiver (including data signals and clock signals) is connected to the input terminals of the two differential registers after passing through the four resistor networks. (Including data signal input and clock signal input) connection. That is, between each output terminal (including a data signal output terminal and a clock signal output terminal) of the DPHY receiver and each input terminal of the two differential registers (including a data signal input terminal and a clock signal input terminal) terminal) is provided with four resistors. Specifically, the connection between each output terminal (including a data signal input terminal and a clock signal input terminal) of the DPHY receiver and each input terminal (including a data signal input terminal and a clock signal input terminal) of the two differential registers There is a first node A on the connecting wire, and the first node A is set close to the two differential registers, _one end of a first resistor R1 is connected to the first node, and the other end is connected to a first pull-up voltage connected, one end of a _second resistor R2 is connected to the first node, and the other end is connected to the ground. In addition, the wiring distance between the first node and the data signal input end of the corresponding differential register is equal.

Continuing from the above example, as shown in FIG. 5, taking one output terminal DHP0_M and DHN0_M of the DPHY receiver as an example, the DHP0_M and DHN0_M are connected to the data signal input terminals of the first differential register and the second differential register. There is the first node (A ₀ , A' ₀ ) on the wire, one end of the first resistor R ₁₀ is connected to the first node A ₀ , and the other end is connected to the first pull-up voltage V ₁₀ , One end of the second resistor _R20 is connected to the first node _A0 , and the other end is connected to the ground. One end of the first resistor _R'10 is connected to the first node _A'0 , the other end is connected to the first pull-up voltage V'10, and _one end of the second resistor _R'20 is connected to the first node A'0. One node A' is connected to ₀ and the other end is connected to ground. Similarly, as shown in FIG. 6, the first node (A _C , A' _C ) is on the wire connected to the clock signal input ends of the first differential register and the second differential register between the CHP_M and CHN_M , one end of the first resistor R _1C is connected to the first node A _C , the other end is connected to the first pull-up voltage V _C , one end of the second resistor R _2C is connected to the first node A _C is connected, and the other end is connected to ground. One end of the first resistor _R'1C is connected to the first node _A'C , and the other end is connected to the first pull-up voltage _V'C , and one end of the second resistor _R'2C is connected to the first node A'C. One node A' _C is connected, and the other end is connected to ground.

Continuing from the above example, as shown in FIG. 3 and FIG. 4 , the output terminals of the first differential register corresponding to DHP0_M and DHN0_M are DHP0_SP and DHN0_SP, and the output terminals of the second differential register are DHP0_SN and DHN0_SN. The output terminals of the first differential register corresponding to DHP1_M and DHN1_M are DHP1_SP and DHN1_SP, and the output terminals of the second differential register are DHP1_SN and DHN1_SN. The output terminals of the first differential register corresponding to DHP2_M and DHN2_M are DHP2_SP and DHN2_SP, and the output terminals of the second differential register are DHP2_SN and DHN2_SN. The output terminals of the first differential register corresponding to DHP3_M and DHN3_M are DHP3_SP and DHN3_SP, and the output terminals of the second differential register are DHP3_SN and DHN3_SN.

Further, as shown in FIG. 6 , the clock input signal of the first differential register is inverted from the clock input signal of the second differential register. Specifically, following the above example, when the CHP_M is connected to the positive phase of the clock signal input terminal of the first differential register after passing through the first node (A _C ), the CHN_M is connected to the positive phase of the clock signal input terminal after passing through the first node ( When A' _C ) is connected to the reverse phase of the clock signal input end of the first differential register, then the CHP_M is connected to the clock signal input of the second differential register after passing through the first node (A _C ). terminal, and the CHN_M is connected to the positive phase of the clock signal input terminal of the second differential register after passing through the first node (A' _C ). Similarly, when the CHP_M passes through the first node (A _C ) and is connected to the inverse phase of the clock signal input end of the first differential register, the CHN_M passes through the first node (A' _C ) When it is connected to the positive phase of the clock signal input end of the first differential register, then the CHP_M is connected to the positive phase of the clock signal input end of the second differential register after passing through the first node (A _C ). , and the CHN_M is connected to the inverting phase of the clock signal input end of the second differential register after passing through the first node (A' _C ). Thus, the data rate of the DPHY receiver is reduced by half. At the same time, since the phase shift between the data signal and the clock signal output by the DPHY is a 90° phase shift, in order to maximize the sampling window of the differential register, the clock signal of the differential register can be used to directly align the data The signal is sampled.

Further, the number of data signal input terminals of the first differential register and the second differential register is greater than the number of differential data signal output terminals of the DPHY receiver, and the first differential register and the second differential register A data signal output end of the differential register is connected inversely to its corresponding data signal input end, and the data signal output end is used as the clock signal output end of the differential register, so that the clock of the DPHY receiver The frequency of the signal is divided by two to obtain a clock signal divided by two.

Specifically, as shown in FIG. 3, the positive phase output (CHP_SP) of the clock signal output terminal of the first differential register is connected to the inverting input corresponding to the clock signal output terminal, and the negative phase output (CHN_SP) of the clock signal output terminal ) is connected to the positive phase input corresponding to the clock signal output end, thereby forming a frequency division circuit of the serial clock by two. The non-inverted output (CHP_SN) of the clock signal output end of the second differential register is connected to the inverting input corresponding to the clock signal output end, and the inverting output (CHN_SN) of the clock signal output end is connected to the corresponding inverting input end of the clock signal output end. The non-inverting input of the connection, thus forming the two-frequency circuit of the serial clock.

Preferably, the frequency division circuit of the serial clock adopts a four-resistor network to realize level conversion between LVPECL and general differential signals. That is, there is a second node on the wire connected to the clock signal output end of the first differential register and the second differential register and the corresponding input end, and the second node is set close to the input end. One end of a third resistor is connected to the second node, and the other end is connected to a second pull-up voltage; one end of a fourth resistor is connected to the second node, and the other end is connected to ground. And the wiring distance between the second node and the data signal input end of the corresponding differential register is equal.

As shown in FIG. 3, for the first differential register, its clock signal output terminal CHP_SP is connected to its corresponding input terminal invertingly, and there is the second node B ₁ on the connecting wire, and the third resistor R _{31 One} end of R41 is connected to the second node B1, the other end is connected to the second pull-up voltage _V21 , _one end of the fourth resistor _R41 is connected to the second node B1, and the other end is connected to the ground . The clock signal output terminal CHN_SP is connected to the inverting phase of its corresponding input terminal, and there is the second node _B'1 on the connecting wire, and one end of the third resistor _R'31 is connected to the second node _B'1 , The other end is connected to the second pull-up voltage _V'21 , one end of the fourth resistor _R'41 is connected to the second node _B'1 , and the other end is connected to the ground.

As shown in FIG. 4, for the second differential register, its clock signal output terminal CHP_SN is connected to its corresponding input terminal invertingly, and there is the second node B ₂ on the connecting wire, and the third resistor R ₃₂ One end of R41 is connected to the _second node B2, the other end is connected to the second pull-up voltage _V22 , _one end of the fourth resistor _R41 is connected to the second node B1, and the other end is connected to the ground . The clock signal output terminal CHN_SN is connected to the inverting phase of its corresponding input terminal, and there is the _second node B'2 on the connecting wire, and one end of the third resistor _R'32 is connected to the _second node B'2, The other end is connected to the second pull-up voltage _V'22 , one end of the fourth resistor _R'42 is connected to the _second node B'2, and the other end is connected to the ground.

Each signal output terminal (including a data signal output terminal and a clock signal output terminal) of the first differential register and the second differential register is connected to an input terminal of a differential repeater. Between each signal output terminal (including the data signal output terminal and the clock signal output terminal) of the first differential register and the second differential register and the input terminal of a differential repeater, a four-resistor network is used to realize LVPECL to general-purpose Level conversion between differential signals, that is, there is a third node M on the wire connected between the output end of each data signal and the input end of the differential transponder, and one end of a fifth resistor is connected to the third node connected, the other end is connected to a third pull-up voltage, one end of a sixth resistor is connected to the third node, and the other end is connected to ground. The routing distance between the third node on each data signal output end of the two differential registers and the corresponding differential transponder is equal.

In this embodiment, the differential transponder is an SN65LVDS100 chip. In other embodiments of the present invention, the differential transponder is not limited to the SN65LVDS100 chip, as long as it has the same function.

Continuing from the above example, taking the data signal output terminals DHP0_SP and DHN0_SP of the first differential register as an example, as shown in FIG. 7, the output terminals corresponding to the DHP0_SP and DHN0_SP in the differential transponder are DHP0_SP2 and DHN0_SP2, The third node (M ₁ , M' ₁ ) is located on the wire connecting the DHPO_SP, DHN0_SP and the differential transponder. For the DHPO_SP, _one end of the fifth resistor _R51 is connected to the third node M1, the other end is connected to the third pull-up voltage _V31 , one end of the sixth resistor _R61 is connected to the _The third node M1 is connected, and the other end is connected to the ground. For the DHN0_SP, one end of the fifth resistor _R'51 is connected to the third node _M'1 , and the other end is also connected to the third pull-up voltage _V'31 , and the sixth resistor _R'61 One end of is connected to the third node _M'1 , and the other end is connected to the ground.

In this embodiment, the resistance values of the first resistor, the fourth resistor and the sixth resistor are equal, and the resistance values of the second resistor, the third resistor and the fifth resistor are equal. The values of the first pull-up voltage, the second pull-up voltage and the third pull-up voltage are equal.

The output end of the described differential transponder connected to the data signal output end of the first differential register and the second differential register is directly connected with the data input end of the FPGA, and is connected with the first differential register and the second differential register The output end of the differential transponder connected to the clock signal output end is directly connected to the clock input end of the FPGA. In order to ensure maximum receiving performance, the routing distances from the output ends of all the differential transponders to the input ends of the FPGA are equal.

So far, after the output signal of the DPHY passes through the two-way frequency division circuit provided by the embodiment of the present invention, one serial clock signal will be divided into two serial clock signals, and each serial data signal will also be divided into two serial clock signals. row data signal. The specific timing diagram is shown in Figure 8. In the figure, DHP is the serial data output by the DPHY, CHP is the serial clock output by the DPHY, and DHP_SP is the frequency-divided data output by the first differential register. , CHP_SP is the frequency-divided clock output by the first differential register, DHP_SN is the frequency-divided data output by the second differential register, and CHP_SN is the frequency-divided clock output by the second differential basis.

According to the current two ways that FPGA receives DPHY signal, if the serial clock with frequency divided by 2 is used to directly sample the serial data with frequency divided by 2, in order to maximize the sampling window of FPGA, it is necessary to use CHP_SN to sample DHP_SP inside FPGA. CHP_SP to sample DHP_SN; if the serial clock after frequency division by two passes through PLL first, and then use the clock output by PLL to drive the LVDS interface, only one serial clock with frequency division by two is needed, and then dynamically adjust the phase of PLL, The correct serial data can be sampled.

Embodiment two

In this embodiment, the frequency division circuit of the serial clock adopts a double-resistor network, that is, at the second node in the first embodiment, one end of a seventh resistor is connected to the second node, and the other One end is connected to a fourth pull-up voltage.

Specifically, for the first differential register, as shown in FIG. 8 , its clock signal output terminal CHP_SP is connected to its corresponding input terminal in reverse phase, and there is the second node B ₁ on the connecting wire, and the seventh _One end of the resistor _R71 is connected to the second node B1, and the other end is connected to the fourth pull-up voltage _V41 . Its clock signal output terminal CHN_SP is connected to the inverse phase of its corresponding input terminal, and there is the second node _B'1 on the connecting wire, and one end of the seventh resistor _R'71 is connected to the second node _B'1 , and the other end is connected to the fourth pull-up voltage _V'41 .

As for the second differential register, as shown in FIG. 9 , its clock signal output terminal CHP_SN is connected to the inverting phase of its corresponding input terminal, and there is the second node B ₂ on the connecting wire, and the seventh resistor R ₇₂ One end of is connected to the _second node B2, and the other end is connected to the fourth pull-up voltage _V42 . Its clock signal output terminal CHN_SN is connected to its corresponding input terminal in reverse phase, and there is the second node B' ₂ on the connecting wire, and one end of the seventh resistor R' ₇₂ is connected to the second node B' ₂ , and the other end is connected to the fourth pull-up voltage _V'42 .

LVPECL is also implemented in a dual resistor network between each signal output terminal (including a data signal output terminal and a clock signal output terminal) of the first differential register and the second differential register and an input terminal of a differential repeater level translation between common differential signals. That is, at the third node in the first embodiment above, one end of an eighth resistor R ₈ is connected to the third node, and the other end is connected to a fifth pull-up voltage.

Specifically, as shown in FIG. 11, taking the data signal output terminals DHP0_SP and DHN0_SP of the first differential register as an example, the output terminals corresponding to the DHP0_SP and DHN0_SP in the differential transponder are DHP0_SP2 and DHN0_SP2. There is the third node (M ₁ , M' ₁ ) on the wire connecting the DHPO_SP, DHN0_SP and the differential transponder. For the DHPO_SP, one end of the eighth resistor R ₈₁ is connected to the third node M ₁ , and the other end is connected to the fifth pull-up voltage V ₅₁ . For the DHN0_SP, one end of the eighth resistor _R'81 is connected to the third node _M'1 , and the other end is also connected to the fifth pull-up voltage _V'51 .

The resistance values of the seventh resistor and the eighth resistor are equal, and the values of the fourth pull-up voltage and the fifth pull-up voltage are equal.

Further, the fourth pull-up voltage=the third pull-up voltage-2.0V. The resistance value of the seventh resistor is equivalent to the parallel connection resistance value of the third resistor and the fourth resistor.

In Embodiment 1 and Embodiment 2 of the present invention, the value of the third pull-up voltage (V3) is 3.3V, that is to say, the values of the fourth pull-up voltage and the fifth pull-up voltage are 1.3V .

Since the first differential register and the second differential register have an open-emitter output structure, there must be a current return path, therefore, the power supply that provides the fourth pull-up voltage and the fifth pull-up voltage must be able to sink current . That is, the power supply needs to meet two conditions, it can absorb current and ensure that the output voltage meets the requirement of the pull-up voltage in the dual-resistor network. In this embodiment, the output voltage must be 1.3V.

Further, in this embodiment, the power supply selects the LT3015 power supply chip, and uses 3.3V as the ground of the LT3015 power supply chip, thereby avoiding the requirement of using a negative voltage as the input voltage of the LT3015 power supply chip. Of course, in other embodiments of the present utility model, the power supply can also choose other power supply chips, as long as they meet the above two conditions, no more details are given here.

Other parts are the same as those in Embodiment 1, and will not be repeated here.

In summary, in the frequency division circuit for receiving DPHY serial signals provided by the embodiment of the present invention, a DPHY receiver, two differential registers and at least four differential transponders are used to perform frequency division processing on the output signal of DPHY , including the data output signal and the clock output signal of the DPHY are divided by two, thereby increasing the rate at which the FPGA receives DPHY serial data, which can meet the requirements of various verification platforms for the speed of the DPHY, and realize Simple, safe and reliable.

The above are only preferred embodiments of the utility model, and do not limit the utility model in any way. Any person skilled in the technical field, without departing from the scope of the technical solution of the utility model, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the utility model, all of which are within the scope of the utility model. The content of the technical solution still belongs to the protection scope of the present utility model.

Claims (10)

1. A divide-by-two circuit for receiving DPHY serial signals, characterized in that it comprises a DPHY receiver, two differential registers and at least four differential transponders; The input terminal of the DPHY receiver receives the serial output signal of the DPHY and separates the differential data signal, and the differential data signal output terminal of the DPHY receiver outputs the differential data signal and is respectively compared with the data of the two differential registers. The signal input terminal is connected, and the clock signal output terminal of the DPHY receiver is respectively connected to the clock signal input terminals of the two differential registers and makes the phases of the clock signals of the two differential registers opposite; One of the multiple data signal output terminals of each differential register is connected inversely to a corresponding data signal input terminal, and the data signal output terminal is used as the clock signal output terminal of the differential register, and at the same time The data signal output terminal is connected to the data signal input terminal of one of the differential transponders, and the other data signal output terminals of each differential register are respectively connected to the data signal input terminals of other differential transponders. 2. The divide-by-two circuit receiving the DPHY serial signal according to claim 1, characterized in that, at the differential data signal output end of the DPHY receiver and the connecting wires of the data signal input ends of the two differential registers There is a first node on, and the first node is arranged close to the differential register. 3. The divide-by-two circuit receiving the DPHY serial signal according to claim 2, further comprising a first resistor and a second resistor; one end of the first resistor is connected to the first node , the other end of which is connected to a first pull-up voltage; one end of the second resistor is connected to the first node, and the other end is connected to the ground. 4. The divide-by-two circuit receiving the DPHY serial signal according to claim 1, characterized in that, a data signal output terminal in the two differential registers is connected in reverse with its corresponding data signal input terminal There is a second node on it, and the second node is set close to the data signal input end of the differential register. 5. The divide-by-two circuit receiving the DPHY serial signal according to claim 4, further comprising a third resistor and a fourth resistor; one end of the third resistor is connected to the second node , the other end of which is connected to a second pull-up voltage; one end of the fourth resistor is connected to the second node, and the other end is connected to the ground. 6. The divide-by-two circuit for receiving DPHY serial signals according to claim 4, further comprising a seventh resistor, one end of the seventh resistor is connected to the second node, and the other end is connected to a Fourth pull-up voltage connection. 7. The divide-by-two circuit for receiving DPHY serial signals according to claim 6, wherein the fourth pull-up voltage is provided by a power supply capable of sinking current. 8. The divide-by-two circuit receiving the DPHY serial signal according to claim 1, wherein the data signal output terminals of the two differential registers are connected to the data signal input terminals of the at least four differential transponders There is a third node on the wire, and the third node is arranged close to the differential transponder. 9. The divide-by-two circuit receiving the DPHY serial signal according to claim 8, further comprising a fifth resistor and a sixth resistor; one end of the fifth resistor is connected to the third node , the other end of which is connected to a third pull-up voltage; one end of the sixth resistor is connected to the third node, and the other end is connected to the ground. 10. The divide-by-two circuit for receiving DPHY serial signals according to claim 8, further comprising an eighth resistor, one end of the eighth resistor is connected to the third node, and the other end is connected to a The fifth pull-up voltage is connected, and the fifth pull-up voltage is provided by a power source capable of sinking current.