CN205049638U - Faint signal detection circuit of high frequency - Google Patents
Faint signal detection circuit of high frequency Download PDFInfo
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- CN205049638U CN205049638U CN201520755386.7U CN201520755386U CN205049638U CN 205049638 U CN205049638 U CN 205049638U CN 201520755386 U CN201520755386 U CN 201520755386U CN 205049638 U CN205049638 U CN 205049638U
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Abstract
本实用新型公开了一种高频微弱信号检测电路，包括积分电路N1、反相比例电路N2、反相求和电路N3、乘法电路N4、反相比例电路N5和积分电路N6；积分电路N1与周期策动力、噪声和待测信号相连，信号经积分电路N1处理后送给反相比例电路N2处理，处理后信号一路输送给积分电路N6进行积分处理，一路输送给反相求和电路N3处理；经积分电路N6处理的信号输送给反相比例电路N5处理，处理后将信号一路送给乘法电路N4处理，一路送给积分电路N1处理；反相比例电路N2和乘法电路N4处理的信号送给反相求和电路N3处理；反相求和电路N3处理后的信号送回积分电路N1。通过观察检测电路输出的相图是否发生相变，来判断待测信号中是否存在高频微弱信号。
The utility model discloses a high-frequency weak signal detection circuit, which comprises an integral circuit N1, an inverse proportional circuit N2, an inverse summation circuit N3, a multiplication circuit N4, an inverse proportional circuit N5 and an integral circuit N6; Periodic driving force, noise and the signal to be measured are connected, the signal is processed by the integration circuit N1 and sent to the inverse proportional circuit N2 for processing, the processed signal is sent to the integration circuit N6 for integral processing, and the signal is sent to the inverting summation circuit N3 for processing ; The signal processed by the integral circuit N6 is sent to the inverse proportional circuit N5 for processing, and after processing, the signal is sent to the multiplication circuit N4 for processing, and the signal is sent to the integral circuit N1 for processing; the signal processed by the inverse proportional circuit N2 and the multiplication circuit N4 is sent to It is processed by the inverting summing circuit N3; the signal processed by the inverting summing circuit N3 is sent back to the integrating circuit N1. By observing whether there is a phase change in the phase diagram output by the detection circuit, it is judged whether there is a high-frequency weak signal in the signal to be tested.
Description
Technical field
The utility model relates to a kind of high-frequency signal testing circuit, particularly relates to a kind of testing circuit of the high frequency weak signal based on chaos technology.
Background technology
Utilize the critical phase transformation of chaotic oscillator to detect the study hotspot that feeble signal is current Detection of Weak Signals field, have a lot for the chaotic oscillator detecting feeble signal at present, wherein the research of Duffing oscillator is comparatively ripe, the method detecting feeble signal based on Duffing oscillator is in fact suppress the process of chaos, namely utilize chaos system to the perturbation of parameter and susceptibility thereof, make Periodic Solutions generation essential change to carry out the detection of weak periodic signal.Holmes type Duffing equation by classics:
In formula (1), k is damping ratio;-x (t)+x
3t () is nonlinear restoring force; Acos ω t is cycle driving force, and wherein a is cycle driving force amplitude, and ω is driving force angular frequency.Being write (1) formula as state equation is:
Very responsive to feeble signal under certain condition based on Duffing oscillator, have immunity to noise, therefore Duffing oscillator very has potentiality in Detection of Weak Signals field simultaneously.
In signal detection process, first by Duffing system call interception to chaos critical conditions, in Duffing system, then add measured signal as cycle hormetic perturbation; If when only having very noisy interference to there is no specific period signal in measured signal, system phasor can not change, and is still in chaos critical conditions; If when having specific period signal in measured signal, even if amplitude is very little, system phasor also can be made to jump to great scale period state from chaos state.Therefore, whether jump to great scale period state from chaos state according to phase path and can judge whether there is specific period signal measured signal.Above-mentioned equation, when the feeble signal detected, be generally low frequency signal, but in conventional feeble signal, most of signal is high frequency band signal, and such scheme is just inapplicable when detecting high-frequency signal.
Utility model content
In order to solve the deficiency that prior art exists, the utility model provides a kind of testing circuit that can be used in detecting high frequency weak signal.
To achieve these goals, the technical solution adopted in the utility model is: a kind of High-frequency weak signal detection circuit, comprises integrating circuit N1, anti-phase ratio circuit N2, anti-phase summing circuit N3, mlultiplying circuit N4, anti-phase ratio circuit N5 and integrating circuit N6;
Integrating circuit N1 is connected with measured signal with cycle driving force, noise, and carries out Integral Processing to it; Signal after integrating circuit N1 process flows to anti-phase ratio circuit N2 and carries out certain proportion amplification and anti-phase process; Signal one tunnel after anti-phase ratio circuit N2 process flows to integrating circuit N6 and carries out quadratic integral process, and a road flows to anti-phase summing circuit N3 and carries out anti-phase summation process; Signal after integrating circuit N6 process flows to anti-phase ratio circuit N5 and carries out certain proportion amplification and anti-phase process; Signal one tunnel after anti-phase ratio circuit N5 process flows to mlultiplying circuit N4 and carries out multiplication process, and a road flows to integrating circuit N1 and carries out Integral Processing; Signal after mlultiplying circuit N4 process flows to anti-phase summing circuit N3 to carry out oppositely and summation process; Signal after anti-phase summing circuit N3 process is transmitted back to integrating circuit N1.
Integrating circuit N1 comprises 6 resistance R1, R2, R3, R4, R5, R6, an electric capacity C1 and operational amplifier U2; Resistance R1, R2, R3, R4, R5 are connected with the inverting input of operational amplifier U2 respectively; One end ground connection of resistance R6, the other end is connected with the in-phase input end of operational amplifier U2; The inverting input of the one termination operational amplifier U2 of described electric capacity C1, the other end is connected with the output terminal of operational amplifier U2; The output terminal of described operational amplifier U2 is connected with anti-phase ratio circuit N2.
Integrating circuit N1 also comprises a feedback resistance RF1; Described feedback resistance RF1 is connected with output terminal with the inverting input of operational amplifier U2 respectively.
Anti-phase ratio circuit N2 comprises three resistance R7, R8, R9 and an operational amplifier U3; Described resistance R7 one end is connected with the output terminal of operational amplifier U2, and the other end is connected with the inverting input of operational amplifier U3; Described resistance R8 one end is connected with the inverting input of operational amplifier U3, and the other end is connected with the output terminal of operational amplifier U3; One end ground connection of described resistance R9, the other end is connected with the in-phase input end of operational amplifier U3; The output terminal of described operational amplifier U3 is connected with reverse summing circuit N3 with integrating circuit N6 respectively.
Anti-phase summing circuit N3 comprises four resistance R10, R11, R12, R13 and an operational amplifier U1; Described resistance R10 one end is connected with the output terminal of operational amplifier U3, and one end is connected with the inverting input of operational amplifier U1; Described resistance R11 one end is connected with the inverting input of operational amplifier U1, and the other end is connected with mlultiplying circuit N4; Described resistance R12 one end is connected with the inverting input of operational amplifier U1, and the other end is connected with the output terminal of operational amplifier U1; One end ground connection of described resistance R13, the other end is connected with the in-phase input end of operational amplifier U1.
Integrating circuit N6 comprises two resistance R14, R15, an electric capacity C2 and operational amplifier U4; One end of described resistance R14 is connected with the output terminal of operational amplifier U3, and the other end is connected with the inverting input of operational amplifier U4; Described resistance R15 one end ground connection, the other end is connected with the in-phase input end of operational amplifier U4; The inverting input of the one termination operational amplifier U4 of described electric capacity C2, the other end is connected with the output terminal of operational amplifier U4; The output terminal of described operational amplifier U4 is connected with anti-phase ratio circuit N5.
Integrating circuit N6 also comprises a feedback resistance RF2; Described feedback resistance RF2 is connected with output terminal with the inverting input of operational amplifier U4 respectively.
Anti-phase ratio circuit N5 comprises three resistance R16, R17, R18 and an operational amplifier U5; Described resistance R16 one end is connected with the output terminal of operational amplifier U4, and the other end is connected with the inverting input of operational amplifier U5; Described resistance R17 one end is connected with the inverting input of operational amplifier U5, and the other end is connected with the output terminal of operational amplifier U5; Described resistance R18 one end ground connection, the other end is connected with the in-phase input end of operational amplifier U5; The output terminal of described operational amplifier U5 is connected with the resistance R1 of integrating circuit N1 with mlultiplying circuit N4 respectively.
Described mlultiplying circuit N4 comprises two multiplier A1 and A2; Described A1 and A2 is interconnected; Be connected with an input end of A2 with the output terminal of operational amplifier U5 respectively, the output terminal of A1 is connected with another input end of A2; The output terminal of described A2 is connected with the resistance R11 of anti-phase summing circuit N3.
The theoretical foundation that High-frequency weak signal detection circuit can realize is: first carried out deformation process to the Holmes type Duffing equation of classics.
First be out of shape by equation (2), make t=ω τ, obtaining the Duffing equation after being out of shape is:
As can be seen from equation (3), the Duffing system of optional frequency ω can realize, for optional frequency Detection of Weak Signals provides theoretical foundation.
In order to (3) formula is applied to reality, further (3) formula is being carried out Integral Processing, when starting condition is x (0)=0, y (0)=0, obtaining equation (4) is:
It can thus be appreciated that equation (4) can be applied to high-frequency signal and detect, its frequency can set according to the size of ω in equation (4).
After adopting the technical solution of the utility model, detection signal frequencies omega can be set by change resistance and capacitance parameter size in circuit.After setting cycle driving force signal frequency, Circuit tuning range value makes circuit reach critical chaotic state, next directly will join in integrating circuit N1 containing noisy measured signal, homogenous frequency signal as what add, the output phasor of testing circuit can jump to great scale period state by critical chaotic state, signal as added is signal or the noise of different frequency, the phasor that circuit exports is still critical chaotic state, this shows, this circuit can realize High-frequency weak signal detection.The utility model circuit structure is simple, measuring accuracy is high, cost of manufacture is lower.
Accompanying drawing explanation
Fig. 1 is the schematic block circuit diagram of High-frequency weak signal detection circuit.
Fig. 2 is the circuit theory diagrams of High-frequency weak signal detection circuit.
Fig. 3 is the sequential chart that High-frequency weak signal detection circuit exports when critical chaotic state.
Fig. 4 is the phasor that High-frequency weak signal detection circuit exports when critical chaotic state.
Fig. 5 is the sequential chart that High-frequency weak signal detection circuit exports when great scale period state.
Fig. 6 is the phasor that High-frequency weak signal detection circuit exports when great scale period state.
Embodiment
Below in conjunction with accompanying drawing, the preferred mode of the utility model is further elaborated:
A High-frequency weak signal detection circuit as shown in Figure 1, comprises integrating circuit N1, anti-phase ratio circuit N2, anti-phase summing circuit N3, mlultiplying circuit N4, anti-phase ratio circuit N5 and integrating circuit N6.
As shown in Figure 2, embodiment with detection signal frequency for ω=10
6rad/s is example, carrys out the parameter of initialization circuit.
Integrating circuit N1 comprises 6 resistance R1, R2, R3, R4, R5, R6, an electric capacity C1 and operational amplifier U2; The resistance of resistance R1 to resistance R5 is 1k Ω, and resistance R6 is 10k Ω, and electric capacity C1 is 100nF, and that operational amplifier U2 adopts is 3554AM.Described resistance R1, R2, R3, R4, R5 are connected with the inverting input of operational amplifier respectively; One end ground connection of resistance R6, the other end is connected with the in-phase input end of operational amplifier U2; The inverting input of the one termination operational amplifier U2 of described electric capacity C1, the other end is connected with the output terminal of operational amplifier U2; The output terminal of described operational amplifier U2 is connected with anti-phase ratio circuit N2.In order to reduce the DC shift of integrating circuit N1 output terminal, the low-frequency voltage gain of limiting circuit, a resistance RF1 in parallel on the feedback capacity C1 of described integrating circuit N1, the resistance of resistance RF1 is 10k Ω, introduces the saturated or cut off phenomenon that resistance RF1 can also prevent integrator drift from causing in described integrating circuit N1.
Anti-phase ratio circuit N2 comprises three resistance R7, R8, R9 and an operational amplifier U3; The resistance of the resistance of resistance R7 to be the resistance of 1k Ω, R8 be 100k Ω, R9 is 10k Ω, and that operational amplifier U3 adopts is 3554AM.Described resistance R7 one end is connected with the output terminal of operational amplifier U2, and the other end is connected with the inverting input of operational amplifier U3; Described resistance R8 one end is connected with the inverting input of operational amplifier U3, and the other end is connected with the output terminal of operational amplifier U3; One end ground connection of described resistance R9, the other end is connected with the in-phase input end of operational amplifier U3; The output terminal of described operational amplifier U3 is connected with reverse summing circuit N3 with integrating circuit N6 respectively.
Anti-phase summing circuit N3 comprises four resistance R10, R11, R12, R13 and an operational amplifier U1; The resistance of R10 is 20k Ω, and the resistance of R11, R12, R13 is 10k Ω, and that operational amplifier U1 adopts is 3554AM.Described resistance R10 one end is connected with the output terminal of operational amplifier U3, and one end is connected with the inverting input of operational amplifier U1; Described resistance R11 one end is connected with the inverting input of operational amplifier U1, and the other end is connected with mlultiplying circuit N4; Described resistance R12 one end is connected with the inverting input of operational amplifier U1, and the other end is connected with the output terminal of operational amplifier U1; One end ground connection of described resistance R13, the other end is connected with the in-phase input end of operational amplifier U1.
Integrating circuit N6 comprises two resistance R14, R15, an electric capacity C2 and operational amplifier U4; The resistance of resistance R14, R15 is 10k Ω, and electric capacity C2 is 1nF, and that operational amplifier U4 adopts is 3554AM.One end of described resistance R14 is connected with the output terminal of operational amplifier U3, and the other end is connected with the inverting input of operational amplifier U4; Described resistance R15 one end ground connection, the other end is connected with the in-phase input end of operational amplifier U4; The inverting input of the one termination operational amplifier U4 of described electric capacity C2, the other end is connected with the output terminal of operational amplifier U4; The output terminal of described operational amplifier U4 is connected with anti-phase ratio circuit N5.The same with described integrating circuit N1, in order to reduce the DC shift of integrating circuit N6 output terminal, the low-frequency voltage gain of limiting circuit, on the feedback capacity C2 of described integrating circuit N6, the resistance of a resistance RF2, resistance RF2 in parallel is 10k Ω; Saturated or the cut off phenomenon that resistance RF2 also can prevent integrator drift from causing is introduced in described integrating circuit N6.
Anti-phase ratio circuit N5 comprises three resistance R16, R17, R18 and an operational amplifier U5; The resistance of resistance R16, R18 is 10k Ω, and the resistance of resistance R17 is 100k Ω, and that operational amplifier U3 adopts is 3554AM.Described resistance R16 one end is connected with the output terminal of operational amplifier U4, and the other end is connected with the inverting input of operational amplifier U5; Described resistance R17 one end is connected with the inverting input of operational amplifier U5, and the other end is connected with the output terminal of operational amplifier U5; Described resistance R18 one end ground connection, the other end is connected with the in-phase input end of operational amplifier U5; The output terminal of described operational amplifier U5 is connected with the resistance R1 of integrating circuit N1 with mlultiplying circuit N4 respectively.
Mlultiplying circuit N4 comprises two multiplier A1 and A2; That multiplier A1 and A2 adopts is AD633JN.Described A1 and A2 is interconnected; Be connected with an input end of A2 with the output terminal of operational amplifier U5 respectively, the output terminal of A1 is connected with another input end of A2; The output terminal of described A2 is connected with the resistance R11 of anti-phase summing circuit N3.
The course of work below by circuit illustrates, after power on circuitry work, first arranging cycle driving force signal frequency is ω=10
6rad/s, debugging driving force signal amplitude effective value is 0.41V, the phasor that circuit is exported from A and B end is critical chaotic state (as shown in Figure 4), the sequential chart now exported from A is chaotic time series figure (as shown in Figure 3), is next directly joined in integrating circuit N1 by the measured signal of Noise.If add with frequently, effective value is when being the sinusoidal wave measured signal of 0.02V, circuit is great scale period state (as shown in Figure 5) from the phasor transition that A and B exports, from the similar periodic signal of sequential chart (as shown in Figure 6) of A output.If the signal added is measured signal or the noise of different frequency, the phasor that circuit exports from A and B end be still critical chaotic state (as shown in Figure 4), and namely this circuit has immunocompetence to difference and the measured signal of self driving frequency and noise.Can be found out by above-mentioned citing, this testing circuit can realize the detection of high frequency weak signal.
If detected other radio-frequency signals with High-frequency weak signal detection circuit of the present utility model, the testing circuit parameter in the utility model is needed to make simple change, the parameter of regulating resistance R1, R7, R8, R14, R16, R17 and electric capacity C1, C2, meets expression formula in circuit
.
Claims (9)
1. a High-frequency weak signal detection circuit, is characterized in that: comprise integrating circuit N1, anti-phase ratio circuit N2, anti-phase summing circuit N3, mlultiplying circuit N4, anti-phase ratio circuit N5 and integrating circuit N6; Described integrating circuit N1 is connected with measured signal with cycle driving force, noise, and carries out Integral Processing to it; Signal after integrating circuit N1 process flows to anti-phase ratio circuit N2 and carries out certain proportion amplification and anti-phase process; Signal one tunnel after anti-phase ratio circuit N2 process flows to integrating circuit N6 and carries out quadratic integral process, and a road flows to anti-phase summing circuit N3 and carries out anti-phase summation process; Signal after integrating circuit N6 process flows to anti-phase ratio circuit N5 and carries out certain proportion amplification and anti-phase process; Signal one tunnel after anti-phase ratio circuit N5 process flows to mlultiplying circuit N4 and carries out multiplication process, and a road flows to integrating circuit N1 and carries out Integral Processing; Signal after mlultiplying circuit N4 process flows to anti-phase summing circuit N3 to carry out oppositely and summation process; Signal after anti-phase summing circuit N3 process is transmitted back to integrating circuit N1.
2. High-frequency weak signal detection circuit according to claim 1, is characterized in that: described integrating circuit N1 comprises 6 resistance R1, R2, R3, R4, R5, R6, an electric capacity C1 and operational amplifier U2; Resistance R1, R2, R3, R4, R5 are connected with the inverting input of operational amplifier U2 respectively; One end ground connection of resistance R6, the other end is connected with the in-phase input end of operational amplifier U2; The inverting input of the one termination operational amplifier U2 of described electric capacity C1, the other end is connected with the output terminal of operational amplifier U2; The output terminal of described operational amplifier U2 is connected with anti-phase ratio circuit N2.
3. High-frequency weak signal detection circuit according to claim 2, is characterized in that: described integrating circuit N1 also comprises a feedback resistance RF1; Described feedback resistance RF1 is connected with output terminal with the inverting input of operational amplifier U2 respectively.
4. High-frequency weak signal detection circuit according to claim 3, is characterized in that: anti-phase ratio circuit N2 comprises three resistance R7, R8, R9 and an operational amplifier U3; Described resistance R7 one end is connected with the output terminal of operational amplifier U2, and the other end is connected with the inverting input of operational amplifier U3; Described resistance R8 one end is connected with the inverting input of operational amplifier U3, and the other end is connected with the output terminal of operational amplifier U3; One end ground connection of described resistance R9, the other end is connected with the in-phase input end of operational amplifier U3; The output terminal of described operational amplifier U3 is connected with reverse summing circuit N3 with integrating circuit N6 respectively.
5. High-frequency weak signal detection circuit according to claim 4, is characterized in that: anti-phase summing circuit N3 comprises four resistance R10, R11, R12, R13 and an operational amplifier U1; Described resistance R10 one end is connected with the output terminal of operational amplifier U3, and one end is connected with the inverting input of operational amplifier U1; Described resistance R11 one end is connected with the inverting input of operational amplifier U1, and the other end is connected with mlultiplying circuit N4; Described resistance R12 one end is connected with the inverting input of operational amplifier U1, and the other end is connected with the output terminal of operational amplifier U1; One end ground connection of described resistance R13, the other end is connected with the in-phase input end of operational amplifier U1.
6. High-frequency weak signal detection circuit according to claim 5, is characterized in that: integrating circuit N6 comprises two resistance R14, R15, an electric capacity C2 and operational amplifier U4; One end of described resistance R14 is connected with the output terminal of operational amplifier U3, and the other end is connected with the inverting input of operational amplifier U4; Described resistance R15 one end ground connection, the other end is connected with the in-phase input end of operational amplifier U4; The inverting input of the one termination operational amplifier U4 of described electric capacity C2, the other end is connected with the output terminal of operational amplifier U4; The output terminal of described operational amplifier U4 is connected with anti-phase ratio circuit N5.
7. High-frequency weak signal detection circuit according to claim 6, is characterized in that: described integrating circuit N6 also comprises a feedback resistance RF2; Described feedback resistance RF2 is connected with output terminal with the inverting input of operational amplifier U4 respectively.
8. High-frequency weak signal detection circuit according to claim 7, is characterized in that: described anti-phase ratio circuit N5 comprises three resistance R16, R17, R18 and an operational amplifier U5; Described resistance R16 one end is connected with the output terminal of operational amplifier U4, and the other end is connected with the inverting input of operational amplifier U5; Described resistance R17 one end is connected with the inverting input of operational amplifier U5, and the other end is connected with the output terminal of operational amplifier U5; Described resistance R18 one end ground connection, the other end is connected with the in-phase input end of operational amplifier U5; The output terminal of described operational amplifier U5 is connected with the resistance R1 of integrating circuit N1 with mlultiplying circuit N4 respectively.
9. High-frequency weak signal detection circuit according to claim 8, is characterized in that: described mlultiplying circuit N4 comprises two multiplier A1 and A2; After two input ends of described A1 are connected, be connected with an input end of A2 with the output terminal of operational amplifier U5 respectively, the output terminal of A1 is connected with another input end of A2; The output terminal of described A2 is connected with the resistance R11 of anti-phase summing circuit N3.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520755386.7U CN205049638U (en) | 2015-09-25 | 2015-09-25 | Faint signal detection circuit of high frequency |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520755386.7U CN205049638U (en) | 2015-09-25 | 2015-09-25 | Faint signal detection circuit of high frequency |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105827393A (en) * | 2016-05-27 | 2016-08-03 | 马英杰 | Holmes-Duffing chaos system and FPGA digital circuit |
| CN113608021A (en) * | 2021-07-23 | 2021-11-05 | 华中科技大学 | Chaotic oscillator circuit and weak signal detection system based on chaos theory |
-
2015
- 2015-09-25 CN CN201520755386.7U patent/CN205049638U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105827393A (en) * | 2016-05-27 | 2016-08-03 | 马英杰 | Holmes-Duffing chaos system and FPGA digital circuit |
| CN113608021A (en) * | 2021-07-23 | 2021-11-05 | 华中科技大学 | Chaotic oscillator circuit and weak signal detection system based on chaos theory |
| CN113608021B (en) * | 2021-07-23 | 2022-05-20 | 华中科技大学 | A Chaos Oscillator Circuit and Weak Signal Detection System Based on Chaos Theory |
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