CN205038592U - Electric system is economized to PCIE equipment based on SMBUS bus agreement - Google Patents

Abstract

The utility model discloses a PCIE device power-saving system based on the SMBUS bus protocol. The system includes a server platform, which is respectively connected with PCIE equipment, an SMBUS buffer chip for protecting static electricity and providing voltage conversion, and used for controlling the server platform. The power-on CPLD chip, wherein, the SMBUS chip is connected with the CPLD chip, and the periphery of the CPLD chip is connected with the key. When the server does not need to use one or more PCIE devices in a certain working state, the power supply of the PCIE slot of the device is terminated through the CPLD, so as to turn off the device, achieve the purpose of saving power consumption, indirectly reduce the temperature, and have a simple structure , The advantages of low cost.

Description

A PCIE device power saving system based on SMBUS bus protocol

technical field

The utility model relates to a power saving system, in particular to a PCIE device power saving system based on the SMBUS bus protocol.

Background technique

With the continuous improvement of domestic CPU functions, its power consumption has also increased accordingly, but domestic CPU itself does not have the function of automatic frequency reduction, resulting in waste of power consumption in certain working conditions, resulting in unnecessary heat, long-term Long-term high-temperature work will also reduce the service life of components. Moreover, high-end server products usually need to run for a long time without downtime, and the long-time work will inevitably generate a lot of heat, and the increase in heat will affect the operation of the motherboard and affect the stability of the server.

Contents of the invention

The technical task of the utility model is to provide a kind of PCIE equipment power-saving system based on the SMBUS bus protocol to solve the above technical problems.

The technical solution adopted by the utility model to solve its technical problems is: the system includes a server platform, which is respectively connected with PCIE equipment (network card, graphics card, etc.), SMBUS buffer chips for protecting static electricity and providing voltage conversion, and for controlling A CPLD chip powered on the server platform, wherein the SMBUS buffer chip is connected to the CPLD chip, and the periphery of the CPLD chip is connected to the key.

The processor of the server platform is Godson 3B, and the architecture of the server platform is ATCA architecture.

The model of the CPLD chip is an EPM570 chip.

The model of the SMBUS buffer chip is TCA9406 chip.

The beneficial effects of the utility model are: when the server does not need to use one or more PCIE devices in a certain working state, the power supply of the PCIE slot of the device is terminated through the CPLD, so as to close the device and achieve the purpose of saving power consumption. Lowering the temperature indirectly has the advantages of simple structure and low cost.

Description of drawings

Below in conjunction with accompanying drawing, the utility model is further described.

Accompanying drawing 1 is a kind of structural block diagram of the PCIE equipment power saving system based on SMBUS bus protocol.

detailed description

Below in conjunction with accompanying drawing and specific embodiment the utility model is further described.

Example 1

As shown in accompanying drawing 1, a kind of PCIE equipment power-saving system based on SMBUS bus protocol of the present utility model, this system comprises the server platform that architecture is ATCA, and the processor of server platform is Godson 3B, and server platform is respectively connected with PCIE equipment (Network card) TCA9406 chip for static protection and voltage conversion, and EPM570 chip for controlling server platform, wherein the TCA9406 chip is connected to the EPM570 chip, and the periphery of the EPM570 chip is connected to the key.

When the system is working, it controls the power-on of relevant PCIE devices according to the real-time information captured by the EPM570 chip through the TCA9406 chip. Here, the PCIE device is a network card. If only one network card I is needed for the server’s tasks within a certain period of time, and the other network card II is idle, then the EPM570 chip will turn off the power enable of this network card after receiving the information. The power consumption of the network card II can be saved; at the same time, if you need to reuse the network card II, send a pulse to the EPM570 chip through the peripheral buttons of the chassis, and the EPM570 chip will power on the PCIE slot again after receiving the pulse to wake up the network card II .

Example 2

As shown in accompanying drawing 1, a kind of PCIE equipment power-saving system based on SMBUS bus protocol of the present utility model, this system comprises the server platform that architecture is ATCA, and the processor of server platform is Godson 3B, and server platform is respectively connected with PCIE equipment (Graphic card) TCA9406 chip for static protection and voltage conversion, and EPM570 chip for controlling the server platform, wherein the TCA9406 chip is connected to the EPM570 chip, and the periphery of the EPM570 chip is connected to the key.

When the system is working, it controls the power-on of relevant PCIE devices according to the real-time information captured by the EPM570 chip through the TCA9406 chip. Here, the PCIE device is a graphics card. If only one graphics card Ⅰ is needed for the server’s tasks within a certain period of time, and the other graphics card Ⅱ is idle, then the EPM570 chip will turn off the power of this graphics card after getting the information. The power consumption of the graphics card II can be saved; at the same time, if you need to reuse the graphics card II, send a pulse to the EPM570 chip through the peripheral buttons of the chassis, and the EPM570 chip will power on the PCIE slot again after receiving the pulse to wake up the graphics card II .

Example 3

As shown in accompanying drawing 1, a kind of PCIE equipment power-saving system based on SMBUS bus protocol of the present utility model, this system comprises the server platform that architecture is ATCA, and the processor of server platform is Godson 3B, and server platform is respectively connected with PCIE equipment (Graphic card) TCA9406 chip for static protection and voltage conversion, and EPM570 chip for controlling the server platform, wherein the TCA9406 chip is connected to the EPM570 chip, and the periphery of the EPM570 chip is connected to the key.

When the system is working, it controls the power-on of relevant PCIE devices according to the real-time information captured by the EPM570 chip through the TCA9406 chip. Here the PCIE device is a sound card. If only one sound card Ⅰ is needed for the server’s tasks within a certain period of time, and the other sound card Ⅱ is idle, then the EPM570 chip will turn off the power of the sound card after receiving the information. The power consumption of the sound card II can be saved; at the same time, if the sound card II needs to be reused, send a pulse to the EPM570 chip through the peripheral buttons of the chassis, and the EPM570 chip will power on the PCIE slot again after receiving the pulse to wake up the sound card II .

Among them, PCIE (PCI-Express) is the latest bus and interface standard. It belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices allocate exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management and error reporting. , end-to-end reliable transmission, hot swapping and quality of service functions.

CPLD (Complex Programmable Logic Device) complex programmable logic device is a digital integrated circuit in which users can construct logic functions according to their own needs.

SMBUS (System Management Bus, System Management Bus), applied to low-speed communication in mobile PC and desktop PC systems, through a cheap and powerful bus (composed of two lines), to control the devices on the motherboard and collect corresponding information .

Through the above specific implementation methods, those skilled in the art can easily realize the utility model. However, it should be understood that the present utility model is not limited to the specific implementation manners described above. On the basis of the disclosed embodiments, those skilled in the art can arbitrarily combine different technical features to achieve different technical solutions.

Claims (4)

1. the PCIE device electricity-saving system based on SMBUS bus protocol, it is characterized in that: this system comprises server platform, server platform is connected to PCIE device, for the CPLD chip protecting electrostatic and provide the SMBUS buffer chip of voltage transitions and power on for Control Server platform, wherein, described SMBUS buffer chip is connected with CPLD chip, and the periphery of CPLD chip is connected with button.

2. a kind of PCIE device electricity-saving system based on SMBUS bus protocol according to claim 1, it is characterized in that: the processor of described server platform is Godson 3B, the framework of server platform is ATCA framework.

3. a kind of PCIE device electricity-saving system based on SMBUS bus protocol according to claim 1, is characterized in that: the model of described CPLD chip is EPM570 chip.

4. a kind of PCIE device electricity-saving system based on SMBUS bus protocol according to claim 1, is characterized in that: the model of described SMBUS buffer chip is TCA9406 chip.