CN204928758U - A Gain Boosted Operational Transconductance Amplifier - Google Patents

Abstract

The utility model discloses an operation transconductance amplifier that gain promoted, the constant current source source concatenates differential input in proper order by offseting, the load current mirror, cascode output stage and adjustable supplementary differential pair constitute, wherein differential input is by 4 PMOS pipe M1a, M2a, M1b and M2b constitute, the load current mirror is by 6 NMOS pipe M3, M4, M5a, M6a, M5b and M6b constitute, the cascode output stage comprises to M12 6 MOS pipe M7, adjustable supplementary differential pair is by M13, M14 and M15 constitute. The intrinsic contradictions between gain in the circuit, bandwidth, the consumption etc. Are thoroughly solved to adjustable supplementary differential pair that the reuse of electric current and output stage increase, the utility model discloses a little less than receiving output voltage to influence very, can not introduce extra limit, simulation result shows the same quiescent power dissipation, the utility model discloses gain, bandwidth all realize the multiplication, still have can finely tune, the characteristics of high accuracy, be applicable to systems such as communication, electronic measurement and automatic control.

Description

A Gain Boosted Operational Transconductance Amplifier

technical field

The utility model relates to an operational amplifier, in particular to an operational transconductance amplifier with increased gain.

Background technique

Operational amplifiers have been widely used in analog circuits such as power supplies, analog-to-digital converters, and filters. With the decrease of power supply voltage and the further reduction of process size, the channel length of transistors continues to decrease, resulting in the decrease of intrinsic gain of transistors. Under such conditions, designing high-gain op amps faces great challenges. In the prior art, two or three stages of cascading are used. In this manner, each cascading brings high gain and at the same time introduces a low-frequency pole, resulting in negative phase shift and degraded phase margin. In order to maintain the stability of the system, the principle of Miller compensation is generally used. This kind of pole separation compensation will seriously degrade the bandwidth performance of the op amp. Boosting the output impedance with bootstrap gain is another way to increase the gain. Although it does not limit the bandwidth performance of the op amp, it consumes more power.

In 2007, R. Assaad published an article entitled "Enhancing general performance off folded cascode amplifier by recycling current" (RFC operational amplifier) in ELECTRONICSLETTERS, which is a multiplexed folded cascode operational amplifier with low power consumption, which applies current multiplexing technology to the In the traditional folding cascode operational amplifier circuit, the circuit is mainly a bias constant current source connected in series with differential input, load current mirror and cascode output stage adjustable auxiliary differential pair. The scheme is shown in Figure 1 Show. Although the current multiplexing technology improves the utilization rate of the current in the circuit, this solution increases the transconductance by sacrificing the phase margin of the circuit, and the gain improvement is not large. Under the existing deep submicron technology, RFC The gain of the operational amplifier is far from the accuracy required in practice, and it is difficult to be widely used

In order to solve the inherent contradiction among gain, bandwidth, power consumption, etc. in the operational amplifier circuit, it is necessary to break the traditional structure and design a high-performance operational amplifier with both high gain and high speed.

Utility model content

The technical problem to be solved by the utility model is to provide an operational transconductance amplifier with increased gain. The bias constant current source is sequentially connected to the differential input, the load current mirror and the cascode output stage, as well as the adjustable auxiliary differential pair. This operational transconductance amplifier is weakly affected by the output voltage and does not introduce additional poles. Improve the output impedance and gain of the operational amplifier to achieve high-precision, high-speed operational amplification.

An operational transconductance amplifier with increased gain designed by the utility model includes a biased constant current source and its sequentially connected differential input, load current mirror and cascode output stage, wherein the biased constant current source is a P-type MOS The source of the tube M ₀ is connected to the power supply VDD, and the gate of the M ₀ is connected to the bias voltage V _bias ; the differential input is composed of 4 P-type MOS transistors M _1a , M _2a , M _1b and M _2b , and the load current mirror is composed of 6 N-type MOS transistors M ₃ , M ₄ , M _5a , M _6a , M _5b and M _6b are formed, and the cascode output stage is composed of 2 N-type MOS transistors M ₇ , M ₁₀ and 4 P-type MOS transistors M ₈ , M ₉ , M ₁₁ and M ₁₂ .

The sources of the differential input stage P-type MOS transistors M _1a , M _2a , M _1b and M _2b are respectively connected to the drain of the P-type MOS transistor M ₀ . The drain of the N _- type MOS transistor M3 is respectively connected to the drain of the P-type MOS transistor _M2b , the gates of the N _- type MOS transistors _M5a and _M5b , and the source of the N-type MOS transistor M3 is connected to the gate of the N-type MOS transistor _M5b . _The drain, the drain of the N-type MOS transistor M4 is respectively connected to the drain of the P-type MOS transistor _M1b , the gates of the N-type MOS transistors _M6a and _M6b , and the source of the N _- type MOS transistor M4 is connected to the N-type MOS transistor The drain of M _6b , the gates of N-type MOS transistors M ₃ and M ₄ are connected to the bias voltage V _b1 , and the sources of N-type MOS transistors M _5a , M _5b , M _6a and M _6b are respectively grounded. _The drain of the N _- type MOS transistor M7 of the cascode output stage is connected to the drain of the P-type MOS transistor M8, and is simultaneously connected to the second output terminal Vout ⁻ of the cascode output stage, and the cascode output stage P _The source of the P-type MOS transistor M8 is connected to the drain of the P-type MOS transistor _M9 , the drain of the N-type MOS transistor M10 is _respectively connected to the drain of the P-type MOS transistor _M11 , and simultaneously connected to the first cascode output stage An output terminal Vout ⁺ , the source of the P-type MOS transistor _M11 is connected to the drain _of the P-type MOS transistor M12, the gates of the N-type MOS transistors _M7 and _M10 are connected to the bias voltage V _b1 respectively, and the P-type MOS transistors The gates of M ₈ and M ₁₁ are respectively connected to the bias voltage V _b2 , the gates of P-type MOS transistors M ₉ and M ₁₂ are connected to the common mode feedback voltage CMFB, and the sources of P-type MOS transistors M ₉ and M ₁₂ are connected to the power supply respectively VDD.

The gain boosted operational transconductance amplifier of the present invention also includes an adjustable auxiliary differential pair, which is composed of P-type MOS transistors M ₁₃ , M ₁₄ and M ₁₅ . The gate of the P-type MOS transistor _M13 is respectively connected to the drains of the P-type MOS transistors _M1a and _M14 , the drain of the N-type MOS transistor _M5a and the source of the N-type MOS transistor _M7 , and the P-type MOS transistor _M14 The gates of the gates are respectively connected to the drains of P-type MOS transistors _M2a and _M13 , the drain of N-type MOS transistors _M6a and the source of N-type MOS transistors _M10 , and the sources of P-type MOS transistors _M13 and _M14 It is connected to the drain of the P-type MOS transistor _M15 , and the source of the P-type MOS transistor _M15 is connected to the power supply VDD.

The four P-type MOS transistors M _1a , M _2a , M _1b and M _2b of the differential input receive differential voltage signals, which are converted into currents and injected into the two pairs of current mirror N-type MOS transistors M _5b -M _5a and M _6b - In M _6a , the current output by the current mirror M _6b -M _6a is sent to the output branches M ₁₀ , M ₁₁ , M ₁₂ of the cascode output stage to form the output voltage V _out ⁺ ; the current mirror M _5b -M _5a The output current is sent to another output branch M ₇ , M ₈ , M ₉ of the cascode output stage to form an output voltage V _out ⁻ . The transmission between the current mirrors realizes the current multiplication, and finally realizes the multiplication of the transconductance of the operational transconductance amplifier.

The size ratios of the current mirrors M _5b -M _5a and M _6b -M _6a are the same, that is, the size of M _5a is K compared with the size of M _5b , and the size of M _6a is also K compared with the size of M _6b , the value range of K is 2-5.

MOS transistor M _5a and output branches M ₇ , M ₈ , M ₉ form a cascode output stage, which increases the output impedance ^of the V _out -end, and MOS transistor M _6a and output branches M ₁₀ , M ₁₁ , M ₁₂ form another A cascode output stage increases the output impedance at _Vout ⁺ .

The drain output voltage signal of the P-type MOS transistor _M13 of the adjustable auxiliary differential pair is directly connected to the gate of the P-type MOS transistor _M14 , and the gate voltage signal of the P-type MOS transistor _M13 controls the P-type MOS transistor _M14 . current, the MOS transistor M ₁₄ constitutes a negative resistance; similarly, the drain output voltage signal of the P-type MOS transistor M ₁₄ is directly connected to the gate of the P-type MOS transistor M ₁₃ , and the gate voltage signal of the P-type MOS transistor M ₁₄ Control the current of the P-type MOS transistor _M13 , the MOS transistor _M13 constitutes a negative resistance, the output impedance of _M13 and _M14 together with the output impedance of the cascode constitute the output impedance of the operational transconductance amplifier.

After the differential signal is input, the signal passes through two paths to the output terminal. The first path: the input voltage signal through the gate of M _1a becomes a current signal and transmitted to the drain of M _5a , and then passes through the cascode output branch M _7. M ₈ , M ₉ to the output terminal, the transconductance of this path is the transconductance g _m1a of the MOS transistor M _1a ; the second path: the input voltage signal through the gate of M _1b becomes a current signal and is transmitted to M ₄ The drain terminal is injected into M _6b , copied to M _6a after passing through the current mirror M _6a -M _6a , realizing the current multiplication K times, and passing through the output branches M ₁₀ , M ₁₁ , M ₁₂ of the cascode stage to the output end, which The transconductance of each path is K times the transconductance g _m1b of the MOS transistor M _1b .

The MOS transistors M _1a and M _1b of the differential input have the same size, and the transconductance of the two is proportional to the channel width-to-length ratio W/L, so the transconductance of the two is equal, that is, g _m1b = g _m1a , the utility model calculates The overall transconductance of the transconductance amplifier is G=g _m1a +Kg _m1b =(1+K)g _m1a .

When the potential of the gate of the adjustable auxiliary differential pair M ₁₃ decreases, that is, the drain voltage of the MOS transistor M ₁₄ also decreases, the voltage between the drain and the source of the MOS transistor M ₁₄ rises, and the variation is +Δvd _DS , the decrease in the potential of the gate of M ₁₃ causes the potential of the drain of M ₁₃ and the potential of the gate of MOS transistor M ₁₄ to increase, and the effective input voltage signal V _GS of the gate of MOS transistor M ₁₄ decreases, resulting in a decrease in the potential of the gate of MOS transistor M ₁₄ The amount of decrease in the output current is -Δi _DS , and the output impedance r _O14 =+Δvd _DS /(-Δi _DS )<0 of the MOS transistor M ₁₄ of the auxiliary differential pair is a negative resistance. Similarly, the potential of the gate of M ₁₄ decreases, and it can be analyzed that the output impedance of M ₁₃ is also a negative resistance according to the above method. Neglecting the channel modulation effect of the MOS tube, the conductance (reciprocal of impedance) of M ₁₄ is expressed as g _m14 ; when analyzing the output impedance of small signals, MOS tube M ₁₄ is connected in parallel with M _5a and M _1a , and the output impedance of MOS tube M ₁₄ is r _O14 is a negative value, which can be represented by -1/g _m14 , and the output impedance of the operational transconductance amplifier of the present invention is expressed as

R _out ≈g _m7 r _o7 (r _o1a ||r _o5a ||r _o14 )||g _m8 r _o8 r _o9 .

When the transconductance and output impedance of M ₇ and M ₈ are equal, that is, g _m8 = g _m7 , r _o8 = r _o7 , the output impedance of the operational transconductance amplifier of the present invention is expressed as

R _out ≈g _m7 /[g _o7 (g _o1a +g _o5a +g _o9 -g _m14 )],

Among them, g _mi , r _oi and _goi are respectively the transconductance, output impedance and output conductance of the _i -th MOS transistor Mi in the circuit, and _goi = 1/r _oi .

By increasing g _m14 while ensuring 0≤g _m14 <g _o1a +g _o5a +g _o9 , the output impedance R _out and the gain can be increased, while the system remains stable with residual value.

A better design scheme takes g _m14 =0.85(g _o1a +g _o5a +g _o9 ), and the output impedance R _out is increased by 6.67 times compared with that without adding g _m14 , which can realize a gain increase of 16.5dB.

In order to eliminate the error of the output gain, the gate of the P-type MOS transistor _M15 is connected to the adjustable bias voltage _Vt , and the transconductance _gm of the adjustable auxiliary differential pair _is proportional to the current It flowing through _M13 and _M14 , Simultaneous current That is, g _m =f(V _t ) of the adjustable auxiliary differential pair is a function of V _t , where μ _p is the electron mobility, C _ox is the gate capacitance per unit area, (W/L) ₁₅ is the P-type MOS transistor M The channel width-to-length ratio is ₁₅ , and V _thp is the turn-on voltage of the P-type MOS transistor M ₁₅ . Due to the influence of MOS tube mismatch and process angle, the output gain will deviate from the preset index, which will cause the output error of the op amp. Fine-tuning the adjustable bias voltage V _t , controlling the proportion of the current flowing from the MOS transistor M ₁₅ to M ₁₃ and M ₁₄ , thereby controlling the magnitude of the negative resistance of M ₁₃ and M ₁₄ . That is, by fine-tuning V _t , error-free amplification is realized. The adjustable range of the adjustable bias voltage V _t is ±1mV.

Compared with the prior art, the advantages of a kind of operational transconductance amplifier with increased gain of the utility model are: 1. 1 pair of differential input MOS tubes of the traditional folding operational amplifier is divided into 2 pairs of differential input MOS tubes, and 2 pairs of loads are used simultaneously. The current mirror receives the output signals of 2 pairs of differential input MOS transistors; in this way, the 2 transistors of the cascode output stage are not only used as constant current sources (such as in the folded operational amplifier), but also can effectively use the current, making The transconductance of the operational transconductance amplifier is multiplied; 2. A pair of adjustable auxiliary differential pairs is added to the cascode structure of the cascode output stage, so that the operational transconductance amplifier is very weakly affected by the output voltage, and No extra poles will be introduced; 3. Realize multi-path operational amplification, improve the traditional large constant current source at the output end of the cascode as the drive tube, not only effectively increase the transconductance of the whole operational amplifier, but also improve the instantaneous 4. Under the same static power consumption, the gain, bandwidth and common mode rejection ratio of the operational transconductance amplifier are doubled. Under the 1.2V working power supply, the 90nm COMSTSMC process is used for Specter simulation. The results show that, Under the condition of power consumption of 1.05mW, the DC open-loop gain of this operational transconductance amplifier is 72.7dB, and the unity gain bandwidth is 217.9MHz; compared with the RFC structure op amp, not only the gain is increased by 19dB, but also has high adjustability, Reduce the impact of the process, and can be applied to communication, electronic measurement, and automatic control systems. Effectively improve the output impedance and gain of the operational transconductance amplifier, realize high precision, low power consumption, large bandwidth, high gain, and high-speed operational amplification, and solve the problem of low gain and bandwidth performance degradation of traditional operational amplifiers in the current deep submicron process , The problem of high power consumption.

Description of drawings

FIG. 1 is a schematic diagram of a circuit structure of a comparatively multiplexed folded cascode operational amplifier.

FIG. 2 is a schematic diagram of the circuit structure of an embodiment of the operational transconductance amplifier with increased gain.

Fig. 3 is the amplitude-frequency diagram of the AC small signal of the present embodiment and the comparative example.

FIG. 4 is a phase-frequency diagram of the AC small signal of the present embodiment and the comparative example.

Detailed ways

The traditional multiplexed folded cascode operational amplifier, that is, the RFC operational amplifier is used as a comparison example, and its circuit structure is shown in Figure 1. It includes a bias constant current source and its sequentially connected differential input, load current mirror and cascode output stage.

The embodiment of the operational transconductance amplifier with increased gain is shown in Figure 2. The bias constant current source is sequentially connected in series with a differential input, a load current mirror, a cascode output stage and an adjustable auxiliary differential pair. The bias constant current source is a P-type MOS transistor M ₀ , its source is connected to the power supply VDD, and the gate of M ₀ is connected to the bias voltage V _bias ; the differential input consists of four P-type MOS transistors M _1a , M _2a , and M _1b and M _2b , the load current mirror is composed of 6 N-type MOS transistors M ₃ , M ₄ , M _5a , M _6a , M _5b and M _6b , and the cascode output stage is composed of 2 N-type MOS transistors M ₇ , M ₁₀ and four P-type MOS transistors M ₈ , M ₉ , M ₁₁ and M ₁₂ are formed, and the adjustable auxiliary differential pair is composed of P-type MOS transistors M ₁₃ , M ₁₄ and M ₁₅ .

The sources of the differential input stage P-type MOS transistors M _1a , M _2a , M _1b and M _2b are respectively connected to the drain of the P-type MOS transistor M ₀ . The drain of the N _- type MOS transistor M3 is respectively connected to the drain of the P-type MOS transistor _M2b , the gates of the N _- type MOS transistors _M5a and _M5b , and the source of the N-type MOS transistor M3 is connected to the gate of the N-type MOS transistor _M5b . _The drain, the drain of the N-type MOS transistor M4 is respectively connected to the drain of the P-type MOS transistor _M1b , the gates of the N-type MOS transistors _M6a and _M6b , and the source of the N _- type MOS transistor M4 is connected to the N-type MOS transistor The drain of M _6b , the gates of N-type MOS transistors M ₃ and M ₄ are connected to the bias voltage V _b1 , and the sources of N-type MOS transistors M _5a , M _5b , M _6a and M _6b are respectively grounded. _The drain of the N _- type MOS transistor M7 of the cascode output stage is connected to the drain of the P-type MOS transistor M8, and is simultaneously connected to the second output terminal Vout ⁻ of the cascode output stage, and the cascode output stage P _The source of the P-type MOS transistor M8 is connected to the drain of the P-type MOS transistor _M9 , the drain of the N-type MOS transistor M10 is _respectively connected to the drain of the P-type MOS transistor _M11 , and simultaneously connected to the first cascode output stage An output terminal Vout ⁺ , the source of the P-type MOS transistor _M11 is connected to the drain _of the P-type MOS transistor M12, the gates of the N-type MOS transistors _M7 and _M10 are connected to the bias voltage V _b1 respectively, and the P-type MOS transistors The gates of M ₈ and M ₁₁ are respectively connected to the bias voltage V _b2 , the gates of P-type MOS transistors M ₉ and M ₁₂ are connected to the common mode feedback voltage CMFB, and the sources of P-type MOS transistors M ₉ and M ₁₂ are connected to the power supply respectively VDD.

The gate of the adjustable auxiliary differential pair P-type MOS transistor _M13 is respectively connected to the drains of the P-type MOS transistors _M1a and _M14 , the drain of the N-type MOS transistor _M5a , and the source of the N-type MOS transistor _M7 . The gate of the P-type MOS transistor M14 is respectively connected to the drains of the P-type MOS transistors _M2a and _M13 , the drain of the N-type MOS transistor _M6a and the source of the N-type MOS transistor _M10 , and the P-type _MOS transistors _M13 , The source of M ₁₄ is connected to the drain of the P-type MOS transistor M ₁₅ , the source of the P-type MOS transistor M ₁₅ is connected to the power supply VDD, and the gate of M ₁₅ is connected to the adjustable bias voltage V _t .

In this example, the size of the current mirror _M5a is 3 compared to _M5b , and the size of _M6a is also 3 compared to _M6b .

In this example, the differential input MOS transistors M _1a and M _1b have the same size.

As shown in Figure 2, when the potential of the gate of the adjustable auxiliary differential pair M ₁₃ decreases, that is, the potential of point A in Figure 2 decreases, the drain voltage of the MOS transistor M ₁₄ also decreases, and the drain of the MOS transistor M ₁₄ The voltage between the source and the source rises, and the change is +Δvd _DS , the potential of the gate of M ₁₃ decreases, causing the potential of the drain of M ₁₃ , the potential of the gate of MOS transistor M ₁₄ to rise, and the gate potential of MOS transistor M ₁₄ The effective input voltage signal V _GS of the pole decreases, causing the output current of the MOS transistor M ₁₄ to decrease by -△i _DS , and the output impedance r _O14 of the MOS transistor M ₁₄ of the auxiliary differential pair =+△vd _DS /(-△i _DS )<0 is negative resistance. Similarly, when the potential of the gate of M ₁₄ in Figure 2 decreases, that is, the potential of point B in Figure 2 decreases, the output impedance of M ₁₃ can also be analyzed as negative resistance according to the above method. Neglecting the channel modulation effect of the MOS transistor, the conductance of M ₁₄ is expressed as g _m14 ; when analyzing the output impedance of the small signal, the MOS transistor M ₁₄ is connected in parallel with M _5a and M _1a , and the output impedance r _O14 of the MOS transistor M ₁₄ is a negative value, It can be expressed by -1/g _m14 , and the output impedance of the operational transconductance amplifier in this example is expressed as

R _out ≈g _m7 r _o7 (r _o1a ||r _o5a ||r _o14 )||g _m8 r _o8 r _o9 .

In this example, the transconductance and output impedance of M ₇ and M ₈ are equal, that is, g _m8 = g _m7 , r _o8 = r _o7 , and the output impedance of the operational transconductance amplifier in this example is expressed as

R _out ≈g _m7 /[g _o7 (g _o1a +g _o5a +g _o9 -g _m14 )],

Among them, g _mi and r _oi are the transconductance and output impedance of the i-th MOS tube M _i in the circuit respectively.

In this example, the transconductance g _m14 of M ₁₄ of the adjustable auxiliary differential pair is 0.85(g _o1a +g _o5a +g _o9 ), and the output impedance R _out is increased by 6.67 times compared with that without adding g _m14 , achieving a 16.5dB gain increase.

In this example, the gate of M ₁₅ of the adjustable auxiliary differential pair is connected to the adjustable bias voltage V _t . By fine-tuning V _t , the influence of MOS tube mismatch and process angle can be overcome, the error of output gain can be eliminated, and error-free amplification can be realized. .

In this embodiment and the comparative example, the simulation comparison experiment is carried out under the same voltage and the same power consumption, and the result of the obtained AC small signal amplitude-frequency diagram is shown in Figure 3. In Figure 3, the abscissa is the frequency, the unit is Hz, and the ordinate is the gain. The unit is dB, the solid line in the figure is the AC small signal amplitude-frequency curve of this embodiment, and the dotted line is the AC small signal amplitude-frequency curve of the comparative example.

The results of the AC small-signal phase-frequency diagram obtained by the simulation comparison experiment under the same conditions of the present embodiment and the comparative example are shown in FIG. The solid line is the AC small-signal phase-frequency curve of this embodiment, and the dotted line is the AC small-signal phase-frequency curve of the comparative example.

It can be seen from Figures 3 and 4 that the phase margin of this embodiment is 70.1°, which is still greater than 60° to ensure the stability of the circuit system; under this condition, the low-frequency DC gain of this embodiment reaches 72.7dB, and the comparison ratio is only 53.7dB, an increase of 30 More than %; the unit gain bandwidth of this embodiment is 217.9 MHz, and the comparison ratio is only 192.7. The simulation results of this embodiment have realized the gain multiplication of the operational amplifier. Obviously, the scheme of the present invention has better performance under the same power consumption.

Table 1 further shows the specific performance parameters obtained from the simulation experiments of this embodiment and the comparative example.

The performance parameter contrast table of table 1 present embodiment and comparative example

parameter comparative example This example Power supply voltage (V) 1.2 1.2 Power Consumption (mW) 1.05 1.05 Low frequency gain(dB) 53.7 72.7 Unity Gain Bandwidth (MHz) 192.7 217.9 Phase Margin(deg) 74.6 70.1 Load capacitance (pF) 5 5 Common Mode Rejection Ratio (dB) 11.2 94.5

The above-mentioned embodiments are only specific examples for further specifying the purpose, technical solutions and beneficial effects of the utility model, and the utility model is not limited thereto. All modifications, equivalent replacements, improvements, etc. made within the disclosed scope of the present utility model are included in the protection scope of the present utility model.

Claims (7)

1. an operation transconductance amplifier for gain lifting, comprises biased constant current source and the Differential Input be connected in series successively, load current mirror and cascade output stage, and wherein biased constant current source is P type metal-oxide-semiconductor M ₀source electrode meet power vd D, M ₀grid meet bias voltage V _bias; Differential Input is by 4 P type metal-oxide-semiconductor M _1a, M _2a, M _1band M _2bform, load current mirror is by 6 N-type metal-oxide-semiconductor M ₃, M ₄, M _5a, M _6a, M _5band M _6bform, cascade output stage is by 2 N-type metal-oxide-semiconductor M ₇, M ₁₀and 4 P type metal-oxide-semiconductor M ₈, M ₉, M ₁₁, M ₁₂form;

Differential input stage P type metal-oxide-semiconductor M _1a, M _2a, M _1band M _2bsource electrode meet P type metal-oxide-semiconductor M respectively ₀drain electrode; N-type metal-oxide-semiconductor M ₃drain electrode meets P type metal-oxide-semiconductor M respectively _2bdrain electrode, N-type metal-oxide-semiconductor M _5aand M _5bgrid, N-type metal-oxide-semiconductor M ₃source electrode meet N-type metal-oxide-semiconductor M _5bdrain electrode, N-type metal-oxide-semiconductor M ₄drain electrode meets P type metal-oxide-semiconductor M respectively _1bdrain electrode, N-type metal-oxide-semiconductor M _6aand M _6bgrid, N-type metal-oxide-semiconductor M ₄source electrode meet N-type metal-oxide-semiconductor M _6bdrain electrode, N-type metal-oxide-semiconductor M ₃, M ₄grid meet bias voltage V _b1, N-type metal-oxide-semiconductor M _5a, M _5b, M _6aand M _6bsource electrode respectively ground connection; The N-type metal-oxide-semiconductor M of cascade output stage ₇drain electrode meet P type metal-oxide-semiconductor M ₈drain electrode, connect the second output end vo ut of cascade output stage simultaneously ^-, cascade output stage P type metal-oxide-semiconductor M ₈source electrode meet P type metal-oxide-semiconductor M ₉drain electrode, N-type metal-oxide-semiconductor M ₁₀drain electrode meet P type metal-oxide-semiconductor M respectively ₁₁drain electrode, connect the first output end vo ut of cascade output stage simultaneously ⁺, P type metal-oxide-semiconductor M ₁₁source electrode meet P type metal-oxide-semiconductor M ₁₂drain electrode, N-type metal-oxide-semiconductor M ₇, M ₁₀grid meet bias voltage V respectively _b1, P type metal-oxide-semiconductor M ₈, M ₁₁grid meet bias voltage V respectively _b2, P type metal-oxide-semiconductor M ₉, M ₁₂grid meet common mode feedback voltage CMFB, P type metal-oxide-semiconductor M ₉, M ₁₂source electrode meet power vd D respectively; It is characterized in that:

Also comprise adjustable auxiliary differential pair, adjustable auxiliary differential is to by P type metal-oxide-semiconductor M ₁₃, M ₁₄and M ₁₅form; P type metal-oxide-semiconductor M ₁₃grid meet P type metal-oxide-semiconductor M respectively _1a, M ₁₄drain electrode, N-type metal-oxide-semiconductor M _5adrain electrode and N-type metal-oxide-semiconductor M ₇source electrode, P type metal-oxide-semiconductor M ₁₄grid meet P type metal-oxide-semiconductor M respectively _2a, M ₁₃drain electrode, N-type metal-oxide-semiconductor M _6adrain electrode and N-type metal-oxide-semiconductor M ₁₀source electrode, P type metal-oxide-semiconductor M ₁₃, M ₁₄source electrode meet P type metal-oxide-semiconductor M ₁₅drain electrode, P type metal-oxide-semiconductor M ₁₅source electrode meet power vd D.

2. the operation transconductance amplifier of gain lifting according to claim 1, is characterized in that:

Described current mirror M _5b-M _5a, M _6b-M _6adimension scale identical, i.e. M _5asize and M _5bsize be in a ratio of K, same M _6asize and M _6bsize compare also for the span of K, K is 2 ~ 5.

3. the operation transconductance amplifier of gain lifting according to claim 1, is characterized in that:

The metal-oxide-semiconductor M of described Differential Input _1a, M _1bmeasure-alike, the mutual conductance of the two is equal, i.e. g _m1b=g _m1a, the overall mutual conductance of this operation transconductance amplifier is G=g _m1a+ Kg _m1b=(1+K) g _m1a.

4. the operation transconductance amplifier of gain lifting according to claim 1, is characterized in that:

Described cascade output stage metal-oxide-semiconductor M ₇and M ₈mutual conductance equal, output impedance is equal, i.e. g _m8=g _m7, r _o8=r _o7; The P type metal-oxide-semiconductor M that described adjustable auxiliary differential is right ₁₄mutual conductance g _m14increase, and 0≤g _m14<g _o1a+ g _o5a+ g _o9.

5. the operation transconductance amplifier of gain lifting according to claim 4, is characterized in that:

The P type metal-oxide-semiconductor M that described adjustable auxiliary differential is right ₁₄mutual conductance g _m14=0.85 (g _o1a+ g _o5a+ g _o9).

6. the operation transconductance amplifier of gain lifting according to claim 1, is characterized in that:

The P type metal-oxide-semiconductor M that described adjustable auxiliary differential is right ₁₅grid meet adjustable bias voltage V _t.

7. the operation transconductance amplifier of gain lifting according to claim 6, is characterized in that:

The P type metal-oxide-semiconductor M that described adjustable auxiliary differential is right ₁₅grid meet adjustable bias voltage V _tadjustable range be ± 1mV.