CN204885150U - Transient voltage inhibitor encapsulation subassembly - Google Patents
Transient voltage inhibitor encapsulation subassembly Download PDFInfo
- Publication number
- CN204885150U CN204885150U CN201520651304.4U CN201520651304U CN204885150U CN 204885150 U CN204885150 U CN 204885150U CN 201520651304 U CN201520651304 U CN 201520651304U CN 204885150 U CN204885150 U CN 204885150U
- Authority
- CN
- China
- Prior art keywords
- diode
- capacitive
- zener diode
- diode assembly
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001052 transient effect Effects 0.000 title claims abstract description 34
- 238000005538 encapsulation Methods 0.000 title abstract 3
- 239000003112 inhibitor Substances 0.000 title abstract 3
- 238000004806 packaging method and process Methods 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 abstract description 55
- 230000004044 response Effects 0.000 abstract description 10
- 230000005611 electricity Effects 0.000 abstract 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 20
- 150000001875 compounds Chemical class 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000003381 stabilizer Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model discloses a transient voltage inhibitor encapsulation subassembly, its characterized in that includes: package frame is including a plurality of pins, first capacitive diode cluster spare is installed on the first pin in a plurality of pins, and a zener diode, install on the second pin in a plurality of pins, wherein, first capacitive diode cluster spare with connect via first bonding line electricity between the zener diode. This transient voltage inhibitor encapsulation subassembly adopts capacitive diode cluster spare and zener diode's tandem position to improve transient response speed. Owing to adopt nonpolarity capacitive diode cluster spare, consequently, the arbitrary lead wire of capacitive diode cluster spare can with zener diode's arbitrary pin connection to semiconductor device's connection error reduces owing to leading to the possibility of chip damage.
Description
Technical field
The utility model relates to microelectronics technology, more specifically, relates to Transient Voltage Suppressor package assembling.
Background technology
Transient Voltage Suppressor TVS (TransientVoltageSuppressor) is the high-effect circuit brake developed on voltage-stabiliser tube basis.Profile and the common voltage-stabiliser tube of TVS diode are as good as, but due to the design of special Structure and energy, the transient response speed of TVS diode and surge absoption ability are far above common voltage-stabiliser tube.Such as, the response time of TVS diode is only 10
-12second, and the surge power up to thousands of watts can be absorbed.Under applied in reverse condition, when bearing a high-octane large pulse, the working impedance of TVS diode can be down to extremely low conduction value fast, thus allows big current to pass through, meanwhile, by voltage clamp at predeterminated level.Therefore, TVS diode can protect the precision components in electronic circuit from the damage of various surge pulse effectively.
The manufacturing process of traditional TVS diode is fairly simple, is generally by special shaped doped direct formation PN junction on P+ substrate/N+ substrate.The response speed of TVS diode and its electric capacity closely related.Traditional TVS diode is mainly used in the data terminal in consumer electronics product, as keyboard, side switch and power line etc.Because this type of terminal speed is comparatively slow, less demanding to the transient response speed of TVS diode, electric capacity is generally at more than 20pF.But video data line has high data transmission rate (up to 480M, some video data transmission rates reach more than 1G to its data transmission rate).Therefore, for the protection of video line, the transient response speed of traditional TVS diode just can not meet instructions for use.In transmission of video, the capacitance requirements of TVS diode is less than 1.0pF.
Be in the Chinese patent application of CN201420858051.3 at application number, disclose a kind of by three integrated TVS device formed on a single die of discrete device.As shown in Figure 1, this TVS device comprises the first diode D1, the second diode D2 and Zener diode ZD, wherein the first diode D1 and Zener diode ZD differential concatenation.The anode connection signal end I/O and earth terminal GND respectively of the first diode D1 and Zener diode, the anode of the second diode D2 and negative electrode connection signal end I/O and earth terminal GND respectively.When surge occurs, if bear positive voltage between signal end I/O and earth terminal, and the numerical value of positive voltage is higher than the puncture voltage of Zener diode ZD, then produces the electric current of the reverse flow along the forward of the first diode and Zener diode, thus play the effect of ESD protection.If bear negative voltage between signal end I/O and earth terminal, then only the second diode D2 forward conduction.
TVS device shown in Fig. 1 is unidirectional device, and wherein, common rectifier diode, as the additional capacitor of small capacitances value, is connected with Zener diode.The capacitance of this TVS device will depend on the capacitance of additional capacitor.This TVS device is included in multiple discrete devices integrated in a chip, thus significantly reduces packaging cost, but manufacture craft relative complex.Under the prerequisite not considering process complexity and cost, the unidirectional ESD safeguard function of low electric capacity can be realized.But this TVS device comprises two rightabout current paths, thus directly can not be used as bilateral device.In addition, due to ghost effect and dispel the heat bad, this TVS device is also difficult to reach higher transient power.
Therefore, expect the TVS device of development of new, while raising transient response speed, take into account unidirectional and bidirectional applications requirement, reduce process complexity and cost, and high protection voltage is provided.
Utility model content
The technical problems to be solved in the utility model is to provide a kind of unidirectional or two-way TVS package assembling that capacitive diode assembly can be adopted to improve transient response speed.
According to the utility model, a kind of Transient Voltage Suppressor package assembling is provided, it is characterized in that, comprising: packaging frame, comprise multiple pin; First capacitive diode assembly, is arranged on the first pin in described multiple pin; And first Zener diode, be arranged on the second pin in described multiple pin, wherein, described first capacitive diode assembly is electrically connected via the first bonding line with between described first Zener diode.
Preferably, described first capacitive diode assembly comprises the diode of two reverse parallel connections.
Preferably, described first capacitive diode assembly is singulated dies, comprising the conductive path of the doped region for short circuit opposite types.
Preferably, described conductive path comprises metal level or conductive channel.
Preferably, described first Zener diode is unidirectional or bi-directional zener diode.
Preferably, any one end of described first capacitive diode assembly is electrically connected with any one end of described first Zener diode.
Preferably, described package assembling also comprises: the second capacitive diode assembly, is arranged on described second pin; And the second Zener diode assembly, be arranged on described first pin, wherein, described second capacitive diode assembly is electrically connected via the second bonding line with between described second Zener diode.
Preferably, described package assembling also comprises: the second capacitive diode assembly, is arranged on described first pin; And the second Zener diode assembly, be arranged on the 3rd pin in described multiple pin, wherein, described second capacitive diode assembly is electrically connected via the second bonding line with between described second Zener diode.
Preferably, described package assembling also comprises: the second capacitive diode assembly, is arranged on the 3rd pin in described multiple pin; And the second Zener diode assembly, be arranged on described first pin, wherein, described second capacitive diode assembly is electrically connected via the second bonding line with between described second Zener diode.
Preferably, described first capacitive diode assembly is identical with the structure of described second capacitive diode assembly, and described first Zener diode is identical with the structure of described second Zener diode.
Adopt capacitive diode assembly as non-polar electric capacity according to the Transient Voltage Suppressor package assembling of embodiment of the present utility model.This capacitive diode assembly comprises the first diode and second diode of reverse parallel connection, has almost identical forward characteristic in the two directions.In preferred package assembling, any lead-in wire of capacitive diode assembly can be connected with any lead-in wire of Zener diode, and the connection error that can reduce due to semiconductor device causes the possibility of wafer damage.
Described ultra-low capacitance capacitive diode assembly can realize on very little chip area, drastically increases the applicability of semiconductor device integration packaging, makes device architecture be applicable to multiple different packing forms.Because Semiconductor substrate is directly drawn as another electrode, can reduce by 1 bonding gold wire when encapsulating, cost of manufacture can be reduced significantly, being conducive to industrialization.
In described package assembling, described ultra-low capacitance capacitive diode assembly is connected with Zener diode, on the voltage of Zener diode, only increases the conduction voltage drop of 0.7V, change the electrology characteristic of Zener diode hardly.Such as, by described ultra-low capacitance capacitive diode assembly and a forward voltage 0.8V, reverse breakdown voltage 20V, electric capacity is that the Zener diode Series Package of 20pF is in a shell, a forward voltage 1.5V will be obtained, reverse breakdown voltage 20.7V, and electric capacity only has the ultra-low capacitance TVS package assembling less than 1pF.Because capacitive diode assembly has ultralow capacitance, therefore, the response speed of TVS package assembling can be improved, widen the range of application of all kinds of device greatly, thus can be applied in the data transmission network of high frequency.
Accompanying drawing explanation
By referring to the description of accompanying drawing to the utility model embodiment, above-mentioned and other objects, features and advantages of the present utility model will be more clear, in the accompanying drawings:
Fig. 1 illustrates the circuit diagram of the Transient Voltage Suppressor according to prior art;
Fig. 2 illustrates the circuit diagram of the Transient Voltage Suppressor according to the utility model embodiment;
Fig. 3 illustrates the structural representation of a kind of capacitive diode assembly used in Transient Voltage Suppressor;
Fig. 4 illustrates the structural representation of the another kind of capacitive diode assembly used in Transient Voltage Suppressor;
Fig. 5 illustrates the vertical view of the Transient Voltage Suppressor package assembling according to the utility model first embodiment, sectional view and circuit diagram;
Fig. 6 illustrates the vertical view of the Transient Voltage Suppressor package assembling according to the utility model second embodiment, sectional view and circuit diagram;
Fig. 7 illustrates the vertical view of the Transient Voltage Suppressor package assembling according to the utility model the 3rd embodiment, sectional view and circuit diagram;
Fig. 8 illustrates the vertical view of the Transient Voltage Suppressor package assembling according to the utility model the 4th embodiment, sectional view and circuit diagram.
Embodiment
In more detail the utility model is described hereinafter with reference to accompanying drawing.In various figures, identical element adopts similar Reference numeral to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.In addition, may some known part not shown.
Be to be understood that, when describing certain structure, when one deck, region are called be positioned at another layer, another region " above " or " top " time, can refer to be located immediately at another layer, another over, or itself and another layer, also comprise other layer or region between another region.Further, if this structure overturn, this one deck, a region will be positioned at another layer, another region " below " or " below ".If the form of presentation of " A is directly on B " or " A also adjoins with it on B " in order to describe the situation being located immediately at another layer, another over, will be adopted herein.
In addition, mention the first conduction type and the second conduction type when describing the conduction type of semi-conducting material, wherein the first conduction type is one of P type and N-type, and the second conduction type is another in P type and N-type.
The utility model can present in a variety of manners, below will describe some of them example.
Fig. 2 illustrates the circuit diagram of the Transient Voltage Suppressor (i.e. TVS device) according to the utility model embodiment.This TVS device is unidirectional TVS device, comprises the capacitive diode assembly and Zener diode ZD that are one another in series and connect.The first end of capacitive diode assembly is as the signal end I/O of TVS device, and the second end is connected with the negative electrode of Zener diode ZD.The anode of Zener diode ZD is as the earth terminal GND of TVS device.Capacitive diode assembly comprises the first diode D1 and the second diode D2 that are connected in antiparallel each other.
Different from the prior art shown in Fig. 1, the first diode D1 and the second diode D2 is connected in antiparallel, and forms capacitive diode assembly C1.In capacitive diode assembly C1, the anode of the first diode D1 and the negative electrode of the second diode D2 are connected to the first end of capacitive diode assembly C1 jointly, and the negative electrode of the first diode D1 and the anode of the second diode D2 are connected to second end of capacitive diode assembly C1 jointly.Capacitive diode assembly C1 utilizes the low pressure drop of diode forward and the characteristic of low on-resistance, thus realizes the electrical characteristics of ultra-low capacitance biphase rectification.
In the TVS device shown in Fig. 2, capacitive diode assembly C1 and Zener diode ZD is connected in series.Because capacitive diode assembly C1 has almost identical forward characteristic in the two directions, therefore, this capacitive diode assembly C1 can as non-polar electric capacity.In TVS device, any one with the second end of the first end of capacitive diode assembly C1 can be connected with the negative electrode of Zener diode ZD.As mentioned below, the non-polar properties of capacitive diode assembly C1 is favourable, not only compatible with single to two-way TVS device, and can simplified manufacturing technique.
In unidirectional TVS device, capacitive diode assembly C1 only increases the conduction voltage drop of 0.7V, changes the electrology characteristic of former TVS device hardly.Such as, when the Zener diode being 20pF by capacitive diode assembly C1 and a forward voltage 0.8V, reverse breakdown voltage 20V, electric capacity is connected, to obtain a forward voltage 1.5V, reverse breakdown voltage 20.7V, and electric capacity only there is the ultra-low capacitance TVS device less than 1pF.
When surge occurs, if bear positive voltage between signal end I/O and earth terminal GND, then the first diode D1 conducting, Zener diode ZD bears reverse voltage.If the numerical value of positive voltage is higher than the puncture voltage of Zener diode ZD, then produce the electric current of the reverse flow along the forward of the first diode and Zener diode, thus play the effect that unidirectional ESD protects.
In the circuit diagram shown in Fig. 2, capacitive diode assembly C1 and Zener diode ZD is connected in series.In the product of reality, capacitive diode assembly C1 and Zener diode ZD can be integrated on same semiconductor chip, or be respectively formed to form independent device on different semiconductor chips, as long as according to both connections shown in Fig. 2.
If capacitive diode assembly C1 and Zener diode ZD is formed on different semiconductor chips; manufacturing process both then can optimizing respectively more neatly; make capacitive diode assembly C1 provide low capacitance to improve the transient response speed of TVS device, Zener diode provides high-breakdown-voltage to obtain required protection voltage level.After forming capacitive diode assembly C1 and Zener diode ZD respectively, both bonding line connections can be adopted, and be encapsulated in a shell.
In the embodiment shown in Figure 2, second end of capacitive diode assembly C1 is connected with the negative electrode of Zener diode.In alternate embodiments, because capacitive diode assembly C1 is nonpolarity, second end of capacitive diode assembly C1 can be connected with the anode of Zener diode.In the embodiment that this substitutes, the negative electrode of Zener diode as the first end of the signal end I/O of Transient Voltage Suppressor, capacitive diode assembly C1 as the earth terminal GND of Transient Voltage Suppressor.
Fig. 3 illustrates the structural representation of a kind of capacitive diode assembly used in Transient Voltage Suppressor.This capacitive diode assembly comprises the diode of two reverse parallel connections formed on a semiconductor substrate.
As shown in Figure 3, P++ type Semiconductor substrate 101 forms N-type epitaxial loayer 103.The thickness of epitaxial loayer 103 is such as greater than 2 μm.P+ type isolated area 104 extends to Semiconductor substrate 101 from the surface of epitaxial loayer 103 through epitaxial loayer 103, thus in epitaxial loayer 103, limit the first active area of the first diode and the second active area of the second diode.Isolated area 104 by the first active area and the second active area spaced.Correspondingly, isolated area 104 comprises the peripheral part around the first active area and the second active area, and by the spaced mid portion in the first active area and the second active area.
P++ type doped region 110 is positioned at the first active area, extends to epitaxial loayer 103 from epitaxial loayer 103 surface.Such as, the doping content of doped region 110 is for being greater than 1.0 × 10
18cm
-3.N++ doped region 111 is positioned at the second active area, extends to epitaxial loayer 103 from epitaxial loayer 103 surface.Such as, the doping content of doped region 111 is for being greater than 8.0 × 10
19cm
-3.
Insulating barrier 120 is positioned at above epitaxial loayer 103.First interconnecting line 107 and the second interconnecting line 108 are such as formed by same metal level.First interconnecting line 107 arrives the top surface of epitaxial loayer 103 and isolated area 104 through insulating barrier 120, thus the two is electrically connected to each other.Second interconnecting line 108 arrives the top surface of doped region 110 and 111 through insulating barrier 120, thus the two is electrically connected to each other.Second interconnecting line 108 also for the electrical connection between external circuit, such as, as signal end I/O.
In the capacitive diode assembly of this embodiment, adopt interconnecting line 107 by epitaxial loayer 103 and isolated area 104 short circuit each other, make that doped region 110, epitaxial loayer 103, current path (as indicated by a dashed arrow in the figure) between isolated area 104 and Semiconductor substrate 101 only exist a PN junction.Thus, form the PN junction of the first diode between doped region 110 and epitaxial loayer 103, between Semiconductor substrate 101 and epitaxial loayer 103, form the PN junction of the second diode, thus realize the basic structure of the first diode and the second diode respectively.
Metal layer on back 160 is formed, as earth terminal GND at the back side of Semiconductor substrate 101.First diode and the second diode adopt Semiconductor substrate 101 and the second interconnecting line 108 to be connected in antiparallel.
This capacitive diode assembly comprises the first diode and second diode of reverse parallel connection, utilizes the low pressure drop of diode forward and the characteristic of low on-resistance to realize the electrical characteristics of ultra-low capacitance biphase rectification.This capacitive diode assembly can be used for unidirectional or two-way TVS device as non-polar electric capacity.
Fig. 4 illustrates the structural representation of the another kind of capacitive diode assembly used in Transient Voltage Suppressor.This capacitive diode assembly comprises the diode of two reverse parallel connections formed on a semiconductor substrate.
As shown in Figure 4, P++ type Semiconductor substrate 101 forms N-type epitaxial loayer 103.The thickness of epitaxial loayer 103 is such as greater than 2 μm.P+ type isolated area 104 extends to Semiconductor substrate 101 from the surface of epitaxial loayer 103 through epitaxial loayer 103, thus in epitaxial loayer 103, limit the first active area of the first diode and the second active area of the second diode.Isolated area 104 by the first active area and the second active area spaced.Correspondingly, isolated area 104 comprises the peripheral part around the first active area and the second active area, and by the spaced mid portion in the first active area and the second active area.
P++ type doped region 110 is positioned at the first active area, extends to epitaxial loayer 103 from epitaxial loayer 103 surface.Such as, the doping content of doped region 110 is for being greater than 1.0 × 10
18cm
-3.N++ doped region 111 is positioned at the second active area, extends to epitaxial loayer 103 from epitaxial loayer 103 surface.Such as, the doping content of doped region 111 is for being greater than 8.0 × 10
19cm
-3.
Insulating barrier 120 is positioned at above epitaxial loayer 103.Conductive channel 107, through insulating barrier 120 and epitaxial loayer 103, enters in Semiconductor substrate 101, thus epitaxial loayer 103 and Semiconductor substrate 101 is electrically connected to each other.Interconnecting line 108 arrives the top surface of doped region 110 and 111 through insulating barrier 120, thus the two is electrically connected to each other.Interconnecting line 108 also for the electrical connection between external circuit, such as, as signal end I/O.
In the capacitive diode assembly of this embodiment, adopt conductive channel 107 by epitaxial loayer 103 and Semiconductor substrate 101 short circuit each other, make that doped region 110, epitaxial loayer 103, current path (as indicated by a dashed arrow in the figure) between conductive channel 107 and Semiconductor substrate 101 only exist a PN junction.Thus, form the PN junction of the first diode between doped region 110 and epitaxial loayer 103, between Semiconductor substrate 101 and epitaxial loayer 103, form the PN junction of the second diode, thus realize the basic structure of the first diode and the second diode respectively.
Metal layer on back 160 is formed, as earth terminal GND at the back side of Semiconductor substrate 101.First diode and the second diode adopt Semiconductor substrate 101 and interconnecting line 108 to be connected in antiparallel.
This capacitive diode assembly comprises the first diode and second diode of reverse parallel connection, utilizes the low pressure drop of diode forward and the characteristic of low on-resistance to realize the electrical characteristics of ultra-low capacitance biphase rectification.This capacitive diode assembly can be used for unidirectional or two-way TVS device as non-polar electric capacity.
Fig. 5 illustrates the vertical view of the Transient Voltage Suppressor package assembling according to the utility model first embodiment, sectional view and circuit diagram.
In the drawings, for the sake of clarity, two pins 201 and 202 of packaging frame are only shown, and encapsulating compound are not shown.Be appreciated that in the chip of reality, encapsulating compound encapsulates the semiconductor device be arranged on pin, and a part for pin exposes and is used for external electrical connections from encapsulating compound.
As shown in Figure 5, capacitive diode assembly C1 and Zener diode ZD1 is arranged on pin 201 and 202 respectively.Capacitive diode assembly C1 comprise the first interconnecting line 211, second interconnecting line 213 and therebetween semiconductor laminated 212.See Fig. 3 and Fig. 4, the first interconnecting line 211 and the second interconnecting line 213 are such as formed by metal level respectively.Semiconductor laminated 212 multiple semiconductor layer and/or the doped regions comprising different doping type, thus the diode of two reverse parallel connections can be formed.Zener diode ZD1 comprise the first interconnecting line 221, second interconnecting line 223 and therebetween semiconductor laminated 222.In this embodiment, Zener diode ZD1 can be any one in unidirectional and bi-directional zener diode, and common process can be adopted to make.
Such as by means of solder, first interconnecting line 211 of capacitive diode assembly C1 is electrically connected with the first pin 201, and first interconnecting line 221 of Zener diode ZD1 is electrically connected with the second pin 202.In the inside of package assembling, adopt a bonding line, second interconnecting line 213 of capacitive diode assembly C1 is electrically connected to each other with second interconnecting line 223 of Zener diode ZD1.This package assembling provides the configured in series of capacitive diode assembly C1 and Zener diode ZD1.
As mentioned previously, the capacitive diode assembly C1 adopting two diode compositions of reverse parallel connection is favourable, because can obtain ultra-low capacitance and almost whole electrology characteristics of reservation Zener diode.Adopt the capacitive diode assembly of ultra-low capacitance, in package assembling, the configured in series of capacitive diode assembly and Zener diode achieves ultra-low capacitance.Further, capacitive diode assembly C1 is non-polar.Therefore do not need when being arranged on packaging frame to distinguish first interconnecting line of capacitive diode assembly C1 and the polarity of the second interconnecting line, thus capacitive diode assembly C1 can be placed easily on packaging frame.As shown in Figure 5 c, any lead-in wire of capacitive diode assembly C1 can be connected with one of the anode and negative electrode of Zener diode ZD1.This package assembling connection error that can reduce due to semiconductor device causes the possibility of wafer damage.
Fig. 6 illustrates the vertical view of the Transient Voltage Suppressor package assembling according to the utility model second embodiment, sectional view and circuit diagram.
In the drawings, for the sake of clarity, two pins 201 and 202 of packaging frame are only shown, and encapsulating compound are not shown.Be appreciated that in the chip of reality, encapsulating compound encapsulates the semiconductor device be arranged on pin, and a part for pin exposes and is used for external electrical connections from encapsulating compound.
As shown in Figure 6, capacitive diode assembly C1 and Zener diode ZD2 is arranged on pin 201, and capacitive diode assembly C2 and Zener diode ZD1 is arranged on pin 202.Capacitive diode assembly C1 comprise the first interconnecting line 211, second interconnecting line 213 and therebetween semiconductor laminated 212.See Fig. 3 and Fig. 4, the first interconnecting line 211 and the second interconnecting line 213 are such as formed by metal level respectively.Semiconductor laminated 212 multiple semiconductor layer and/or the doped regions comprising different doping type, thus the diode of two reverse parallel connections can be formed.The structure of capacitive diode assembly C2 and the similar of capacitive diode assembly C1, comprise the first interconnecting line 231, second interconnecting line 233 and therebetween semiconductor laminated 232.Zener diode ZD1 comprise the first interconnecting line 221, second interconnecting line 223 and therebetween semiconductor laminated 222.In this embodiment, Zener diode ZD1 is such as bi-directional zener diode, and common process can be adopted to make.The similar of Zener diode ZD2 and Zener diode ZD1, comprise the first interconnecting line 241, second interconnecting line 243 and therebetween semiconductor laminated 242.
Such as by means of solder, first interconnecting line 211 of capacitive diode assembly C1, first interconnecting line 231 of Zener diode ZD2 are electrically connected with the first pin 201, and first interconnecting line 221 of Zener diode ZD1, first interconnecting line 241 of capacitive diode assembly C2 are electrically connected with the second pin 202.In the inside of package assembling, adopt two bonding lines, second interconnecting line 213 of capacitive diode assembly C1 is electrically connected to each other with second interconnecting line 223 of Zener diode ZD1, and second interconnecting line 243 of capacitive diode assembly C2 is electrically connected to each other with second interconnecting line 233 of Zener diode ZD2.This package assembling provides the configured in series of capacitive diode assembly C1 and Zener diode ZD1, the configured in series of capacitive diode assembly C2 and Zener diode ZD2.Further, adopt pin 201 and 202 respectively as public input and output.
Adopt the capacitive diode assembly of ultra-low capacitance, in package assembling, the configured in series of capacitive diode assembly and Zener diode achieves ultra-low capacitance.Further, capacitive diode assembly C1 and C2 is non-polar.Therefore do not need when being arranged on packaging frame to distinguish first interconnecting line of capacitive diode assembly C1 and C2 and the polarity of the second interconnecting line, thus capacitive diode assembly C1 and C2 can be placed easily on packaging frame.As fig. 6 c, any lead-in wire of capacitive diode assembly C1, C2 can be connected with any lead-in wire of Zener diode ZD1, ZD2.This package assembling connection error that can reduce due to semiconductor device causes the possibility of wafer damage.
Fig. 7 illustrates the vertical view of the Transient Voltage Suppressor package assembling according to the utility model the 3rd embodiment, sectional view and circuit diagram.
In the drawings, for the sake of clarity, three pins 201,202 and 203 of packaging frame are only shown, and encapsulating compound are not shown.Be appreciated that in the chip of reality, encapsulating compound encapsulates the semiconductor device be arranged on pin, and a part for pin exposes and is used for external electrical connections from encapsulating compound.
As shown in Figure 7, Zener diode ZD1 and ZD2 is arranged on pin 201, and capacitive diode assembly C1 is arranged on pin 202, and capacitive diode assembly C2 is arranged on pin 203.Capacitive diode assembly C1 comprise the first interconnecting line 211, second interconnecting line 213 and therebetween semiconductor laminated 212.See Fig. 3 and Fig. 4, the first interconnecting line 211 and the second interconnecting line 213 are such as formed by metal level respectively.Semiconductor laminated 212 multiple semiconductor layer and/or the doped regions comprising different doping type, thus the diode of two reverse parallel connections can be formed.The structure of capacitive diode assembly C2 and the similar of capacitive diode assembly C1, comprise the first interconnecting line 221, second interconnecting line 223 and therebetween semiconductor laminated 222.Zener diode ZD1 comprise the first interconnecting line 231, second interconnecting line 233 and therebetween semiconductor laminated 232.In this embodiment, Zener diode ZD1 is such as unidirectional or bi-directional zener diode, and common process can be adopted to make.The similar of Zener diode ZD2 and Zener diode ZD1, comprise the first interconnecting line 241, second interconnecting line 243 and therebetween semiconductor laminated 242.
Such as by means of solder, first interconnecting line 231 of Zener diode ZD1 and first interconnecting line 241 of Zener diode ZD2 are electrically connected with the first pin 201, first interconnecting line 211 of capacitive diode assembly C1 is electrically connected with the second pin 202, and first interconnecting line 221 of capacitive diode assembly C2 is electrically connected with the 3rd pin 203.In the inside of package assembling, adopt two bonding lines, second interconnecting line 213 of capacitive diode assembly C1 is electrically connected to each other with second interconnecting line 233 of Zener diode ZD1, and second interconnecting line 223 of capacitive diode assembly C2 is electrically connected to each other with second interconnecting line 243 of Zener diode ZD2.This package assembling provides the configured in series of capacitive diode assembly C1 and Zener diode ZD1 and the configured in series of capacitive diode assembly C2 and Zener diode ZD2.Further, adopt pin 201 as public input, adopt pin 202 and 203 respectively as two outputs.
Adopt the capacitive diode assembly of ultra-low capacitance, in package assembling, the configured in series of capacitive diode assembly and Zener diode achieves ultra-low capacitance.Further, capacitive diode assembly C1 and C2 is non-polar.Therefore do not need when being arranged on packaging frame to distinguish first interconnecting line of capacitive diode assembly C1 and C2 and the polarity of the second interconnecting line, thus capacitive diode assembly C1 and C2 can be placed easily on packaging frame.As shown in Figure 7 c, any lead-in wire of capacitive diode assembly C1, C2 can be connected with any lead-in wire of Zener diode ZD1, ZD2.This package assembling connection error that can reduce due to semiconductor device causes the possibility of wafer damage.
Fig. 8 illustrates the vertical view of the Transient Voltage Suppressor package assembling according to the utility model the 4th embodiment, sectional view and circuit diagram.
In the drawings, for the sake of clarity, three pins 201,202 and 203 of packaging frame are only shown, and encapsulating compound are not shown.Be appreciated that in the chip of reality, encapsulating compound encapsulates the semiconductor device be arranged on pin, and a part for pin exposes and is used for external electrical connections from encapsulating compound.
As shown in Figure 8, capacitive diode assembly C1 and C2 is arranged on pin 201, and Zener diode ZD1 is arranged on pin 202, and Zener diode ZD1 is arranged on pin 203.Capacitive diode assembly C1 comprise the first interconnecting line 211, second interconnecting line 213 and therebetween semiconductor laminated 212.See Fig. 3 and Fig. 4, the first interconnecting line 211 and the second interconnecting line 213 are such as formed by metal level respectively.Semiconductor laminated 212 multiple semiconductor layer and/or the doped regions comprising different doping type, thus the diode of two reverse parallel connections can be formed.The structure of capacitive diode assembly C2 and the similar of capacitive diode assembly C1, comprise the first interconnecting line 221, second interconnecting line 223 and therebetween semiconductor laminated 222.Zener diode ZD1 comprise the first interconnecting line 231, second interconnecting line 233 and therebetween semiconductor laminated 232.In this embodiment, Zener diode ZD1 is such as unidirectional or bi-directional zener diode, and common process can be adopted to make.The similar of Zener diode ZD2 and Zener diode ZD1, comprise the first interconnecting line 241, second interconnecting line 243 and therebetween semiconductor laminated 242.
Such as by means of solder, first interconnecting line 211 of capacitive diode assembly C1 and first interconnecting line 221 of capacitive diode assembly C2 are electrically connected with the first pin 201, first interconnecting line 231 of Zener diode ZD1 is electrically connected with the second pin 202, and first interconnecting line 241 of Zener diode ZD2 is electrically connected with the 3rd pin 203.In the inside of package assembling, adopt two bonding lines, second interconnecting line 213 of capacitive diode assembly C1 is electrically connected to each other with second interconnecting line 233 of Zener diode ZD1, and second interconnecting line 223 of capacitive diode assembly C2 is electrically connected to each other with second interconnecting line 243 of Zener diode ZD2.This package assembling provides the configured in series of capacitive diode assembly C1 and Zener diode ZD1 and the configured in series of capacitive diode assembly C2 and Zener diode ZD2.Further, adopt pin 201 as public output, adopt pin 202 and 203 respectively as two inputs.
Adopt the capacitive diode assembly of ultra-low capacitance, in package assembling, the configured in series of capacitive diode assembly and Zener diode achieves ultra-low capacitance.Further, capacitive diode assembly C1 and C2 is non-polar.Therefore do not need when being arranged on packaging frame to distinguish first interconnecting line of capacitive diode assembly C1 and C2 and the polarity of the second interconnecting line, thus capacitive diode assembly C1 and C2 can be placed easily on packaging frame.As shown in Figure 8 c, any lead-in wire of capacitive diode assembly C1, C2 can be connected with any lead-in wire of Zener diode ZD1, ZD2.This package assembling connection error that can reduce due to semiconductor device causes the possibility of wafer damage.
In the above description, known structural element and step are not described in detail.But it will be appreciated by those skilled in the art that and by various technological means, corresponding structural element and step can be realized.In addition, in order to form identical structural element, those skilled in the art can also design the not identical method with method described above.In addition, although respectively describing each embodiment above, this is not also meaning that the measure in each embodiment can not advantageously be combined.
Above embodiment of the present utility model is described.But these embodiments are only used to the object illustrated, and are not intended to limit scope of the present utility model.Scope of the present utility model is by claims and equivalents thereof.Do not depart from scope of the present utility model, those skilled in the art can make multiple substituting and amendment, and these substitute and amendment all should drop within scope of the present utility model.
Claims (10)
1. a Transient Voltage Suppressor package assembling, is characterized in that, comprising:
Packaging frame, comprises multiple pin;
First capacitive diode assembly, is arranged on the first pin in described multiple pin; And
First Zener diode, is arranged on the second pin in described multiple pin,
Wherein, described first capacitive diode assembly is electrically connected via the first bonding line with between described first Zener diode.
2. package assembling according to claim 1, is characterized in that, described first capacitive diode assembly comprises the diode of two reverse parallel connections.
3. package assembling according to claim 2, is characterized in that, described first capacitive diode assembly is singulated dies, comprising the conductive path of the doped region for short circuit opposite types.
4. package assembling according to claim 3, is characterized in that, described conductive path comprises metal level or conductive channel.
5. package assembling according to claim 2, is characterized in that, described first Zener diode is unidirectional or bi-directional zener diode.
6. package assembling according to claim 3, is characterized in that, any one end of described first capacitive diode assembly is electrically connected with any one end of described first Zener diode.
7. package assembling according to claim 1, is characterized in that, also comprises:
Second capacitive diode assembly, is arranged on described second pin; And
Second Zener diode assembly, is arranged on described first pin,
Wherein, described second capacitive diode assembly is electrically connected via the second bonding line with between described second Zener diode.
8. package assembling according to claim 1, is characterized in that, also comprises:
Second capacitive diode assembly, is arranged on described first pin; And
Second Zener diode assembly, is arranged on the 3rd pin in described multiple pin,
Wherein, described second capacitive diode assembly is electrically connected via the second bonding line with between described second Zener diode.
9. package assembling according to claim 1, is characterized in that, also comprises:
Second capacitive diode assembly, is arranged on the 3rd pin in described multiple pin; And
Second Zener diode assembly, is arranged on described first pin,
Wherein, described second capacitive diode assembly is electrically connected via the second bonding line with between described second Zener diode.
10. the package assembling according to any one of claim 7 to 9, it is characterized in that, described first capacitive diode assembly is identical with the structure of described second capacitive diode assembly, and described first Zener diode is identical with the structure of described second Zener diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520651304.4U CN204885150U (en) | 2015-08-26 | 2015-08-26 | Transient voltage inhibitor encapsulation subassembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520651304.4U CN204885150U (en) | 2015-08-26 | 2015-08-26 | Transient voltage inhibitor encapsulation subassembly |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204885150U true CN204885150U (en) | 2015-12-16 |
Family
ID=54829495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520651304.4U Active CN204885150U (en) | 2015-08-26 | 2015-08-26 | Transient voltage inhibitor encapsulation subassembly |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204885150U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108598078A (en) * | 2018-07-11 | 2018-09-28 | 上海艾为电子技术股份有限公司 | a kind of ESD protection circuit and electronic device |
| CN109326592A (en) * | 2018-10-26 | 2019-02-12 | 深圳市鹏朗贸易有限责任公司 | Transient voltage suppressor and method of making the same |
| CN110444537A (en) * | 2019-08-29 | 2019-11-12 | 中国振华集团永光电子有限公司（国营第八七三厂） | A kind of ceramic paster encapsulates the design method of two-way low junction capacity TVS diode |
| CN114005817A (en) * | 2021-11-29 | 2022-02-01 | 无锡会顶电子科技有限公司 | Semiconductor device and method of making the same |
| US11336088B2 (en) | 2019-01-17 | 2022-05-17 | Ipu Semiconductor Co., Ltd. | Transient voltage suppression device |
| WO2024027964A1 (en) * | 2022-08-03 | 2024-02-08 | Siemens Aktiengesellschaft | Semiconductor component |
-
2015
- 2015-08-26 CN CN201520651304.4U patent/CN204885150U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108598078A (en) * | 2018-07-11 | 2018-09-28 | 上海艾为电子技术股份有限公司 | a kind of ESD protection circuit and electronic device |
| CN108598078B (en) * | 2018-07-11 | 2024-06-04 | 上海艾为电子技术股份有限公司 | ESD protection circuit and electronic device |
| CN109326592A (en) * | 2018-10-26 | 2019-02-12 | 深圳市鹏朗贸易有限责任公司 | Transient voltage suppressor and method of making the same |
| CN109326592B (en) * | 2018-10-26 | 2020-08-28 | 南京溧水高新创业投资管理有限公司 | Transient voltage suppressor and method of making the same |
| US11336088B2 (en) | 2019-01-17 | 2022-05-17 | Ipu Semiconductor Co., Ltd. | Transient voltage suppression device |
| CN110444537A (en) * | 2019-08-29 | 2019-11-12 | 中国振华集团永光电子有限公司（国营第八七三厂） | A kind of ceramic paster encapsulates the design method of two-way low junction capacity TVS diode |
| CN114005817A (en) * | 2021-11-29 | 2022-02-01 | 无锡会顶电子科技有限公司 | Semiconductor device and method of making the same |
| WO2024027964A1 (en) * | 2022-08-03 | 2024-02-08 | Siemens Aktiengesellschaft | Semiconductor component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN204885150U (en) | Transient voltage inhibitor encapsulation subassembly | |
| CN105186478B (en) | Transient Voltage Suppressor | |
| CN105932023B (en) | Transient Voltage Suppressor | |
| CN104465723B (en) | A kind of low capacitor transient stage voltage suppressor device and preparation method thereof | |
| CN105185782B (en) | Capacitive diode assembly and its manufacture method | |
| CN204886173U (en) | Transient voltage inhibitor | |
| CN106158851B (en) | Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof | |
| CN106169508B (en) | Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof | |
| CN204348725U (en) | The low capacitor transient stage voltage suppressor device of a kind of single channel | |
| CN203103299U (en) | Highly reliable high-voltage diode for automobile igniter | |
| CN105185783B (en) | Capacitive diode assembly and its manufacturing method | |
| CN107731818A (en) | Transient suppression diode chip structure | |
| CN210778581U (en) | High-reliability transient voltage suppression diode | |
| CN205016525U (en) | Capacitive diode cluster spare | |
| CN205680681U (en) | Multichannel Transient Voltage Suppressor | |
| CN205092242U (en) | Capacitive diode cluster spare | |
| CN207165576U (en) | Transient voltage suppressor | |
| CN202473924U (en) | Ultra-Low Capacitance Transient Voltage Suppression Devices | |
| CN113380786B (en) | Structure of thyristor transient voltage suppression protection device with integrated reverse conduction diode | |
| TWI788213B (en) | Bidirectional electrostatic discharge (esd) protection device | |
| CN108198811B (en) | Transient voltage suppressor and method of manufacturing same | |
| CN206301790U (en) | A kind of two-way ultra-low capacitance Transient Voltage Suppressor | |
| CN210224031U (en) | Integrated low-capacitance ESD protection device | |
| CN207398146U (en) | Transient suppression diode chip structure | |
| CN208400845U (en) | Semiconductor structure and chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20160323 Address after: 101500 Beijing Qingyuan Miyun Road Economic Development Zone No. 3 building 2-3 Patentee after: Beijing East Semiconductor Technology Co., Ltd. Address before: 100015 Beijing city Chaoyang District Dongzhimen West eight room Wanhong No. 2 West Street Patentee before: Beijing Yandong Microelectronic Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210127 Address after: 100176 4d15, 4th floor, building 1, No.8 Wenchang Avenue, economic and Technological Development Zone, Daxing District, Beijing Patentee after: BEIJING YANDONG MICROELECTRONIC TECHNOLOGY Co.,Ltd. Address before: 101500 building 2-3, No.3 Qingyuan Road, Miyun Economic Development Zone, Beijing Patentee before: BEIJING YANDONG SEMICONDUCTOR TECHNOLOGY Co.,Ltd. |