CN204883691U - Duplicate protection device of nonvolatile store content - Google Patents

Abstract

The utility model relates to an improvement reactor protection system's the reliability and the technical problem of security will be solved to nonvolatile store's duplicate protection device, including nonvolatile store, FPGA chip and hardware control circuit switch, nonvolatile store's the guard signal pin of writing is connected with the hardware control circuit switch, and nonvolatile store's chip selection signal pin is connected with a pin of FPGA chip, and another pin and the hardware control circuit switch of FPGA chip are connected, nonvolatile store's a pin writing guard signal pin and FPGA chip is connected to the backplate through the connector of the general logical integrated circuit board at place, then connects to lieing in the backplate on the hardware control circuit switch. The utility model provides nuclear power protection system platform carries out duplicate protection control to the nonvolatile store content requirement has been satisfied in the high nuclear power protection system of flexibility write reliability of protection and implementation among to(for) nonvolatile store.

Description

The double protecting device of nonvolatile memory content

Technical field

The utility model relates to the protective device of nuclear power instrument control field nonvolatile memory content, particularly relates to be controlled by hardwire and the dual mode of fpga chip internal programmable logic control carries out the device of protecting control to nonvolatile memory content.

Background technology

In nuclear power instrument control field, often need some data such as setting value, parameter stored in nonvolatile memory (non-volatilememory, be called for short NVM) in, these parameters are started at I&C system, run and unexpected dead electricity feelings under obtain the data such as the parameter value preset as required, improve the dirigibility of system cloud gray model and reliability.On the other hand, these setting values and parameter keep relative stability, and can not change, therefore need to avoid changing the content stored in NVM chip unintentionally along with the change of I&C system operating condition.

Can be realized by the mode of hardware or software the protection of content in NVM.Chinese patent " read-write protection circuit " (publication No.: CN102243890A) provides a kind of read-write protection circuit content in NVM being carried out to hardware protection, and it mainly comprises storer and control circuit.Control circuit is for determining the power supply that storer receives.Storer has a pin for determining the access status of storer, and when this pin receives high levle voltage, then the access status of storer is set to read-only; When this pin receives low level voltage, then the access status of storer is set to read-write.Wherein, by the design of this control circuit, it can make user's reading and writing memory data of manufacture end, and makes the user of complete machine end only can read data.Chinese patent " in embedded system write-protected control method and device " (publication No.: CN102207913A) provides a kind of mode by software and carries out write-protected method to memory content in embedded system, the method comprises: obtain the illegal writing address causing the abnormal write command interrupted of cpu bus to write, wherein, illegal writing address is pre-arranged as write-protect; Illegal writing address is revised as the address in the region allowing write; The address in the region allowing write is performed to the operation of write command.This invention solves the problem that in embedded system of the prior art, Write-protection method security is lower, improves write-protected security in embedded system.

Existingly mainly adopt the mode of software or hardware to realize to content protecting in NVM, when relevant software or hardware failure, just likely undesigned change is made to content in NVM, thus the normal operation of harm system.This deficiency, for very serious nuclear power I&C system, therefore needs a kind of method of the NVM content in nuclear power I&C system being carried out to multiple protective.

Nuclear power protection system platform based on FPGA does not have software and CPU, is realized steering logic and the calculation function of core completely by FPGA.How realizing on this platform in nuclear power I&C system for the multiple writing protection function of NVM content is the gordian technique affecting reactor protection system platform reliability and security.The method that NVM content based on the nuclear power protection system platform of FPGA carries out multiple protective is also the great research topic of numerous scientific and technical personnel in the industry and the direction of effort for it.

Summary of the invention

The technical problems to be solved in the utility model is the double protecting device and the guard method thereof that propose a kind of nonvolatile memory content; it can make the NVM content in nuclear power protection system both by overall write-protect in units of cabinet, independently can be controlled by all NVM again in cabinet under allowing the prerequisite of write operation by logic board single in cabinet to single NVM content.This protective device and guard method are forbidden when nuclear power protection system is run carrying out write operation to the content of NVM in whole cabinet, simultaneously when nuclear power protection system is debugged as required by cabinet in FPGA on single board control whether to modify to the content in the NVM on this board.

For achieving the above object; the technical solution adopted in the utility model is: a kind of double protecting device of nonvolatile memory content; comprise nonvolatile memory, fpga chip and hardware control circuit switch; it is characterized in that: the write protect signal pin of described nonvolatile memory is connected with described hardware control circuit switch; the chip selection signal pin of described nonvolatile memory is connected with a pin of described fpga chip, and another pin of described fpga chip is connected with described hardware control circuit switch.

The write protect signal pin of the above nonvolatile memory and a pin of described fpga chip are connected to backboard by the connector of the generic logic board at place, are then connected to and are positioned on the described hardware control circuit switch of backboard.

The above generic logic board comprising nonvolatile memory and fpga chip can have polylith; the write protect signal pin of the nonvolatile memory on each block generic logic board and a pin of fpga chip are all connected to backboard by the connector of the generic logic board at place; and these leg signal link together on backboard, be then connected to and be positioned on the hardware control circuit switch of backboard.

Good effect of the present utility model can carry out multiple write-protect to NVM content: first rewrites defencive function by cabinet external hardware control circuit switch control rule, whether hardware control circuit switch is connected by the write protect signal pin of backboard with the NVM chip on generic logic boards all in cabinet, thus control NVM content in whole cabinet and can be carried out wiping and write operation; Second heavily protects the signal exported by the fpga chip pin on generic logic board each in cabinet to control, and whether fpga chip pin is connected with the chip selection signal pin of NVM chip, be write-protected for controlling single NVM content.If first rewrite defencive function when nuclear power protection system is run and forbid carrying out write operation to the content of NVM storer in whole cabinet, then second heavily protect and also forbid that the content to single NVM storeies all in whole cabinet carries out write operation; When nuclear power protection system is debugged, the first rewriting defencive function allows to carry out write operation to the content of NVM in whole cabinet as required, and now the second rewriting defencive function will determine whether according to other signal of fpga chip internal programmable logic allowing to carry out write operation to NVM content single in cabinet.The utility model not only increases in nuclear power protection system for the write-protected reliability of NVM content; and improve its dirigibility implemented, meet based on FPGA nuclear power protection system platform to NVM memory chip store the multifarious requirement that content controls.

Accompanying drawing explanation

Fig. 1 is the schematic diagram that on single generic logic board, nonvolatile memory content is write-protected;

Fig. 2 is the schematic diagram that in a cabinet, all nonvolatile memory contents are write-protected;

Fig. 3 is the write-protect FPGA (Field Programmable Gate Array) schematic diagram of fpga chip to nonvolatile memory.

Embodiment

Be described in further detail embodiment of the present utility model below in conjunction with accompanying drawing, but the present embodiment does not limit the utility model, every employing analog structure of the present utility model and similar change thereof, all should list protection domain of the present utility model in.

A double protecting device for nonvolatile memory content, its carrier implemented can for based on the generic logic board in nuclear power protection system cabinet of FPGA, backboard and the line that is connected.More than one generic logic board is comprised in cabinet, generic logic board comprises the circuit of the chip compositions such as nonvolatile memory, fpga chip, power supply chip, these chip pins or be connected with other signal wire on generic logic board, or be connected with external signal line by the connector on generic logic board.The power pins (Vcc) of these chips and ground pin (Vss or GND) are also connected to power supply (Vcc) and the ground wire (GND) of backboard, are powered to it by backboard.

As shown in Figure 1, nonvolatile memory and fpga chip are positioned on a generic logic board, the write protect signal pin (W_n) of NVM is connected with hardware control circuit switch, the chip selection signal pin (S_n) of NVM is connected with a pin (EEPROM_CHIP_SELECT_IN_N) of fpga chip, another pin (STATUS_WRITE_PROTECT) of fpga chip is connected with hardware control circuit switch, specifically, the write protect signal pin (W_n) of NVM and a pin (STATUS_WRITE_PROTECT) of fpga chip can be connected to backboard by the connector of generic logic board, then be connected to and be positioned on the described hardware control circuit switch of backboard.

As shown in Figure 1, the clock signal (C) of NVM chip, data input signal (D), data output signal (Q), pin serial clock input (EEPROM_SERIAL_CLK_IN) that the signals such as holding signal (HOLD_n) and chip selection signal (S_n) are corresponding with fpga chip respectively, serial date transfer (EEPROM_SERIAL_DATA_IN), serial data exports (EEPROM_SERIAL_DATA_OUT), holding signal input (EEPROM_HOLD_IN_N) is connected with sheet choosing input (EEPROM_CHIP_SELECT_IN_N), thus the signal pins of the NVM signal pins corresponding with fpga chip is connected, achieve fpga chip internal programmable logic to the control of the corresponding signal wire of NVM.

The double protection method of nonvolatile memory content comprises the following steps:

(1) the hardwire control signal (CTRL) produced by hardware control circuit switch inputs write protect signal pin (W_n) and the fpga chip pin (STATUS_WRITE_PROTECT) of nonvolatile memory simultaneously, if hardwire control signal (CTRL) is for writing, then nonvolatile memory can not carry out write operation, if hardwire control signal (CTRL) for writing, then goes to step (2);

(2) the chip selection signal pin (S_n) of signal to nonvolatile memory exported by the pin (NVM_CHIP_SELECT_IN_N) of the fpga chip be connected with the chip selection signal pin (S_n) of nonvolatile memory controls.

Generic logic board carries out write-protect control by the chip selection signal pin (S_n) of NVM and write-protect pin (W_n) to NVM.Wherein, the hard-wired signals (CTRL) that the control signal of the write-protect pin (W_n) of NVM is inputted by the connector of generic logic board controls it; The sheet of NVM selects the control signal of pin (S_n) to be connected with the leg signal of FPGA, is controlled it by the internal programmable logic of FPGA.Simultaneously; the control signal of the write-protect pin of the NVM content inputted by the connector of generic logic board is also sent in fpga chip simultaneously; FPGA (Field Programmable Gate Array) in order to control FPGA inside produces the chip selection signal of NVM content, thus effectively carries out write-protect control to NVM content.

As shown in Figure 1, sheet choosing input (NVM_CHIP_SELECT_IN_N) that the chip selection signal of NVM chip is corresponding with fpga chip is connected, and achieves fpga chip internal programmable logic to the control of the corresponding signal wire of NVM.

Can have polylith generic logic board in cabinet, on all generic logic boards, the connection of the write-protect leg signal of NVM as shown in Figure 2.Write-protect pin (W_n) signal of each NVM is connected to backboard by the generic logic card connector at place; and these signals are connected to together on backboard; then be connected on the hardware control circuit switch of backboard, by the hardware switch on cabinet, it controlled.Determine that whether the write-protect pin of NVM is effective by hardware switch signal (CTRL), that is, whether all NVM in cabinet can be wiped free of and write data.

Fpga chip internal programmable logic carries out write-protect by the chip selection signal pin (S_n) of NVM to the content of NVM, and its schematic diagram as shown in Figure 3.Chip selection signal is undertaken generating with computing by three signals: the signal (NVM_WRITE) NVM being carried out to write operation that in the NVM write protect signal (STATUS_WRITE_PROTECT) produced from cabinet hardware circuit gauge tap, fpga chip, in the mode control signal (LOGIC_MODE_CTRL) of FPGA (Field Programmable Gate Array) and fpga chip, FPGA (Field Programmable Gate Array) generates.Namely, the chip selection signal of NVM only has following condition all to meet could be effective: cabinet hardware circuit switch allows to carry out write operation to NVM, in fpga chip, FPGA (Field Programmable Gate Array) is in specific pattern (such as when FPGA (Field Programmable Gate Array) in fpga chip is in " memory write pattern "), and in fpga chip, FPGA (Field Programmable Gate Array) generates the write signal of NVM content.

Claims (3)

1. the double protecting device of a nonvolatile memory content; comprise nonvolatile memory, fpga chip and hardware control circuit switch; it is characterized in that: the write protect signal pin of described nonvolatile memory is connected with described hardware control circuit switch; the chip selection signal pin of described nonvolatile memory is connected with a pin of described fpga chip, and another pin of described fpga chip is connected with described hardware control circuit switch.

2. the double protecting device of nonvolatile memory content according to claim 1; it is characterized in that: the write protect signal pin of described nonvolatile memory and a pin of described fpga chip are connected to backboard by the connector of the generic logic board at place, are then connected to and are positioned on the described hardware control circuit switch of backboard.

3. the double protecting device of nonvolatile memory content according to claim 2; it is characterized in that: described in comprise nonvolatile memory and fpga chip generic logic board can have polylith; the write protect signal pin of the nonvolatile memory on each block generic logic board and a pin of fpga chip are all connected to backboard by the connector of the generic logic board at place; and these leg signal link together on backboard, be then connected to and be positioned on the hardware control circuit switch of backboard.