CN204706406U - A kind of piezo-resistance adopting novel pin method for designing - Google Patents

Abstract

The utility model relates to a kind of piezo-resistance adopting novel pin method for designing, it is characterized in that piezo-resistance has multiple pin, the position of pin and quantity by calculate and current density emulation draws, avaivable electrode sheet connection during input, output more than one pin.Such design can under the prerequisite of the area and volume that do not change original piezo-resistance substrate, electric current is made to sufficiently flow through filler in piezo-resistance, promote the characteristics such as piezo-resistance through-current capability, shock-resistant ability, improve piezo-resistance useful life and degree of protection.

Description

A piezoresistor adopting a new pin design method

technical field

The utility model belongs to the field of electrical and electronic components. Mainly for varistors, change the pin structure to make the flow performance better.

Background technique

Varistor is a voltage-sensitive non-linear overvoltage protection semiconductor element. It can be divided into many types according to its structure, manufacturing process, materials used, and volt-ampere characteristics. Common varistor devices are metal oxide voltage Varistors, especially zinc oxide varistors. Different from ordinary resistors, varistors are made according to the nonlinear characteristics of semiconductor materials. Ordinary resistors obey Ohm's law, while the voltage and current of varistors have a special nonlinear relationship. When the voltage applied across the varistor is lower than the nominal rated voltage value, the resistance value of the varistor is close to infinity, and there is almost no current flowing inside, which is equivalent to an open circuit in the circuit; when the varistor is two When the terminal voltage is slightly higher than the nominal rated voltage, the varistor will quickly break down and turn on, and change from a high-impedance state to a low-impedance state, and the working current will increase sharply; At the rated voltage, the varistor returns to a high-resistance state; but when the voltage across the varistor exceeds the maximum limit voltage it can withstand, the varistor will be completely broken down and damaged, even if the voltage drops, it cannot recover.

According to the non-linear characteristics of varistors, it is widely used in household appliances and other electronic products for overvoltage protection, lightning protection, surge current suppression, peak pulse absorption, amplitude limiting, high voltage arc extinguishing, noise elimination, Protect semiconductor components, etc. Lightning current is different from interference, noise, and operating overvoltage in ordinary lines. Lightning current is an instantaneous large pulse, and the current can reach hundreds of thousands of amperes within tens of microseconds; the lightning electromagnetic generated in the line through electromagnetic induction The pulse can also reach tens of thousands of amperes. As the main device for surge protection of electrical and electronic systems, varistors must be able to discharge such a large lightning current or lightning electromagnetic pulse into the ground in an instant to ensure the safe use of the protected equipment behind it. The requirements for parameters such as flow capacity and impact resistance are extremely high.

At present, the packaging methods of varistors in the domestic and foreign markets include patch type and pin type, but they are only two contact poles, that is, for the internal filling material (commonly zinc oxide grains and grain boundary layers) Generally speaking, the path of current flowing through them is a single path of "one in and one out", and the current must choose the path with the least resistance to pass through, so this single path is very short, that is to say, the varistor of a complete varistor Only a small part of the internal filling material is used to resist the current shock and discharge the current. The existing two-pin design of varistors with "one input and one output" has some defects in current flow and impact resistance. Macroscopically, it reflects that the service life of varistors is short, and it is not enough to resist lightning protection. Larger lightning current impact is difficult to meet the requirements of national standards.

Utility model content

In order to effectively solve the above problems in the prior art, the utility model proposes a piezoresistor using a new pin design method to comprehensively improve the current flow capacity caused by the single path of "one in and one out" of the existing piezo pins Poor impact resistance and poor impact resistance, this new pin design can effectively prolong the service life of the same varistor substrate and improve its practical application effect. This kind of varistor with a new pin design method will be an innovative utility model in the varistor manufacturing industry, and it can be better used in various lightning protection devices, thereby bringing huge economic benefits ; At the same time enhance the industry's dominant position in international competition.

The utility model adopts the following technical solutions: the utility model is a piezoresistor adopting a new pin design method. Under the premise of not increasing or changing the volume of the piezoresistor substrate, the number and position of the pins are calculated and The current density simulation determines the result of the maximum utilization of the internal filling material, thereby improving the flow capacity and impact resistance characteristics of the varistor, and improving the service life and protection level of the varistor. The utility model mainly includes piezoresistor substrates, electrode sheets and pins.

The utility model is characterized in that:

1. The position and number of pins of the varistor adopting the new pin design method are determined according to calculation and current density simulation. Such a design can make the current fully flow through the internal filling material and improve the utilization rate of the internal material. , so as to improve the flow capacity and impact resistance of the entire varistor without increasing or changing the volume of the varistor substrate.

2. The varistor adopting the new pin design method can be designed as a typical structure of "two inputs and one output". The direction of current inflow is two pins, which are connected by one electrode sheet; the direction of current outflow is one pin.

3. The varistor adopting the new pin design method can be designed as a typical structure of "one input and two outputs". The direction of current inflow is one pin; the direction of current outflow is two pins, which are connected by an electrode sheet.

4. The varistor adopting the new pin design method can be designed as a typical structure of "two inputs and two outputs". The direction of current flow is two pins, which are connected by an electrode sheet; the direction of current flow is also two pins. , connected with an electrode piece.

5. The design of the varistor adopting the new pin design method also includes the forms of "multiple input and one output", "one input and multiple places", "multiple input and multiple outputs", etc. The outlet end is connected with electrode pads.

Description of drawings

Fig. 1 is a schematic diagram of the principle of the first exemplary embodiment of the present utility model.

Fig. 2 is a schematic diagram of the principle of the second exemplary embodiment of the present invention.

Fig. 3 is a principle schematic diagram of a third exemplary embodiment of the present invention.

FIG. 4 is a current density simulation model 1 of the first exemplary embodiment of the present invention.

FIG. 5 is the current density simulation diagram 1 of the first typical embodiment of the present invention.

FIG. 6 is a current density simulation model 2 of the first exemplary embodiment of the present invention.

Fig. 7 is the current density simulation Fig. 2 of the first typical embodiment of the present invention.

FIG. 8 is a current density simulation model 3 of the first exemplary embodiment of the present invention.

FIG. 9 is the current density simulation diagram 3 of the first exemplary embodiment of the present invention.

Detailed ways

Below in conjunction with accompanying drawing and embodiment the utility model is further described:

Figure 1 is the first typical embodiment of the present utility model, current "two in and one out" type, 1-1 is the current input electrode sheet, 1-2a is the current input pin 1, 1-2b is the current input pin 2. 1-3 are current output pins, and 1-4 are varistor substrates.

Figure 2 is the second typical embodiment of the present utility model, current "one into two out" type, 2-1 is the current input pin, 2-2 is the varistor substrate, 2-3a is the current output pin 1, 2-3b are current output pins 2, and 2-4 are current output electrode sheets.

Figure 3 is the third typical embodiment of the utility model, current "two in two out" type, 3-1 is the current input electrode sheet, 3-2a is the current input pin 1, 3-2b is the current input pin 2. 3-3a is the current output pin 1, 3-3b is the current output pin 2, 3-4 is the current output electrode sheet, and 3-5 is the varistor substrate.

In addition to the three typical embodiments shown in Figures 1, 2, and 3, the utility model can also be other embodiments of the current "multiple input and one output" type, "one input and multiple output" type, and "multiple input and multiple output" type. .

Fig. 4-Fig. 9 are three kinds of current density simulation models and simulation diagrams of the first typical embodiment of the utility model, under the situation of different positions of the piezoresistor inlet and outlet pins, the two electrodes at the inlet end are connected in parallel, and the With the same magnitude of current, observe the current distribution on the electrodes and on the piezoresistor chip, and determine the best position of the pin, so as to better improve product performance. Through multiple simulation experiments, in the models shown in Figure 4-9, the maximum current density of the piezoresistor chip is 1.69×e ⁹ A/m ² , 6.15×e ⁸ A/m ² , 5.35×e ⁸ A/m 2 m, the position of the pins used in the models in Figure 8 and Figure 9 is relatively better; and the appropriate increase in the electrode width also improves the performance of the resistor. The current density simulation of the second typical embodiment and the third typical embodiment is also the same. The data obtained by several connection methods and connection positions are compared, and the final piezoresistor pin connection scheme is obtained through comparison, that is, through the experiment Data collection ultimately determines which connection method to use to minimize resistivity.

The number of current input and output pins is obtained based on calculation and current density simulation. The position and number of pins determine the path and density of current in the varistor filling material.

The incoming or outgoing wires that are larger than one pin are connected with electrode sheets. The electrode piece can be used as the fixed end of the connecting wire when the piezoresistor is in use.

The new pin design method is an improvement and promotion of the original varistor substrate without changing the area and volume of the original varistor substrate.

Utilizing the technical solution of the utility model to achieve corresponding technical effects, or equivalent transformation of the technical solution without departing from the design idea of the utility model, all fall within the protection scope of the utility model.

Claims (6)

1. A varistor adopting a novel pin design method is characterized in that: the varistor has a plurality of pins, and more than one pin of the input and output terminals can be connected by an electrode sheet; the varistor substrate, tube Composed of feet and electrodes. 2. A varistor adopting a novel pin design method according to claim 1, characterized in that: the area and volume of the original varistor substrate are not changed. 3. A varistor using a new pin design method according to claim 1, characterized in that: the input and output pins of the varistor adopt a "two-in-one-out" design. 4. A varistor using a new pin design method according to claim 1, characterized in that: the input and output pins of the varistor adopt a "one-in, two-out" design. 5. A varistor using a new pin design method according to claim 1, characterized in that: the input and output pins of the varistor adopt a "two-in, two-out" design. 6. A varistor using a new pin design method according to claim 1, characterized in that: the input and output pins of the varistor can also adopt "multiple input and one output", "one input and multiple output" , "Multiple in and multiple out" design.