CN204679541U - A kind of digital oscilloscope based on flush bonding processor - Google Patents

Abstract

The utility model discloses a kind of digital oscilloscope based on flush bonding processor, it is characterized in that: comprise FPGA circuit, controllable gain amplifying circuit, frequency measurement circuit, sampling hold circuit, A/D convertor circuit, display screen and matrix keyboard; Controllable gain amplifying circuit is the front end of digital oscilloscope, directly connects input signal; Controllable gain amplifying circuit, sampling hold circuit, A/D convertor circuit are connected with FPGA circuit connected in series; Controllable gain amplifying circuit, frequency measurement circuit are connected with FPGA circuit connected in series; FPGA is connected with controllable gain amplifying circuit, frequency measurement circuit, sampling hold circuit, A/D convertor circuit, display screen and matrix keyboard respectively, for controlling controllable gain amplifying circuit, frequency measurement circuit, sampling hold circuit, A/D convertor circuit work and completing the interactive function of digital oscilloscope and user.The utility model is a kind of cheap, easy to carry, specificity and digital oscilloscope with strong points.

Description

A Digital Oscilloscope Based on Embedded Processor

technical field

The utility model belongs to the technical field of electronic measuring instruments and relates to a digital oscilloscope, in particular to a digital oscilloscope based on an embedded processor NIOS II.

Background technique

Digital oscilloscope is an indispensable tool for designing, manufacturing and maintaining electronic equipment. It can convert electrical signals that cannot be observed by naked eyes into visible images, which is convenient for studying the changing process of this electrical phenomenon. The application of traditional analog oscilloscope is limited due to its single function and low measurement accuracy. Digital storage oscilloscopes use microprocessors for acquisition, processing and measurement analysis, greatly improving measurement accuracy and processing speed. Compared with traditional analog oscilloscopes, digital oscilloscopes not only have the advantages of storing waveforms, small size, low power consumption, and convenient use, but also have powerful real-time signal analysis and processing functions.

At present, digital oscilloscopes on the market already have powerful measurement functions, but they still have disadvantages such as expensive, inconvenient to carry, poor specificity and pertinence.

Utility model content

In order to solve the above-mentioned technical problems, the utility model provides a digital oscilloscope with low price, convenient portability, specificity and strong pertinence.

The technical scheme adopted by the utility model is: a digital oscilloscope based on an embedded processor, characterized in that it includes an FPGA circuit, a controllable gain amplifier circuit, a frequency measurement circuit, a sampling and holding circuit, an AD conversion circuit, a display screen and Matrix keyboard; described controllable gain amplifier circuit is the front end of digital oscilloscope, directly connected to input signal; described controllable gain amplifier circuit, sample and hold circuit, AD conversion circuit and FPGA circuit are connected in series; described controllable gain amplifier circuit Amplifying circuit, frequency measuring circuit and FPGA circuit are connected in series; Described FPGA is connected with described controllable gain amplifying circuit, frequency measuring circuit, sample and hold circuit, AD conversion circuit, display screen and matrix keyboard respectively, is used for controlling all The controllable gain amplifying circuit, frequency measuring circuit, sampling and holding circuit, and AD conversion circuit described above work, and the interactive function between the digital oscilloscope and the user is completed.

As preferably, the core device of the FPGA circuit is a Nios II embedded processor.

As a preference, the controllable gain amplifying circuit is composed of a small signal amplifying circuit and a large signal amplifying circuit, and adopts broadband, high-performance operational amplifiers OPA656, OPA847 and THS3001, and the FPGA circuit controls the relay to switch the feedback resistor of OPA656 to change the signal amplification multiples to improve the signal-to-noise ratio.

Preferably, the controllable gain amplifying circuit is further equipped with a 7th-order passive Butterworth filter to filter high-frequency noise, and the cut-off frequency of the filter is 10 MHz.

Preferably, the frequency measuring circuit is composed of two parts, the first part is an OPA656 saturated amplifier circuit, and the second part is a hysteresis comparison circuit realized by a high-speed comparator TLV3501.

As preferably, the sample-and-hold circuit is made up of amplifier THS4011, analog switch TS5A3166, 220pF sample-and-hold capacitor, programmable delay chip AD9501; two amplifiers THS4011 are used as isolated analog switch TS5A3166 and sample-and-hold capacitor, and the Turn on and off the sampling and holding state of the corresponding sampling and holding circuit; the programmable delay chip AD9501 realizes the precise delay of the sampling and holding clock, generates a step-delayed sampling sequence pulse, and realizes the acquisition of high-frequency signals.

As preferably, the AD conversion circuit adopts 12-bit high-speed AD conversion chip ADS805, the output signal of the sample and hold circuit is input from the non-inverting terminal, and the inverting terminal of the AD conversion chip ADS805 is connected to the internal 2.5V reference level. It is used to collect 0~5V signal.

Preferably, the display screen adopts a TFT display and is driven by an FPGA circuit for display.

The utility model takes NIOS II as the control core, and can quickly collect, analyze and measure data. Using the FPGA circuit to control the timing can ensure the digital oscilloscope to carry out accurate gain control and AD equivalent sampling; the utility model reasonably sets the amplification factor of the signal, selects high-performance devices, and adopts filtering, decoupling, etc. to reduce noise. technology, which improves the sampling accuracy and reliability of the digital oscilloscope. The utility model can display signal waveforms and measure various commonly used power parameters, has stable and reliable performance, and is easy to operate.

Description of drawings

Fig. 1: is the structural diagram of the utility model embodiment.

Fig. 2: is the circuit diagram of the small signal amplifier of the utility model embodiment.

Fig. 3: is the circuit diagram of the large-signal amplifier of the utility model embodiment.

Fig. 4: is the frequency measurement circuit diagram of the utility model embodiment.

Fig. 5: is the equivalent sampling principle diagram of the embodiment of the present invention.

Fig. 6: is the sample and hold circuit diagram of the utility model embodiment.

Fig. 7: is the circuit diagram of the AD conversion circuit of the embodiment of the present invention.

Detailed ways

In order to facilitate those of ordinary skill in the art to understand and implement the utility model, the utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the implementation examples described here are only used to illustrate and explain the utility model, and It is not used to limit the utility model.

Please see Fig. 1, a kind of digital oscilloscope based on embedded processor that the present embodiment provides, comprises FPGA circuit, controllable gain amplifying circuit, frequency measurement circuit, sample and hold circuit, AD conversion circuit, display screen and matrix keyboard; FPGA The circuit uses Altera's CycloneⅢ series devices, the core device is Nios Ⅱ embedded processor; the controllable gain amplifier circuit is the front end of the digital oscilloscope, directly connected to the input signal; the controllable gain amplifier circuit, sample and hold circuit, AD conversion circuit and FPGA The circuits are connected in series; the controllable gain amplifier circuit, the frequency measurement circuit and the FPGA circuit are connected in series; Controllable gain amplification circuit, frequency measurement circuit, sample and hold circuit, AD conversion circuit work, and complete the interactive function between the digital oscilloscope and the user.

The controllable gain amplifying circuit of this embodiment is composed of a small signal amplifying circuit and a large signal amplifying circuit, adopts broadband, high-performance operational amplifiers OPA656, OPA847 and THS3001, switches the feedback resistor of OPA656 by the FPGA circuit control relay, and changes the signal amplification factor, Improve the signal-to-noise ratio.

As shown in FIG. 2 , it is a small signal amplification circuit diagram of this embodiment. In order to realize the input impedance of 1MΩ, the system OPA847 (U4) is connected to the 1.77MΩ resistor R22 to the ground, and the THS3001 (U1) is connected to the 3MΩ resistor R8 to the ground. In the small signal amplification circuit, the voltage from 2mV to 16mV is amplified by 250 times, and the voltage from 16mV to 80mV is amplified by 62.5 times. The first-stage OPA847 (U4) is fixedly amplified by 40 times, and then passed through a 7th-order passive Butterworth low-pass with a cut-off frequency of 10MHz composed of resistors R19, R23, inductors L4, L5, L6, and capacitors C8, C10, C11, and C12. filter. The signal enters OPA656 (U5) after the DC signal is isolated by C7. OPA656 switches the ground resistance R11 and R15 through relay S2 to achieve 12.5 times and 3.125 times changes, and finally achieves 250 times and 62.5 times amplification. The resistor R24 from the U53 pin to ground is for passing the bias current.

As shown in FIG. 3 , it is a circuit diagram of a large signal amplification circuit of this embodiment. Signals from 80mV to 800mV should be amplified by a factor of 6.25, and signals from 800mV to 8V should be amplified by a factor of 0.625. In order to realize the maximum signal input of 8VPP, the first stage uses THS3001 (U1) for voltage follower. The second stage uses OPA656 (U2) to switch between 1x and 10x amplification, and then passes through a low-pass filter with the same cut-off frequency composed of resistors R7, R33, inductors L1, L2, L3, and capacitors C3, C4, C5, and C6. , the final signal is amplified by 2.5 times fixedly through OPA656 (U3), and finally realizes the amplification of 6.25 times and 0.625 times.

The controllable gain amplifying circuit of this embodiment is also equipped with a 7th-order passive Butterworth filter to filter out high-frequency noise, and the cut-off frequency of the filter is 10 MHz.

As shown in FIG. 4, it is a frequency measurement circuit diagram of this embodiment. The frequency measuring circuit consists of two parts, the first part is OPA656 saturated amplifier circuit, the second part is hysteresis comparison circuit realized by high-speed comparator TLV3501. The input signal of the frequency measuring circuit is the output signal of the controllable gain amplifier. The output signal amplitude range of the controllable gain amplifier is 500mV _PP ~ 5V _PP . OPA656 saturation amplifier circuit (U6) fixedly amplifies the input signal by 15.5 times, and the output signal is saturated and cut off. The saturated amplified signal is compared with the hysteresis through the high-speed comparator TLV3501 (U7). The high-speed comparator TLV3501 is a high-speed comparator with only 4.5ns delay and rail-to-rail output, which is very suitable for voltage comparison with a maximum frequency of 10MHz in this embodiment.

As shown in FIG. 5 , it is a schematic diagram of equivalent sampling in this embodiment. In order to ensure that the collected signal is not distorted, according to the Nyquist sampling theorem, the sampling rate is at least twice the signal. In actual engineering applications, in order to ensure that the waveform is not distorted, it is generally necessary to collect signals at a sampling rate of more than 10 times. In this embodiment, the sampling rate is set to 20 times the signal frequency, that is, 20 points are collected in one signal cycle. This requires a sampling rate of up to 200MHz, realized with the principle of equivalent sampling. The basic principle of equivalent sampling is to obtain and reconstruct the signal waveform through multiple triggers and multiple sampling. The premise is that the signal must be repeated. Equivalent sampling reorganizes the data sampled in different periods of the signal through multiple sampling, so that the original signal waveform can be reconstructed.

As shown in FIG. 6 , it is a sample and hold circuit diagram of this embodiment. The sample and hold circuit is composed of amplifier THS4011, analog switch TS5A3166, 220pF sample and hold capacitor, and programmable delay chip AD9501; two amplifiers THS4011 are used to isolate the analog switch TS5A3166 and the sample and hold capacitor, and the opening and closing of the analog switch TS5A3166 correspond to sampling Hold the sampling and holding state of the circuit; the programmable delay chip AD9501 realizes the precise delay of the sampling and holding clock, generates a step-delayed sampling sequence pulse, and realizes the acquisition of high-frequency signals; two THS4011 (U8, U9) The role is to isolate the amplification. The output signal of the sample-and-hold circuit is superimposed with a 2.5V DC level in order to balance with the fixed 2.5V DC bias of the inverting terminal of the AD conversion circuit ADS805 (U12). The sampling and holding clock of the analog switch TS5A3166 (U10) is output by AD9501 (U11). AD9501 is a programmable delay chip, and the delay time can be determined by programming. According to the AD9501 data sheet, the full scale of the delay time is t _DFS = R _SET × (C _EXT +8.5pF) × 3.84 = 7.5 × 8.5 × 3.84 = 244.8ns. Because the on-resistance of TS5A3166 is 0.9Ω, a 15Ω resistor R40 is connected in series with the output, and the value of holding capacitor C14 is 220pF. Then, the time constant of the circuit during sampling is T=RC=15.9×220×10 ⁻³ =3.498 ns. Taking 3T as the sampling time of the circuit, the estimated sampling time is about 10 ns. The delay output is connected to the reset terminal through an RC delay circuit, and the reset delay time constant is 180ns, which meets the delay requirement of the sampling time.

As shown in FIG. 7 , it is a circuit diagram of the AD conversion circuit of this embodiment. The AD conversion circuit uses a 12-bit high-speed AD conversion chip ADS805, the output signal of the sample-and-hold circuit is input from the non-inverting terminal, and the inverting terminal of the AD conversion chip ADS805 is connected to the internal 2.5V reference level for collecting 0-5V signals; ADS805 (U12) is a 12-bit high-speed AD converter, the sampling rate can reach up to 20MHz, and the amplitude range of the input signal is 2V _PP ~ 5V _PP . The SEL pin of ADS805 is connected to the ground, select the input range of 0~5V _PP , and the reverse input terminal Connect to internal voltage reference pin V _REF . This connection means that the common-mode voltage at the input is 2.5V.

The display screen of this embodiment adopts a TFT display and is driven by an FPGA circuit for display. The content displayed on the display screen includes: waveform display window, function menu, and measurement parameters. The waveform display window is the main part of the display screen, and the window is divided into grids, with 10 grids in the horizontal direction and 8 grids in the vertical direction. The center of the display screen is the window for waveform display, and the power parameters displayed by default on the right side are: average value, maximum value, minimum value, and trigger value. The measured power displayed in the window includes peak-to-peak value, root mean square value, period, and frequency. The current vertical voltage resolution and horizontal scanning speed are displayed below the waveform window.

The matrix keyboard of this embodiment is used for function selection. Selected functions include: 2mV/div, 10mV/div, 100mV/div and 1V/div four vertical sensitivity switching, 25 levels of horizontal scanning switching from 500ms to 100ns, waveform translation, waveform storage and playback, measurement amplitude, measurement frequency, Cursor measurement, automatic measurement.

The utility model work process is as follows:

The utility model adopts the FPGA circuit of CycloneⅢ series of Altera Company as the control core to collect, display and measure the input signal. There are four vertical voltage resolutions: 2mV/div, 10mV/div, 100mV/div and 1V/div. Users can choose the appropriate vertical resolution according to the size of the current input signal. If the vertical resolution is too large, the displayed waveform will be cut off. If the resolution is too small, the displayed waveform will be too small, which will affect the observation. The scanning speed in the horizontal direction has 25 levels from 500ms to 100ns. The user can choose the appropriate horizontal scanning speed according to the frequency of the current input signal. If the horizontal scanning speed is too small, the waveform of the complete cycle cannot be displayed. If the horizontal scanning speed is too high, the waveform will overlap and affect the observe. In addition to manually adjusting the vertical voltage resolution and horizontal scanning speed, you can also press the ATUO key for automatic setting, and the system will automatically set the vertical resolution and horizontal scanning speed to the most suitable gear. You can rotate the button to move the waveform up and down or left and right, and observe the changes of the waveform within a sampling period. Waveform storage and playback can record waveforms, and the data will not be lost when power is off, and can be played back when needed. The system sets a cursor line, the user can rotate the cursor line to any waveform and any position, the window can display the data of the intersection point of the cursor line and the waveform in real time, and two cursor lines can be set, so that the difference between the two cursor lines can be displayed.

It should be understood that the parts not described in detail in this specification belong to the prior art.

It should be understood that the above-mentioned descriptions for the preferred embodiments are relatively detailed, and cannot therefore be considered as limiting the protection scope of the utility model patent. In the case of the scope of protection of the new claims, replacement or deformation can also be made, all of which fall within the protection scope of the utility model, and the scope of protection of the utility model should be based on the appended claims.

Claims (8)

1. a kind of digital oscilloscope based on embedded processor, it is characterized in that: comprise FPGA circuit, controllable gain amplifying circuit, frequency measuring circuit, sample and hold circuit, AD conversion circuit, display screen and matrix keyboard; Described controllable Gain amplifying circuit is the front end of digital oscilloscope, directly connected to input signal; Described controllable gain amplifying circuit, sample and hold circuit, AD conversion circuit and FPGA circuit are connected in series; Described controllable gain amplifying circuit, frequency measurement circuit and FPGA The circuits are connected in series; the FPGA is connected with the controllable gain amplifier circuit, frequency measurement circuit, sample and hold circuit, AD conversion circuit, display screen and matrix keyboard respectively, for controlling the controllable gain amplifier circuit, The frequency measuring circuit, the sampling and holding circuit, the AD conversion circuit work, and the interactive function between the digital oscilloscope and the user is completed. 2. the digital oscilloscope based on embedded processor according to claim 1, is characterized in that: the core device of described FPGA circuit is NiosⅡ embedded processor. 3. the digital oscilloscope based on embedded processor according to claim 1, is characterized in that: described controllable gain amplifying circuit is made up of small signal amplifying circuit and large signal amplifying circuit, adopts broadband, high-performance operational amplifier OPA656 , OPA847 and THS3001, the FPGA circuit controls the relay to switch the feedback resistor of OPA656 to change the signal amplification factor and improve the signal-to-noise ratio. 4. The digital oscilloscope based on embedded processor according to claim 1 or 3, characterized in that: the controllable gain amplifier circuit is also equipped with a 7-order passive Butterworth filter to filter out high-frequency noise , the cutoff frequency of the filter is 10MHz. 5. the digital oscilloscope based on embedded processor according to claim 1, is characterized in that: described frequency measuring circuit is made up of two parts, and the first part is OPA656 saturated amplifier circuit, and the second part is made of high-speed comparator TLV3501 Realized hysteresis comparator circuit. 6. the digital oscilloscope based on embedded processor according to claim 1, is characterized in that: described sample and hold circuit is made up of the sample and hold capacitor of amplifier THS4011, analog switch TS5A3166, 220pF, programmable delay chip AD9501; Two amplifiers THS4011 are used to isolate the analog switch TS5A3166 and the sample-and-hold capacitor. The opening and closing of the analog switch TS5A3166 corresponds to the sampling and holding state of the sample-and-hold circuit; the programmable delay chip AD9501 realizes the precise delay of the sample-hold clock and generates The sampling sequence pulse with step delay realizes the acquisition of high-frequency signals. 7. the digital oscilloscope based on embedded processor according to claim 1, is characterized in that: described AD conversion circuit adopts 12 high-speed AD conversion chips ADS805, and the output signal of described sampling and holding circuit is input from noninverting terminal , The inverting end of the AD conversion chip ADS805 is connected to the internal 2.5V reference level for collecting 0-5V signals. 8. The digital oscilloscope based on an embedded processor according to claim 1, characterized in that: said display screen adopts a TFT display, and is driven and displayed by an FPGA circuit.