CN204536697U - Display panel - Google Patents

Abstract

The utility model discloses a display panel, include: a substrate, the substrate comprising a non-display region, wherein the non-display region comprises at least one thin film transistor, wherein the thin film transistor comprises: the first opening row and the second opening row are respectively arranged on two sides of the first metal layer in an adjacent mode; and the second metal layer comprises a first part and a second part which are respectively arranged at two sides of the first metal layer in an adjacent mode, wherein the first part corresponds to the first opening row, the second part corresponds to the second opening row, the shortest distance from the edge of the first part of the second metal layer to the edge of the first metal layer is a first distance, the shortest distance from the edge of the second part of the second metal layer to the edge of the first metal layer is a second distance, and the second distance is larger than the first distance.

Description

display panel

technical field

The utility model relates to a thin film transistor and a display panel thereof, in particular to a thin film transistor with a metal layer and a display panel thereof.

Background technique

Liquid crystal display devices have been widely used in display elements of various products in recent years. The liquid crystal display device utilizes the property that liquid crystal molecules have different polarization or refraction effects on light in different alignment states to control the amount of light passing through, thereby enabling the liquid crystal display device to generate images. The traditional Twisted Nematic (TN) liquid crystal display device has very good transmission characteristics, but due to the influence of liquid crystal molecular structure and optical properties, its viewing angle is very narrow.

In order to solve this problem, the industry has recently developed other types of liquid crystal display devices with wide viewing angles, such as In-Plane Switching (IPS) liquid crystal display devices and Fringe-Field Switching (FFS) liquid crystal display devices. A liquid crystal display device having a wide viewing angle, such as a display device. However, the above-mentioned display devices may still have problems of poor durability and short product life.

Therefore, the industry urgently needs a display device that can further improve durability and product life.

Utility model content

In order to solve the above problems, the utility model provides a display panel, including: a substrate, including a display area and a non-display area adjacent to the display area, wherein the non-display area includes at least one thin film transistor, wherein the thin film transistor includes: a semiconductor layer, set On the substrate; the first insulating layer is arranged on the semiconductor layer; the first metal layer is arranged on the first insulating layer; the second insulating layer is arranged on the first metal layer; the first opening row (via hole series) and the second row of openings are respectively arranged on both sides of the first metal layer, the first row of openings includes a plurality of first openings, and the second row of openings includes a plurality of second openings, and the first openings and the second openings are sequentially Penetrating through the second insulating layer, the first insulating layer and exposing the surface of the semiconductor layer; the second metal layer is arranged on the second insulating layer, wherein the second metal layer includes a first part and a second part, which are respectively arranged on the first metal layer The first part corresponds to the first row of openings, and fills the plurality of first openings to be electrically connected to the semiconductor layer, and the second part corresponds to the second row of openings, and fills the plurality of second openings to electrically connect to the semiconductor layer. The semiconductor layer, wherein the shortest distance from the edge of the first part of the second metal layer to the edge of the first metal layer is the first distance, and the shortest distance from the edge of the second part of the second metal layer to the edge of the first metal layer is the first distance Two distances, the second distance is greater than the first distance.

The second distance is about 0.1 μm to 1.0 μm larger than the first distance.

The shortest distance from the edge of the first portion of the second metal layer to the edge of the second portion is a third distance, and the third distance is less than the length of the first row of openings.

The first metal layer has an arc-shaped end.

The width of the part of the second metal layer corresponding to the first opening is smaller than the width of the part of the second metal layer corresponding between the two first openings.

The plurality of first openings are arranged equidistantly from each other, and the plurality of second openings are arranged equidistantly from each other.

The first metal layer includes a first branch portion and a second branch portion, wherein the first branch portion is adjacent to the first portion of the second metal layer, and the second branch portion is adjacent to the second branch portion of the second metal layer two parts.

The second branch portion of the first metal layer has an arc-shaped end.

The first branch portion and the second branch portion of the first metal layer are electrically connected to each other.

The shortest distance from the first branch to the first portion of the second metal layer is the first distance, and the shortest distance from the second branch to the second portion of the second metal layer is the second distance.

The display panel further includes a third opening row, located between the first branch portion and the second branch portion of the first metal layer, and the third opening row includes a plurality of third openings, the plurality of third openings The opening is defined by the sidewall of the first insulating layer, the sidewall of the second insulating layer and the surface of the semiconductor layer; the second metal layer further includes a third part, and the third part passes through the plurality of third The opening is electrically connected to the semiconductor layer, wherein the shortest distance from the edge of the third portion to an edge of the first branch portion is a third distance, and the distance from the edge of the third portion to an edge of the second branch portion is The shortest distance is a fourth distance, and the third distance is greater than the fourth distance.

The third distance is about 0.1 μm to 1.0 μm larger than the fourth distance.

The second distance is greater than the fourth distance, and the third distance is greater than the first distance.

The shortest distance from the edge of the second portion of the second metal layer to the edge of the third portion is a fifth distance, and the fifth distance is smaller than the length of the third opening row.

The width of the part of the second metal layer corresponding to the third opening is smaller than the width of the part of the second metal layer corresponding to the part between the two third openings.

The utility model also provides a display panel, which includes: a color filter substrate, which is arranged opposite to the substrate; and a liquid crystal layer, which is arranged between the substrate and the color filter substrate.

The display panel also includes: an upper substrate; an organic light-emitting layer located between the substrate and the upper substrate.

The utility model has the advantage that the distance from the source to the gate of the thin film transistor in the non-display area is set to be different from the distance from the drain to the gate, so the resistance of the device can be increased and the amount of current can be reduced, so that the device generates The temperature is lowered and the hot carrier effect is reduced, so the durability and product life of the display device can be improved.

In order to make the features and advantages of the present invention more comprehensible, preferred embodiments are specifically listed below, together with the accompanying drawings, which are described in detail as follows.

Description of drawings

Fig. 1 is the top view of the thin film transistor substrate of the utility model embodiment;

FIG. 2A is a top view of an active element disposed in a non-display area according to an embodiment of the present invention;

Figure 2B is a cross-sectional view drawn along line 2B-2B of Figure 2A;

Fig. 3 is a top view of an active element disposed in a non-display area according to another embodiment of the present invention;

FIG. 4A is a top view of an active element disposed in a non-display area according to another embodiment of the present invention;

Figure 4B is a cross-sectional view drawn along the line segment 4B-4B of Figure 4A;

5 is a cross-sectional view of a display panel according to an embodiment of the present invention;

FIG. 6 is a cross-sectional view of a display device according to an embodiment of the present invention.

Symbol Description

10 thin film transistor substrate;

20 substrates;

30 display area;

40 non-display area;

50 subpixels;

50C sub-pixel column;

50R sub-pixel columns;

60 gate drive circuit;

70 source drive circuit;

80 lines;

90 lines;

100 active components;

100A active components;

100B active components;

200 active components;

202 substrate;

204 buffer layer;

206 semiconductor layer;

206S surface;

208 first insulating layer;

210 first metal layer;

210E edge;

212 second insulating layer;

214 first opening;

214S The first open row;

216 second opening;

216S second open row;

218 second metal layer;

218A Part I;

218AE edge;

218B Part II;

218BE edge;

300 active components;

306 semiconductor layer;

310 first metal layer;

310A first branch;

310B second branch;

314 first opening;

314S The first open row;

316 second opening;

316S second open row;

318 second metal layer;

318A Part I;

318B Part II;

400 active components;

402 substrate;

404 buffer layer;

406 semiconductor layer;

406S surface;

408 first insulating layer;

410 first metal layer;

410A First branch;

410AE edge;

410B second branch;

410BE edge;

412 second insulating layer;

414 first opening;

414S The first open row;

416 second opening;

416S second open row;

417 third opening;

417S The third open row;

418 second metal layer;

418A Part I;

418AE edge;

418B Part II;

418BE edge;

418C Part III;

418CE edge;

500 display panels;

502 Thin film transistor substrate;

504 color filter substrate;

506 liquid crystal layer;

600 display devices;

602 backlight module;

A1 direction;

A2 direction;

E1 curved end;

E2 curved end;

E3 curved end;

D1 distance;

D2 distance;

D3 distance;

D4 distance;

D5 distance;

D6 distance;

D7 distance;

L2 length;

L3 length;

L4 length;

W1 width;

W2 width;

W3 width;

W4 width;

CH2 channel;

2B-2B line segment;

4B-4B line segment.

Detailed ways

The thin film transistor and its display panel of the present invention will be described in detail below. It should be understood that the following descriptions provide many different embodiments or examples for implementing different aspects of the present invention. The following specific components and arrangements are used to describe the utility model simply. Certainly, these are only for example rather than limitation of the present invention. Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the present utility model, and do not represent any relationship between the different embodiments and/or structures discussed. Furthermore, when it is mentioned that a first material layer is located on or above a second material layer, it includes the situation that the first material layer is in direct contact with the second material layer. Alternatively, there may be one or more layers of other material interspersed, in which case there may be no direct contact between the first material layer and the second material layer.

It must be understood that elements not specifically described or illustrated may exist in various forms well known to those skilled in the art. In addition, when a layer is "on" other layers or substrates, it may mean that it is "directly" on other layers or substrates, or that a certain layer is on other layers or substrates, or that it is interposed between other layers or substrates. other layers.

In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element to another element in the drawings. It will be appreciated that if the illustrated device is turned over so that it is upside down, elements described as being on the "lower" side will become elements on the "higher" side.

Here, the terms "about" and "approximately" usually mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The given quantity here is an approximate quantity, which means that the meaning of "about" and "approximately" can still be implied in the absence of specific instructions.

In the embodiment of the present invention, the distance from the source to the gate of the thin film transistor in the non-display area is set to be different from the distance from the drain to the gate, so as to improve the durability and product life of the display device.

First, refer to FIG. 1 , which is a top view of a thin film transistor substrate 10 according to an embodiment of the present invention. As shown in FIG. 1 , the TFT substrate 10 includes a substrate 20 . The substrate 20 can be a transparent substrate, such as a glass substrate, a ceramic substrate, a plastic substrate or any other suitable transparent substrate. And the substrate 20 includes a display area 30 and a non-display area 40 adjacent to the display area 30 . The display area 30 refers to an area in the thin film transistor substrate 10 where pixel displays including transistors are provided, and the transistors may be, for example, thin film transistors. The non-display area 40 refers to other areas in the TFT substrate 10 except the display area 30 . In this embodiment, the non-display area 40 surrounds the display area 30 .

As shown in FIG. 1 , a plurality of sub-pixels 50 are disposed in the display area 30 , and a gate driving circuit 60 and a source driving circuit 70 are disposed in the non-display area 40 . The gate drive circuit 60 is used to provide scan pulse signals to the sub-pixels 50 of the display area 30, and the source drive circuit 70 is used to provide source signals to the sub-pixels 50 of the display area 30, together with the scan pulse signals Each sub-pixel 50 disposed in the display area 30 is controlled to generate an image.

In detail, at least one active element 100 may be disposed in the gate driving circuit 60 and the source driving circuit 70, such as an active element 100A disposed in the gate driving circuit 60 and an active element 100 disposed in the source driving circuit 70. active element 100B. The active device 100 can be a thin film transistor. When displaying an image, the active element 100A provided in the gate driving circuit 60 simultaneously provides a scan pulse signal to a plurality of sub-pixels 50 through the line 80, for example, simultaneously provides a scan pulse signal to all the sub-pixels 50 in the primary pixel row 50R, The active element 100B disposed in the source driving circuit 70 provides source signals to multiple sub-pixels 50 simultaneously through the line 90 , for example, provides source signals to all the sub-pixels 50 in the primary pixel row 50C simultaneously.

Referring to FIG. 2A and FIG. 2B , these two figures illustrate an active device 200 according to an embodiment of the present invention. FIG. 2A is a top view of the active device 200 , and FIG. 2B is a cross-sectional view along line 2B- 2B of FIG. 2A . The active element 200 is disposed on the non-display area of the TFT substrate. More specifically, the active element 200 here can be disposed in the gate driving circuit 60 and/or the source driving circuit 70 of the non-display area 40 of the thin film transistor substrate 10 in FIG. 1 . In one embodiment, the active device 200 can be a thin film transistor.

The active device 200 includes a buffer layer 204 disposed on the substrate 202 , and a semiconductor layer 206 disposed on the buffer layer 204 . The substrate 202 is the substrate 20 shown in FIG. 1 , which can be a transparent substrate, such as a glass substrate, a ceramic substrate, a plastic substrate, or any other suitable transparent substrate. The buffer layer 204 can improve the film quality of the semiconductor layer 206 . The material of the buffer layer 204 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The above-mentioned semiconductor layer 206 may include elemental semiconductors of silicon or germanium with single crystal structure, polycrystalline structure or amorphous structure; amorphous silicon (amorphous silicon), polycrystalline silicon (polycrystalline silicon), indium gallium zinc oxide (Indium gallium zinc oxide), nitride Gallium (GaN), silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide or indium antimonide ) and other compound semiconductors; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP or GaInAsP or other suitable materials and/or combinations thereof.

In addition, the active device 200 also includes a first insulating layer 208 disposed on the semiconductor layer 206, a first metal layer 210 disposed on the first insulating layer 208, and a first metal layer 210 disposed on the first metal layer 210. Two insulating layers 212 .

The first insulating layer 208 is used as a gate dielectric layer, and its material can be silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, or any other suitable dielectric material, or a combination of the above. The material of this high dielectric constant (high-k) dielectric material can be metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, Metal aluminates, zirconosilicates, zircoaluminates. For example, the high-k dielectric material can be LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO _2. HfO ₃ , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr)TiO ₃ (BST), Al ₂ O ₃ , other high dielectric constants of other appropriate materials Dielectric material, or a combination of the above. The gate dielectric layer can be formed by chemical vapor deposition (CVD) or spin coating, such as low pressure chemical vapor deposition (low pressure chemical vapor deposition, LPCVD), low temperature chemical vapor deposition (low temperature chemical vapor deposition, LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma-assisted chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD), atomic layer chemical vapor deposition Atomic layer deposition (ALD) or other commonly used methods.

The first metal layer 210 is used as a gate electrode, and its material may include but not limited to copper, aluminum, molybdenum, tungsten, titanium, tantalum, platinum ( platinum) or hafnium (hafnium). The material of the gate electrode can be formed by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition methods.

The above-mentioned second insulating layer 212 serves as an interlayer dielectric layer between the first metal layer 210 (gate electrode) and the subsequent second metal layer 218 (serving as source and/or drain electrodes), and its material can be silicon oxide , silicon nitride, silicon oxynitride, high-k dielectric material, or any other suitable dielectric material, or a combination thereof. In a preferred embodiment, the second insulating layer 212 has a flat upper surface. The second insulating layer 212 can be formed using the aforementioned chemical vapor deposition (CVD).

Continuing to refer to FIG. 2A and FIG. 2B , the active device 200 further includes a first via hole series 214S and a second via hole series 216S. The first row of openings 214S and the second row of openings 216S are respectively adjacent to the two sides of the first metal layer 210 (or called the two sides of the first branch portion 210 of the first metal layer), and the first row of openings 214S includes a first plurality of openings 214 and a second row of openings 216S includes a second plurality of openings 216 . The first opening 214 and the second opening 216 sequentially penetrate the second insulating layer 212 and the first insulating layer 208 and expose the surface 206S of the semiconductor layer 206 , as shown in FIG. 2B . The first opening 214 and the second opening 216 are defined by the sidewalls of the first insulating layer 208 , the sidewalls of the second insulating layer 212 and the surface 206S of the semiconductor layer 206 . And as shown in FIG. 2A , the plurality of first openings 214 are arranged equidistantly from each other, and the plurality of second openings 216 are also arranged equidistantly from each other.

Continuing to refer to FIG. 2A and FIG. 2B , the active device 200 further includes a second metal layer 218 disposed on the second insulating layer 212 and filling the first opening 214 and the second opening 216 . In detail, the second metal layer 218 includes a first portion 218A and a second portion 218B. The first part 218A and the second part 218B are respectively provided on both sides of the first metal layer 210 (or called the two sides of the first branch part 210 of the first metal layer), and can be respectively used as a source electrode and a drain. pole electrode. For example, in one embodiment, the first portion 218A acts as a source electrode and the second portion 218B acts as a drain electrode. However, in other embodiments, the first portion 218A acts as a drain electrode while the second portion 218B acts as a source electrode. In addition, the semiconductor layer 206 disposed under the second metal layer 210 (serving as a gate electrode) has a channel between the first portion 218A and the second portion 218B (serving as a source electrode and a drain electrode) of the second metal layer 218 CH2, the length of this channel CH2 is length L2.

Continuing to refer to FIG. 2A and FIG. 2B , the first portion 218A of the second metal layer 218 is disposed corresponding to the first opening row 214S, and fills the plurality of first openings 214 to be electrically connected to the semiconductor layer 206 . The second portion 218B of the second metal layer 218 is disposed corresponding to the second opening row 216S, and fills the plurality of second openings 216 to be electrically connected to the semiconductor layer 206 . Specifically, the first portion 218A of the second metal layer 218 covers the sidewalls of the first insulating layer 208 in the first opening 214, the sidewalls of the second insulating layer 212 and the surface 206S of the semiconductor layer 206, and the second portion 218B also covers Covering the sidewalls of the first insulating layer 208 , the sidewalls of the second insulating layer 212 and the surface 206S of the semiconductor layer 206 in the second opening 216 . Moreover, neither the first portion 218A nor the second portion 218B of the second metal layer 218 completely fills the first opening 214 and the second opening 216 . However, it should be noted that, in other embodiments, the first part 218A and the second part 218B of the second metal layer 218 can also completely fill the first opening 214 and the second opening 216, and the scope of the present invention is not limited to The embodiments shown in FIGS. 2A-2B are limited.

2A and 2B, the shortest distance from the edge 218AE of the first portion 218A of the second metal layer 218 to the edge 210E of the first metal layer 210 is the distance D1, and the edge 218BE of the second portion 218B of the second metal layer 218 to The shortest distance of the edge 210E of the first metal layer 210 is the distance D2, and the distance D2 is greater than the distance D1. As shown in FIG. 2B , the distance D2 is longer than the distance D1 is the distance D3 . In other words, the distance D2 is the distance D1 plus the distance D3 (D2=D1+D3).

It should be noted that there is a width difference between the width of the portion of the second metal layer 218 corresponding to the opening (ie, the width W1 and the width W3 ) and the width of the portion between the two openings (ie, the width W2 and the width W4 ). (ie W2-W1 or W4-W3), so the distances D1 and D2 in FIG. 2A and the distances D1 and D2 in FIG. 2B actually have this width difference (ie W2-W1 or W4-W3). However, since the width difference is much smaller than the distances D1 and D2, it is assumed here that the distances D1 and D2 in FIG. 2A are approximately equal to the distances D1 and D2 in FIG. 2B for the convenience of describing the features of this case.

Continuing to refer to FIG. 2A , in this figure, the long axis extending direction of the first metal layer 210 serving as the gate electrode is A1 , and the direction perpendicular to the direction A1 is the direction A2 . The above-mentioned shortest distance D1 refers to the shortest distance from the edge 218AE to the edge 210E in the direction A2. Similarly, the above-mentioned shortest distance D2 refers to the shortest distance from the edge 218BE to the other edge 210E in the direction A2. More specifically, the edge 218AE and the edge 210E are projected onto the substrate 202 , and the shortest distance between the two projections in the direction A2 is the distance D1 . Similarly, the edge 218BE and the edge 210E are projected onto the substrate 202 , and the shortest distance between the two projections in the direction A2 is the distance D2 .

The utility model lengthens the channel CH2 by a distance D3, increases the resistance of the device and reduces the current, so that the temperature generated by the device is reduced, so as to improve the durability and product life of the display device. In implementing the above method, only a distance D3 between the second part 218A and the first metal layer 210 is elongated, while the distance between the first part 218B and the first metal layer 210 remains unchanged, which can further reduce hot carriers. The effect is quite helpful to improve the durability and lifespan of the display device.

The distance D2 is about 0.1 μm to 1.0 μm longer than the distance D1 (that is, the distance D3 ), for example, about 0.2 μm to 0.7 μm longer. It should be noted that if the length difference (that is, the distance D3 ) is too large, for example greater than 1.0 μm, the resistance of the device will be excessively increased and the overall performance of the device will be reduced. However, if the length difference (that is, the distance D3 ) is too small, such as less than 0.1 μm, the current flow of the device cannot be effectively reduced.

Referring to FIG. 2A , the shortest distance between the edge 218AE of the first portion 218A of the second metal layer 218 and the edge 218BE of the second portion 218B is a distance D4 , and the distance D4 is smaller than the length L3 of the first opening row 214S. In detail, the above-mentioned distance D4 refers to the shortest distance from the edge 218AE of the first portion 218A of the second metal layer 218 to the edge 218BE of the second portion 218B in the direction A2. Or in more detail, the edge 218AE and the edge 218BE are projected onto the substrate 202 , and the shortest distance between the two projections in the direction A2 is the distance D4 . The length L3 of the first opening row 214S refers to the maximum distance between the edges of the farthest two first openings 214 in the first opening row 214S in the direction A1 of the long axis of the first metal layer 210 . Similarly, the above-mentioned distance D4 is also smaller than the length L4 of the second opening row 216S. The definition of the length L4 is similar to the above-mentioned length L3, so it will not be repeated here.

In addition, as shown in FIG. 2A, the first metal layer 210 has an arc-shaped end E1, the first portion 218A of the second metal layer 218 has an arc-shaped end E2, and the second portion 218B of the second metal layer 218 also has an arc. Shaped end E3. The arc-shaped end can prevent the static charge from accumulating on the metal tip, which can reduce the probability of the active device 200 being damaged by the static charge.

In addition, the width W1 of the first portion 218A of the second metal layer 218 corresponding to the first opening 214 is smaller than the width W2 of the portion between the two first openings 214 . Similarly, the width W3 of the second portion 218B of the second metal layer 218 corresponding to the second opening 216 is also smaller than the width W4 of the portion between the two second openings 216 . This width change can further evenly distribute the current in the second metal layer 218, so that the lifetime of the device can be further improved.

It should be noted that although the first metal layer used as the gate electrode in the embodiment shown in FIGS. , as shown in the embodiment of FIG. 3 below. Therefore, the embodiments shown in FIGS. 1-2B are for illustration purposes only, and the scope of the present invention is not limited thereto. It should be noted that the same or similar components or film layers in the following text will be denoted by the same or similar symbols, and their materials, manufacturing methods and functions are the same or similar to those described above, so this part will not be repeated in the following text. repeat.

Referring to FIG. 3 , FIG. 3 is a top view of an active element 300 disposed in a non-display area according to another embodiment of the present invention. The difference between the embodiment shown in FIG. 3 and the aforementioned embodiments in FIGS. 2A-2B is that the first metal layer 310 includes a first branch portion 310A and a second branch portion 310B. The first branch portion 310A is adjacent to the first portion 318A of the second metal layer 318 , and the second branch portion 310B is adjacent to the second portion 318B of the second metal layer 318 . And the shortest distance from the first branch portion 310A of the first metal layer 310 to the first portion 318A of the second metal layer 318 is the above distance D1, and the distance from the second branch portion 310B of the first metal layer 310 to the second metal layer 318 The shortest distance of the second portion 318B is the above-mentioned distance D2. In addition, there is no second metal layer 318 between the first branch portion 310A and the second branch portion 310B of the first metal layer 310 . The above-mentioned first metal layer 310 including the first branch portion 310A and the second branch portion 310B can have better control over the channel under it.

It should be noted that although the second metal layer serving as the source and/or drain electrode in the embodiments shown in FIGS. 1-3 above has only two parts, the second metal layer may also have three parts. , as shown in the embodiments of FIG. 4A-FIG. 4B below. Therefore, the embodiments shown in FIGS. 1-3 are for illustration purposes only, and the scope of the present invention is not limited thereto.

Referring to FIGS. 4A-4B , FIG. 4A is a top view of an active element 400 disposed in a non-display area according to another embodiment of the present invention, and FIG. 4B is a cross-sectional view drawn along line 4B-4B of FIG. 4A . The difference between the embodiment shown in FIGS. 4A-4B and the embodiment shown in FIGS. 2A-3 is that the second metal layer 418 of the active element 400 includes a first part 418A, a second part 418B and a third part 418C, and here Active element 400 has three rows of openings.

In detail, the active device 400 can be sequentially provided with a buffer layer 404 , a semiconductor layer 406 , a first insulating layer 408 , a first metal layer 410 , and a second insulating layer 412 on the substrate 402 . The first metal layer 410 includes a first branch portion 410A and a second branch portion 410B, and the first branch portion 410A and the second branch portion 410B are electrically connected to each other, as shown in FIG. 4A .

In addition, the active device 400 further includes a first via hole series 414S, a second via hole series 416S and a third via hole series 417S. The first opening row 414S is adjacent to the first branch portion 410A of the first metal layer 410, the third opening row 417S is adjacent to the first branch portion 410A and the second branch portion 410B, and the second opening The row 416S is disposed adjacent to the outside of the second branch portion 410B of the first metal layer 410 , as shown in FIG. 4A . In addition, the first opening row 414S includes a plurality of first openings 414, the second opening row 416S includes a plurality of second openings 416, and the third opening row 417S includes a plurality of third openings 417. The first openings 414, the second Both the opening 416 and the third opening 417 penetrate through the second insulating layer 412 and the first insulating layer 408 in sequence and expose the surface 406S of the semiconductor layer 406 .

Continuing to refer to FIGS. 4A-4B , the active device 400 further includes a second metal layer 418 disposed on the second insulating layer 412 and filling the first opening 414 , the second opening 416 and the third opening 417 . In detail, the second metal layer 418 includes a first portion 418A, a second portion 418B, and a third portion 418C, which are sequentially disposed corresponding to the first row of openings 414S, the second row of openings 416S, and the third row of openings 417S. And the first part 418A, the second part 418B and the third part 418C of the second metal layer 418 are sequentially filled into the first opening 414 , the second opening 416 and the third opening 417 to be electrically connected to the semiconductor layer 406 .

In this active device 400 , the above-mentioned first metal layer 410 serves as a gate electrode of the active device 400 . The first part 418A and the second part 418B of the second metal layer 418 are used as one of the source electrode or the drain electrode of the active element 400, and the third part 418C of the second metal layer 418 is used as the source electrode or the drain electrode. The other pole electrode. For example, in one embodiment, the first portion 418A and the second portion 418B serve as the source electrode of the active device 400 , while the third portion 418C serves as the drain electrode. However, in other embodiments, the first portion 418A and the second portion 418B serve as the drain electrode of the active device 400 , while the third portion 418C serves as the source electrode.

As shown in FIGS. 4A-4B , the shortest distance from the edge 418AE of the first part 418A of the second metal layer 418 to the edge 410AE of the first branch portion 410A of the first metal layer 410 is the distance D1. The shortest distance from the edge 418CE of the three portions 418C to the edge 410AE of the first branch portion 410A of the first metal layer 410 is a distance D5, which is greater than the distance D1.

Similarly, the shortest distance from the edge 418CE of the third portion 418C of the second metal layer 418 to the edge 410BE of the second branch portion 410B of the first metal layer 410 is the distance D6, and the edge of the second portion 418B of the second metal layer 418 The shortest distance to the edge 410BE of the second branch portion 410B of the first metal layer 410 is a distance D2, the distance D2 is greater than the distance D6, and the distance D5 is greater than the distance D6. The above-mentioned distance D5 is about 0.1 μm to 1.0 μm (that is, the distance D7 ), for example, about 0.2 μm to 0.7 μm, than the distance D1 .

It should be noted that since there is a width difference between the width of the portion of the second metal layer 418 corresponding to the opening and the width of the portion between the two openings, the distances D1, D2, D5 and D6 in FIG. 4A are different from the distances in FIG. 4B D1, D2, D5 and D6 actually also have this width difference. However, since the width difference is much smaller than the distances D1, D2, D5, and D6, it is assumed here that the distances D1, D2, D5, and D6 in FIG. 4A are approximately equal to the distances D1, D2, D5, and D6 in FIG. 4B for convenience of illustration. The characteristics of this case.

In addition, it should be noted that the detailed definitions of the above-mentioned distance D1 and distance D2 are similar to those of the distance D1 and distance D2 in the embodiment shown in FIG. 2A-FIG. 2B , so details are not repeated here.

The utility model lengthens the channel by a distance D7, increases the resistance of the device and reduces the current, so that the temperature generated by the device is reduced, so as to improve the durability and product life of the display device. In implementing the above method, only a distance D7 between the third portion 418C of the second metal layer 418 and the first branch portion 410A of the first metal layer 410 is elongated, while the first portion 418A of the first metal layer 410 is connected to the first branch portion 410A. The distance between the first branch portions 410A of the metal layer remains unchanged, which can further reduce the hot carrier effect, which is quite helpful to improve the durability and lifespan of the display device. Similarly, only a distance D7 between the second part 418B of the second metal layer 418 and the second branch part 410B of the first metal layer 410 is elongated, while the third part 418C of the second metal layer 418 and the first metal layer 410 The distance between the second branch portions 410B remains unchanged, which can also achieve the effect of reducing the hot carrier effect.

In addition, the source-gate capacitance in the active device 400 is preferably equal to the drain-gate capacitance. For example, in one embodiment, the first portion 418A and the second portion 418B of the second metal layer 418 serve as a source electrode, and the third portion 418C serves as a drain electrode. The first metal layer 410 including the first branch portion 410A and the second branch portion 410B serves as the gate electrode.

There is a first source-gate capacitance between the first part 418A (as a source electrode) and the first branch part 410A (as a gate electrode), and the second part 418B (as a source electrode) and the second There is a second source-gate capacitance between the branch portions 410B (serving as gate electrodes). The third portion 418C of the second metal layer 418 (serving as a drain electrode) and the first branch portion 410A and the second branch portion 410B (serving as a gate electrode) respectively have a first drain-gate capacitance and a first drain-gate capacitance. Two drain-gate capacitors. The sum of the first source-gate capacitance and the second source-gate capacitance is preferably equal to the sum of the first drain-gate capacitance and the second drain-gate capacitance.

Equalizing the source-gate capacitance and the drain-gate capacitance in the active device 400 can improve device performance. In detail, since the source and the drain are only defined by the current direction between the electrodes, the first part 418A, the second part 418B, and the third part 418C of the second metal layer 418 can all be used as the source or the drain. . Therefore, equating the source-gate capacitance and the drain-gate capacitance in the active device 400 allows the first portion 418A, the second portion 418B, and the third portion 418C to switch between the source and the drain. There will be no error caused by different capacitance values, and the performance of the device can be improved.

In addition, the present invention also provides a display panel including the thin film transistor substrate of the above-mentioned active elements. Refer to FIG. 5 , which is a cross-sectional view of a display panel 500 according to an embodiment of the present invention. As shown in FIG. 5 , the display panel 500 includes a TFT substrate 502 , an upper substrate 504 , and a display medium layer 506 disposed between the TFT substrate 502 and the upper substrate 504 . In the embodiment of the present invention, the display panel 500 is a liquid crystal display panel, the upper substrate 504 is a color filter substrate, and the display medium layer 506 is a liquid crystal layer. In another embodiment of the present invention, the display panel 500 is an organic light emitting display panel, the upper substrate 504 is a transparent substrate, and the display medium layer 506 is an organic light emitting layer. In yet another embodiment of the present invention, the display panel 500 is an organic light emitting display panel, the upper substrate 504 is a color filter substrate, and the display medium layer 506 is an organic light emitting layer.

The thin film transistor substrate 502 can be provided with the active element 200 in the embodiment of FIG. 2A and FIG. 2B , the active element 300 in the embodiment of FIG. 3 , or the embodiment of FIGS. 4A-4B in the non-display area. The active element 400. The color filter substrate 504 may include a transparent substrate and a color filter layer (not shown) disposed on the transparent substrate. The color filter layer can be a red filter layer, a green filter layer, a blue filter layer, or any other suitable color filter layer. The liquid crystal layer 506 can be nematic liquid crystal (nematic), smectic liquid crystal (smectic), cholesteric liquid crystal (cholesteric), blue phase liquid crystal (Blue phase) or any other suitable liquid crystal material.

Since the active elements 200, 300, or 400 in the thin film transistor substrate 502 can increase the resistance of the device and reduce the amount of current, the temperature generated by the device can be reduced, and the hot carrier effect can be reduced, so the display panel 500 can have better durability. performance and product life.

In addition, the present invention also provides a display device manufactured with the display panel. Referring to FIG. 6 , this figure is a cross-sectional view of a display device 600 according to an embodiment of the present invention. As shown in FIG. 6 , the display device 600 includes a backlight module 602 and a display panel 500 disposed on the backlight module 602 . The backlight module 602 can be an LED backlight module or any other suitable backlight module. It should be noted that if the display panel 500 is an organic light emitting display panel, the backlight module can also be omitted. Since the active elements in the display panel 500 can increase the resistance of the device and reduce the current flow, the temperature generated by the device can be reduced, and the hot carrier effect can be reduced, so the display device 600 can have better durability and product life.

To sum up, in the embodiment of the present invention, the distance from the source to the gate of the thin film transistor in the non-display area is set to be different from the distance from the drain to the gate, so the resistance of the device can be increased and the current flow can be reduced, so that The temperature generated by the device is reduced, and the hot carrier effect is reduced, so the durability and product life of the display device can be improved.

Claims (17)

1. a display panel, is characterized in that, this display panel comprises:

Substrate, comprises a non-display area of a viewing area and this viewing area adjacent;

Thin film transistor (TFT), is positioned on this non-display area of this substrate;

Wherein this thin film transistor (TFT) comprises:

Semiconductor layer, is positioned on this substrate;

First insulation course, is positioned on this semiconductor layer;

The first metal layer, is positioned on this first insulation course;

Second insulation course, is positioned on this first insulation course;

First opening row and the second opening row, be adjacent to the both sides of this first metal layer respectively, multiple first opening is drawn together in this first opening package, and multiple second opening is drawn together in this second opening package, and the plurality of first opening and the plurality of second opening are with the sidewall of this first insulation course, the sidewall of this second insulation course and the surface definition of this semiconductor layer;

Second metal level, be positioned on this second insulation course, wherein this second metal level comprises Part I and Part II, wherein this Part I by the plurality of first opening to be electrically connected to this semiconductor layer, and this Part II by the plurality of second opening to be electrically connected to this semiconductor layer

Wherein the bee-line at edge a to edge of this first metal layer of this Part I is one first distance, and the bee-line at edge to another edge of this first metal layer of this Part II is a second distance, and this second distance is greater than this first distance.

2. display panel as claimed in claim 1, is characterized in that, this second distance than this first apart from about 0.1 μm to 1.0 μm between.

3. display panel as claimed in claim 1, it is characterized in that, the bee-line at edge to the edge of this Part II of this Part I of this second metal level is one the 3rd distance, and the 3rd distance is less than the length of this first opening row.

4. display panel as claimed in claim 1, it is characterized in that, this first metal layer has a curved end.

5. display panel as claimed in claim 1, is characterized in that, this second metal level is to the width of part of the first opening being less than the width of the part between corresponding two these the first openings of this second metal level.

6. display panel as claimed in claim 1, is characterized in that, the plurality of first opening equidistant arrangement each other, the plurality of second opening equidistant arrangement each other.

7. display panel as claimed in claim 1, it is characterized in that, this the first metal layer comprises the first branch and the second branch, wherein this Part I of this first branch this second metal level contiguous, and this Part II of this second branch this second metal level contiguous.

8. display panel as claimed in claim 7, it is characterized in that, this second branch of this first metal layer has a curved end.

9. display panel as claimed in claim 7, it is characterized in that, this first branch and this second branch of this first metal layer are electrically connected to each other.

10. display panel as claimed in claim 7, it is characterized in that, this first branch is this first distance to the bee-line of this Part I of this second metal level, and this second branch to the bee-line of this Part II of this second metal level is this second distance.

11. display panels as claimed in claim 10, it is characterized in that, this display panel also comprises the 3rd opening row, between this first branch and this second branch of this first metal layer, and multiple 3rd opening is drawn together in the 3rd opening package, the plurality of 3rd opening is with the sidewall of this first insulation course, the sidewall of this second insulation course and the surface definition of this semiconductor layer;

This second metal level also comprises Part III, and this Part III by the plurality of 3rd opening to be electrically connected to this semiconductor layer,

Wherein the bee-line at edge a to edge of this first branch of this Part III is one the 3rd distance, and the bee-line at edge a to edge of this second branch of this Part III is one the 4th distance, and the 3rd distance is greater than the 4th distance.

12. display panels as claimed in claim 11, is characterized in that, the 3rd distance than the 4th apart from about 0.1 μm to 1.0 μm between.

13. display panels as claimed in claim 11, it is characterized in that, this second distance is greater than the 4th distance, and the 3rd distance is greater than this first distance.

14. display panels as claimed in claim 11, is characterized in that, the bee-line at edge to the edge of this Part III of this Part II of this second metal level is one the 5th distance, and the 5th distance is less than the length of the 3rd opening row.

15. display panels as claimed in claim 11, is characterized in that, this second metal level is to the width of part of the 3rd opening being less than the width of the part between corresponding two the 3rd openings of this second metal level.

16. display panels as claimed in claim 1, it is characterized in that, this display panel also comprises:

Colored filter substrate;

Liquid crystal layer, between this substrate and this colored filter substrate.

17. display panels as claimed in claim 1, it is characterized in that, this display panel also comprises: upper substrate;

Organic luminous layer, between this substrate and this upper substrate.