CN204359405U - The flow velocity simulation system of ultrasonic flow meter - Google Patents

Abstract

A flow velocity simulation system of an ultrasonic flowmeter, comprising an FPGA circuit, a touch screen, a DA converter, an output control circuit, a channel switching circuit, a signal threshold comparison circuit and two transducers, the FPGA circuit is connected to the output control circuit and the channel respectively The switching circuit is connected to control the on or off of the output control circuit and the channel switching circuit respectively, and the ultrasonic flowmeter to be tested is used to send driving signals to the two transducers respectively, and the two transducers are used for Respectively receive the driving signals of the ultrasonic flowmeter to be tested, and transmit them to the signal threshold comparison circuit through the channel switching circuit respectively, and the FPGA circuit is used to receive the start signal of the signal threshold comparison circuit, generate timing time, and output control signals at regular intervals to control the DA The converter outputs the ultrasonic pulse waveform, which is transmitted to the two transducers respectively through the output control circuit.

Description

Flow Velocity Simulation System of Ultrasonic Flowmeter

technical field

The utility model relates to the testing field of ultrasonic flowmeters, in particular to a flow velocity simulation system of ultrasonic flowmeters.

Background technique

Because the ultrasonic flowmeter does not touch the measured medium, the measurement accuracy is less affected by the medium temperature and pressure parameters, so it is widely used.

The applicant company used the time difference method to measure the fluid flow velocity in the development process of the ultrasonic flowmeter before. The basic principle is to measure the time difference of the ultrasonic pulse in the downstream flow and the upstream flow to reflect the flow velocity, so as to measure the flow rate. Therefore, in the development of the previous ultrasonic flowmeter, in order to obtain the information of the flow rate, the ultrasonic sensor must be installed on the actual pipeline, and the fluid with a certain flow rate must be passed through to verify whether the pulse transceiver circuit of the relevant ultrasonic flowmeter is normal and whether the measurement result is linear. and other relevant information. Functional testing like this cannot be done without the availability of piping and fluids. Therefore, it is necessary to design a circuit system that simulates the sending and receiving waveform of the ultrasonic sensor, so that the parameter verification of the ultrasonic flowmeter can also verify whether the ultrasonic pulse sending and receiving circuit is normal and whether the linearity of the flowmeter is in the absence of actual pipelines and fluids. within a reasonable range.

Invention content

The utility model aims at the deficiencies of the prior art, and provides a flow velocity simulation system of an ultrasonic flowmeter. This system can effectively solve the drawback that the functional verification of the ultrasonic flowmeter must be carried out only when there are pipelines and a fluid with a certain flow velocity. The function verification of the ultrasonic flowmeter can also be realized without pipeline fluid. The utility model is suitable for simulating the signal sending and receiving mode of the ultrasonic flowmeter to realize flow velocity simulation and linearity analysis without actual pipeline fluid.

The technical scheme adopted by the utility model to solve the above technical problems is: a flow velocity simulation system of an ultrasonic flowmeter, including an FPGA circuit, a touch screen, a DA converter, an output control circuit, a channel switching circuit, a signal threshold comparison circuit and two switching circuits. The FPGA circuit is connected with the output control circuit and the channel switching circuit respectively, and is used to respectively control the connection or disconnection of the output control circuit and the channel switching circuit. The FPGA circuit is connected with the touch screen through the RS485 interface, and the FPGA The circuit is connected to the ultrasonic flowmeter to be tested through the RS232 interface, and the ultrasonic flowmeter to be tested is used to send driving signals to two transducers respectively, and the two transducers are used to respectively receive the driving signals of the ultrasonic flowmeter to be tested , and respectively passed to the signal threshold comparison circuit through the channel switching circuit, the signal threshold comparison circuit is used to compare the driving voltage of the driving transducer of the ultrasonic flowmeter to be tested with the set threshold, and output the start signal to the FPGA circuit, The FPGA circuit is used to receive the starting signal of the signal threshold comparison circuit, generate timing time, output the control signal regularly, control the DA converter to output the ultrasonic pulse waveform, and transmit it to the two transducers respectively through the output control circuit.

The FPGA circuit adopts an FPGA chip whose model is EP4CE10.

The DA converter adopts a digital-to-analog converter whose model is AD9760AR.

The output control circuit adopts an analog switch chip whose model is ADG1421.

The signal threshold comparison circuit includes an operational amplifier U12A, an operational amplifier U14B and several resistors and capacitors, the non-inverting input terminal of the operational amplifier U14B is connected with the output terminal of the channel switching circuit through the 28th resistor R28, and the inverting input terminal of the operational amplifier U14B The input terminals are respectively connected to one end of the 26th resistor R26, one end of the 27th resistor R27, and one end of the 53rd capacitor C53, the other end of the 26th resistor R26 is grounded, the other end of the 27th resistor R27, the 53rd capacitor C53 The other end of each capacitor C53 is connected to the output terminal of the operational amplifier U14B, the output terminal of the operational amplifier U14B is connected to the non-inverting input terminal of the operational amplifier U12A through the 29th resistor R29, and the inverting input terminal of the operational amplifier U12A is respectively connected to the resistor RA1 One end of the resistor RA2 is connected to one end of the resistor RA2, the other end of the resistor RA1 is connected to a voltage of 1.2V, the other end of the resistor RA2 is grounded, and the output end of the operational amplifier U12A is connected to the FPGA circuit.

The channel switching circuit adopts an analog switch chip whose model is ADG1421.

The utility model adopts the beneficial effect of the above-mentioned technical solution: because the flow velocity simulation system of the ultrasonic flowmeter of the utility model includes an FPGA circuit, a touch screen, a DA converter, an output control circuit, a channel switching circuit, a signal threshold comparison circuit and two The transducer, the FPGA circuit is connected with the output control circuit and the channel switching circuit respectively, and is used to control the connection or disconnection of the output control circuit and the channel switching circuit respectively, and the FPGA circuit is connected with the touch screen through the RS485 interface, and the The FPGA circuit is connected to the ultrasonic flowmeter to be tested through the RS232 interface, and the ultrasonic flowmeter to be tested is used to send driving signals to two transducers respectively, and the two transducers are used to receive the drive of the ultrasonic flowmeter to be tested respectively signal, and respectively pass the channel switching circuit to the signal threshold comparison circuit, the signal threshold comparison circuit is used to compare the drive voltage of the drive transducer of the ultrasonic flowmeter to be tested with the set threshold, and output the start signal to the FPGA circuit , the FPGA circuit is used to receive the starting signal of the signal threshold comparison circuit, generate a timing time, output a control signal regularly, control the DA converter to output the ultrasonic pulse waveform, and transmit it to the two transducers respectively through the output control circuit. This system simulates the transmitting and receiving circuit of ultrasonic pulse and the parameter setting system of ultrasonic flowmeter. In the absence of pipelines and fluids, through the ingenious combination of the parameter setting system mainly realized by the touch screen and the analog circuit of ultrasonic pulse transmitting and receiving, the ultrasonic flow rate can also be verified. Check whether the function of the transmitter and receiver circuit is normal, and whether the linearity is within a reasonable range.

This system can effectively solve the disadvantage that the function verification of ultrasonic flowmeter must be carried out under the condition of pipeline and fluid with a certain flow rate, so that the function verification of ultrasonic flowmeter can also be realized without pipeline fluid.

Description of drawings

Fig. 1 is the circuit diagram of the utility model;

Fig. 2 is the circuit diagram of DA converter of the present utility model, output control circuit;

Fig. 3 is a circuit diagram of a signal threshold comparison circuit and a channel switching circuit of the present invention;

Fig. 4 is the method flowchart of the present utility model;

Figure 5 is a schematic diagram of flow rate measurement by differential method.

Detailed ways

Below in conjunction with accompanying drawing and embodiment the utility model is further described:

Referring to Figures 1 to 5, a flow velocity simulation system of an ultrasonic flowmeter includes an FPGA circuit, a touch screen, a DA converter, an output control circuit, a channel switching circuit, a signal threshold comparison circuit and two transducers, the FPGA circuit Connect with the output control circuit and the channel switching circuit respectively, and are used to control the connection or disconnection of the output control circuit and the channel switching circuit respectively. The FPGA circuit is connected with the touch screen through the RS485 interface, and the FPGA circuit is connected with the test device through the RS232 interface. The ultrasonic flowmeter is connected, and the ultrasonic flowmeter to be tested is used to send driving signals to two transducers respectively, and the two transducers are used to respectively receive the driving signals of the ultrasonic flowmeter to be tested, and pass through the channel switching circuit respectively Passed to the signal threshold comparison circuit, the signal threshold comparison circuit is used to compare the drive voltage of the drive transducer of the ultrasonic flowmeter to be tested with the set threshold, and output the start signal to the FPGA circuit, and the FPGA circuit is used to receive The start signal of the signal threshold comparison circuit generates a timing time, outputs a control signal at a timing, controls the DA converter to output an ultrasonic pulse waveform, and transmits it to two transducers respectively through the output control circuit.

As shown in Figure 1, the touch screen is mainly used to set parameters, such as ultrasonic velocity, pipe diameter, installation angle, etc. At the same time, the verification results and linearity information are also displayed on the touch screen; FPGA is the core device of this patent, used to receive transducers Signal, generate precise timing, control DA output ultrasonic pulse waveform and channel switching, etc. The signal threshold comparison circuit compares the set threshold with the voltage of the driving transducer of the ultrasonic flowmeter to be tested. If the threshold is exceeded, the start signal is output, and the FPGA is notified to start timing immediately and send an ultrasonic pulse waveform.

The function of setting the trigger circuit between the FPGA and the transducer is that the output signal amplitude of the ultrasonic flowmeter is very small (this circuit is 10 millivolts), and the threshold value comparison is to output a high level to trigger the FPGA to reduce the delay time. If it is not set, the output signal of the flowmeter will be detected by the FPGA at a higher level (above 2.0V), and the time delay will be large.

The specific circuit description is as follows:

The FPGA circuit adopts an FPGA chip whose model is EP4CE10. The DA converter adopts a digital-to-analog converter whose model is AD9760AR. The DACLK pin of the digital-to-analog converter is the 32M HZ sine wave clock signal obtained by the FPGA through the frequency division of the internal phase-locked loop. The output control circuit adopts an analog switch chip whose model is ADG1421. The channel switching circuit adopts an analog switch chip whose model is ADG1421.

The signal threshold comparison circuit includes an operational amplifier U12A, an operational amplifier U14B and several resistors and capacitors, the non-inverting input terminal of the operational amplifier U14B is connected with the output terminal of the channel switching circuit through the 28th resistor R28, and the inverting input terminal of the operational amplifier U14B The input terminals are respectively connected to one end of the 26th resistor R26, one end of the 27th resistor R27, and one end of the 53rd capacitor C53, the other end of the 26th resistor R26 is grounded, the other end of the 27th resistor R27, the 53rd capacitor C53 The other end of each capacitor C53 is connected to the output terminal of the operational amplifier U14B, the output terminal of the operational amplifier U14B is connected to the non-inverting input terminal of the operational amplifier U12A through the 29th resistor R29, and the inverting input terminal of the operational amplifier U12A is respectively connected to the resistor RA1 One end of the resistor RA2 is connected to one end of the resistor RA2, the other end of the resistor RA1 is connected to a voltage of 1.2V, the other end of the resistor RA2 is grounded, and the output end of the operational amplifier U12A is connected to the FPGA circuit.

Referring to Fig. 4, a flow velocity simulation method of an ultrasonic flowmeter adopts the flow velocity simulation system of the above-mentioned ultrasonic flowmeter, including the following steps:

1) Pre-set the simulation parameters on the touch screen, including the pipe diameter D, the angle between the two ultrasonic transducers and the horizontal direction of the pipe , range, ultrasonic velocity c, determine a plurality of test points for testing linearity according to the set range, the fluid flow velocity v of each test point corresponds to each percentage of the range, and the first transducer of the two transducers The time from when the transducer starts to send a pulse to when the second transducer receives the pulse signal is defined as t1, and the time from when the second transducer sends a pulse to when the first transducer receives the pulse signal is defined as t2, and the difference between t1 and t2 is defined as is ⊿t, after setting the simulation parameters on the touch screen, the FPGA calculates the t1 and t2 values corresponding to multiple different range percentage points through formulas 1, 2 and 3 according to the set simulation parameters, among which, formula 1 is , formula 2 is , formula 3 is .

In this embodiment, 5 test points are set according to the range, and the fluid velocity v of the 5 test points corresponds to 10%, 30%, 60%, 90%, and 100% of the range. When the set range is 10m/S, the first detection point calculates t1 and t2 according to the fluid velocity v of 1m/S, the second detection point calculates t1 and t2 according to the fluid velocity v of 3m/S, and the third The detection point calculates t1 and t2 according to the fluid flow velocity of 6m/S, the fourth detection point calculates t1 and t2 according to the fluid flow velocity of 9m/S, and the fifth detection point calculates t1 and t2 according to the fluid flow velocity of 10m/S. The velocity c of the ultrasonic wave in the fluid is relatively fixed, and it is treated as a constant in the present invention. The present invention uses the following formulas 1, 2, and 3 to measure the velocity of the fluid in the pipeline. Formulas 1, 2, and 3 only calculate the actual flow velocity of the fluid. After the range, that is, the maximum flow velocity is determined, the ultrasonic velocity is known, and the pipe diameter and installation angle are also set, the fluid flow velocity v in the pipeline is only related to t1 and t2. Different flow velocities Corresponding to different differences between t1 and t2, the test point with a large percentage corresponds to a large difference between t1 and t2.

2) Start the test, the FPGA circuit notifies the ultrasonic flowmeter that the test process starts through the RS232 interface, the ultrasonic flowmeter first sends a driving pulse on the first transducer, and the FPGA circuit determines that after receiving the ultrasonic flowmeter emission pulse through the signal threshold comparison circuit, The FPGA circuit starts timing immediately. After timing t1, the FPGA circuit controls the DA converter to output the analog receiving signal waveform to the second transducer. The ultrasonic flowmeter measures the time interval T1 from sending the driving pulse to receiving the analog receiving signal waveform, and then The ultrasonic flowmeter sends a driving pulse on the second transducer, and the FPGA circuit determines through the signal threshold comparison circuit that after receiving the transmitted pulse of the ultrasonic flowmeter, the FPGA circuit immediately starts timing. After timing t2, the FPGA circuit controls the DA converter to the second transducer. A transducer outputs an analog receiving signal waveform. The ultrasonic flowmeter measures the time interval T2 from sending the driving pulse to receiving the analog receiving signal waveform. The ultrasonic flowmeter calculates the flow velocity V according to the measured time interval T1 and T2, and The flow velocity V is sent to the FPGA circuit, and the FPGA circuit can judge whether the ultrasonic flowmeter's work sending and receiving signal function is normal according to the flow velocity V, and send it to the touch screen for display;

The analog receiving signal waveform is a series of sine wave envelopes whose peaks gradually increase to the highest value and then decrease. In this system, FPGA and DA converter are needed to simulate this waveform as the echo receiving signal of the ultrasonic flowmeter to be tested. The driving pulses are 6 continuous sine waves with a frequency of 1Mhz, which are used to simulate the sine wave envelope of a certain voltage peak generated by the transducer after receiving the ultrasonic pulse excitation.

3) According to step 2), calculate the flow velocity corresponding to multiple test points, and judge the linearity.

Linearity is a straight line based on the flow velocity test values of 10% of the range and 100% of the point. Taking the range of 30m/S as an example, it is assumed that the flow velocity simulator sends 10% of the range according to formulas 1, 2, and 3 (theoretical value 3m/S The ⊿t signal of S) is sent to the ultrasonic flowmeter, and the measured value of the ultrasonic flowmeter is assumed to be 3.2m/S; it is also assumed that the flow velocity simulator sends ⊿ of the 100% range point (theoretical value 30m/S) according to formulas 1, 2, and 3 The t signal is sent to the ultrasonic flowmeter, and the actual measured value of the ultrasonic flowmeter is assumed to be 29m/S, then according to the above two measured values, the measured value of the 30% (9m/S) point should theoretically be 3.2+(29-3.2)*(30 %-10%)=8.36m/S. When the ultrasonic flow velocity simulator sends out the ⊿t signal corresponding to the 30% range test point, the actual measured value of the ultrasonic flowmeter is 8.86, then the linear deviation of the changed point is (8.86- 8.36)/29=0.017 or 1.7%. In the same way, the linear deviation of the 60% and 90% points can be obtained.

In this method, the time-difference method measurement principle shown in Figure 5 is adopted. Figure 5 shows a schematic diagram of the ultrasonic flowmeter differential method for measuring flow velocity, starting from the first transducer to send pulses to the second transducer receiving pulse signals The time of t1 is t1, and the time from the second transducer sending the pulse to the first transducer receiving the pulse signal is t2. The difference between t1 and t2 is ⊿t, and its relationship with the fluid velocity in the pipeline is shown in formula 1:

(1)

(2)

(3)

In the formula, c is the speed of ultrasonic waves in the fluid, D is the diameter of the pipe, is the angle between the two ultrasonic transducers and the horizontal direction of the pipeline. It can be seen from Equation 1 that when the propagation velocity of ultrasonic waves in a stationary fluid can be considered constant, the fluid flow velocity is proportional to the time difference ⊿t, and the flow velocity can be obtained by measuring ⊿t, and then the flow rate can be obtained.

The principle of pulse simulation and function test of the present invention adopts the schematic diagram shown in FIG. 1 . The first transducer and the second transducer are not real sensors, their sending signals are generated by the flowmeter, and the receiving signals are simulated by this flow rate simulator. After setting the parameters of the simulated pipeline flow (such as pipeline diameter, ultrasonic velocity, installation angle, etc., range), after determining the above parameters, the flow rate simulation system can be determined in 5 different range percentages after calculation of formulas 1, 2, and 3. Points (10%, 30%, 60%, 90%, 100%) correspond to the values of t1 and t2, and the FPGA determines through the threshold trigger circuit that after receiving the transmitted pulse of the ultrasonic flowmeter, the FPGA controls the DA converter with the values of t1 and t2 respectively. The time interval outputs the analog receiving signal waveform on the corresponding transducer. Press the start button on the touch screen to start the test process. The FPGA notifies the ultrasonic flowmeter to start the test process through the RS232 interface. The ultrasonic flowmeter first sends out a driving waveform on the first transducer. The driving waveform is 6 continuous sine waves with a frequency of 1Mhz and an amplitude of about 4V. The simulation is the transducer The sine wave envelope of a certain voltage peak generated by the transducer after receiving the ultrasonic pulse excitation. Figure 3 shows the sine wave envelope actually generated by the transducer after receiving the ultrasonic pulse. The flow velocity simulator simulates the waveform through the DA converter When the threshold is greater than the threshold, the threshold is set so that when the flowmeter sends a drive pulse greater than 10 millivolts, the threshold detection circuit outputs a high level to trigger the FPGA to start timing t1, and when the timing t1 arrives, the FPGA immediately drives the DA converter to output the output shown in Figure 3 Analog waveform, the analog waveform is a series of sine wave envelopes whose peak value gradually increases to the highest value and then decreases. Generally, the peak voltage of the highest point of the liquid ultrasonic receiving signal is about 500 millivolts. The flowmeter in this example is at the second A sine wave is used as the time measurement point. Output to the second transducer through the channel control as the flowmeter receiving signal. If the ultrasonic flowmeter transceiver circuit works normally, it can be concluded that the first transducer sends the pulse and the second transducer receives the echo signal. The time until the end is t1; similarly, the time from when the second transducer sends the waveform to when the first transducer receives the analog echo signal is t2; from formula 1, the ultrasonic flowmeter is based on the above time t1 and t2 can calculate the flow, and send this flow information to FPGA, and FPGA will send it to the touch screen for display. After the range is set, the corresponding 5 test points are clear. The range setting is changed according to the measurement range of the sensor. For example, if the range is set to 10m/S, the corresponding 10%, 30%, 60%, 90%, 100% The test points are (1m/S, 3m/S, 6m/S, 9m/S, 10m/S), and there is only one measuring range. In order to measure the linearity, depending on the range, it is necessary to set 5 test points, respectively 10%, 30%, 60%, 90%, 100% of the range, different test points, as shown in formula 1, 2, 3, determine After the pipe diameter, installation angle, ultrasonic speed and other parameters are determined, it is only necessary to change the time t1 and t2. If the ultrasonic flowmeter works normally, the corresponding theoretical flow rate can be obtained, and the linearity error of the system should not exceed 2%. . The test points currently set in this system are the above five, which are also the test points generally required for the actual flow calibration of the ultrasonic flowmeter industry. In the future, the position and quantity of the test points can be flexibly changed through the touch screen parameter setting.

Claims (6)

1. the flow velocity simulation system of a ultrasonic flow meter, it is characterized in that: comprise FPGA circuit, touch-screen, D/A converter, output control circuit, channel switching circuit, signal threshold value comparator circuit and two transducers, described FPGA circuit respectively with output control circuit, channel switching circuit connects, for controlling output control circuit respectively, being switched on or switched off of channel switching circuit, described FPGA circuit is connected with touch-screen by RS485 interface, described FPGA circuit is connected with ultrasonic flow meter to be measured by RS232 interface, described ultrasonic flow meter to be measured is used for sending drive singal respectively to two transducers, described two transducers are used for the drive singal accepting ultrasonic flow meter to be measured respectively, and pass to signal threshold value comparator circuit through channel switching circuit respectively, described signal threshold value comparator circuit is used for ultrasonic flow meter to be measured to drive the driving voltage of transducer and the threshold value of setting to compare, export enabling signal to FPGA circuit, described FPGA circuit is used for the enabling signal of Received signal strength threshold value comparator circuit, produce timing, timing output control signal, control D/A converter output ultrasonic wave pulse waveform, and pass to two transducers respectively through output control circuit.

2. the flow velocity simulation system of ultrasonic flow meter according to claim 1, is characterized in that: described FPGA circuit adopts model to be the fpga chip of EP4CE10.

3. the flow velocity simulation system of ultrasonic flow meter according to claim 1, is characterized in that: described D/A converter adopts model to be the digital to analog converter of AD9760AR.

4. the flow velocity simulation system of ultrasonic flow meter according to claim 1, is characterized in that: described output control circuit adopts model to be the analog switch chip of ADG1421.

5. the flow velocity simulation system of ultrasonic flow meter according to claim 1, it is characterized in that: described signal threshold value comparator circuit comprises amplifier (U12A), amplifier (U14B) and some resistance, electric capacity, the in-phase input end of described amplifier (U14B) is connected with the output terminal of channel switching circuit through the 28th resistance (R28), the inverting input of amplifier (U14B) respectively with one end of the 26th resistance (R26), one end of 27th resistance (R27), one end of 53rd electric capacity (C53) connects, the other end ground connection of the 26th resistance (R26), the other end of the 27th resistance (R27), the other end of the 53rd electric capacity (C53) is all connected with the output terminal of amplifier (U14B), the output terminal of amplifier (U14B) is connected with the in-phase input end of amplifier (U12A) through the 29th resistance (R29), the inverting input of amplifier (U12A) respectively with one end of resistance (RA1), one end of resistance (RA2) connects, another termination 1.2V voltage of resistance (RA1), the other end ground connection of resistance (RA2), the output terminal of described amplifier (U12A) is connected with FPGA circuit.

6. the flow velocity simulation system of ultrasonic flow meter according to claim 1, is characterized in that: described channel switching circuit adopts model to be the analog switch chip of ADG1421.