CN204272094U

CN204272094U - I/Q Mismatch Detection Circuit for Low IF Receiver

Info

Publication number: CN204272094U
Application number: CN201420622056.6U
Authority: CN
Inventors: 胡伟迪; 何文涛; 李晓江
Original assignee: JIAXING MICROELECTRONICS AND SYSTEMS ENGINEERING CENTER CHINESE ACADEMY OF SCIENCES
Current assignee: HANGZHOU ZHONGKE MICROELECTRONICS CO Ltd
Priority date: 2014-10-24
Filing date: 2014-10-24
Publication date: 2015-04-15
Anticipated expiration: 2024-10-24

Abstract

The utility model discloses an I/Q mismatch detection circuit of a low intermediate frequency receiver, which is used for detecting amplitude mismatch and phase mismatch between a Q channel signal and an I channel signal or between an I channel signal and a Q channel signal. The first signal comes from the I channel, and the second signal comes from the Q channel. The I/Q mismatch detection circuit of the low intermediate frequency receiver of the present invention comprises two accumulators, one multiplication accumulator, two square accumulators, two squarers, one square extractor, two dividers, two A multiplier, three subtractors and three left shifters, these arithmetic units form a circuit according to the detection operation formula, and obtain amplitude mismatch and phase mismatch according to the first signal and the second signal. The utility model forms a functional circuit according to a detection operation formula through a plurality of arithmetic units, and can obtain amplitude mismatch and phase mismatch quickly and with high precision, so as to facilitate subsequent I/Q mismatch compensation operations.

Description

I/Q Mismatch Detection Circuit for Low IF Receiver

技术领域 technical field

本实用新型涉及一种检测电路，尤其涉及一种低中频接收机的I/Q失配检测电路。 The utility model relates to a detection circuit, in particular to an I/Q mismatch detection circuit of a low intermediate frequency receiver.

背景技术 Background technique

近年来，基于正交下变频结构的使用，低中频接收机得到了广泛的应用，低中频接收机具有超外差接收机和零中频接收机的优点，即直流失调干扰小，1/f噪声干扰影响小，但低中频接收机中存在镜像信号干扰的问题。经天线接收的信号经混频器一次正交下变频后变为同相正交两路信号，但由于本地振荡器不可能精确产生90°相差的信号，混频后级的放大器和复数滤波器本身的结构不对称同样会引起I/Q两路幅度和相位失配，因此，需要在电路中引入I/Q失配补偿电路。 In recent years, based on the use of quadrature down-conversion structure, low-IF receivers have been widely used. Low-IF receivers have the advantages of superheterodyne receivers and zero-IF receivers, that is, small DC offset interference, 1/f noise The effect of interference is small, but there is a problem of image signal interference in low-IF receivers. The signal received by the antenna is turned into two signals in phase and quadrature after a quadrature down-conversion by the mixer. However, since the local oscillator cannot accurately generate signals with a 90° phase difference, the amplifier and the complex filter itself in the post-mixing stage The structural asymmetry of the I/Q circuit will also cause the amplitude and phase mismatch of the I/Q channels. Therefore, an I/Q mismatch compensation circuit needs to be introduced into the circuit.

一种补偿方案是采用模拟方法消除，I/Q失配补偿电路置于复数滤波器之前，利用ADC采样信号估计I/Q失配值或直接在模拟域估计失配值，利用模拟电路实现补偿。此种方式虽然电路结构简单，但由于电阻和电流源限制，不能产生较为精确的补偿值，随着需要补偿的失配范围增大，电路规模也不可避免的增大，而且对于不同的工艺，电路参数都需重新设计，增加了设计周期和设计成本。 One compensation scheme is to use an analog method to eliminate it. The I/Q mismatch compensation circuit is placed before the complex filter, and the ADC sampling signal is used to estimate the I/Q mismatch value or directly estimate the mismatch value in the analog domain, and the analog circuit is used to realize the compensation. . Although the circuit structure of this method is simple, due to the limitation of resistance and current source, it cannot produce more accurate compensation value. As the range of mismatch that needs to be compensated increases, the scale of the circuit will inevitably increase, and for different processes, All circuit parameters need to be redesigned, which increases the design cycle and design cost.

现有技术的中国专利申请“正交下变频接收机I、Q通道信号失配校准装置”(申请号201110076268.X)采用可调电阻和偏置电流源实现在模拟域对幅度和相位失配进行校准，其可达到的幅度校准范围为±1.6dB，校准精度为0.2dB；相位校准范围为±5°，校准精度为0.5°。此校准装置虽具有较简单的电路结构(参见图1，图中的各元件及其符号可参阅该专利申请)，但仅具有校准功能，失配检测功能需要另外电路来实现，而且校准精度较差，在幅度和相位失配较小时不能正确校准。 The prior art Chinese patent application "Quadrature down-conversion receiver I, Q channel signal mismatch calibration device" (application number 201110076268.X) uses adjustable resistance and bias current source to realize the amplitude and phase mismatch in the analog domain For calibration, the achievable amplitude calibration range is ±1.6dB, and the calibration accuracy is 0.2dB; the phase calibration range is ±5°, and the calibration accuracy is 0.5°. Although this calibration device has a relatively simple circuit structure (see Figure 1, the components and their symbols in the figure can refer to the patent application), it only has a calibration function, and the mismatch detection function needs another circuit to realize, and the calibration accuracy is relatively high. Poor and cannot be calibrated correctly when the magnitude and phase mismatches are small.

现有技术的中国专利申请“一种正交I/Q信号相位失衡校正电路”(申请号201210338612.2)利用I/Q信号的正交特性，采用矩阵耦合电路进行相位失衡校正，耦合系数决定校正幅度大小，能达到相位校正范围±7°，和0.04°的校正精度(参见图2，图中的各元件及其符号可参阅该专利申请)。此实用新型校正精度高，集成度高，但是不能对幅度失配进行校正，而且，随着需要校正的相位失配范围增大，电路的规模也会增大。 The prior art Chinese patent application "A Quadrature I/Q Signal Phase Imbalance Correction Circuit" (Application No. 201210338612.2) utilizes the quadrature characteristics of I/Q signals and uses a matrix coupling circuit for phase imbalance correction. The coupling coefficient determines the correction range The size can reach a phase correction range of ±7°, and a correction accuracy of 0.04° (see Figure 2, the components and their symbols in the figure can refer to the patent application). The utility model has high correction precision and high integration, but cannot correct the amplitude mismatch, and, as the range of the phase mismatch to be corrected increases, the scale of the circuit also increases.

广范应用的方案是在数字域进行消除，利用ADC和DSP采用多种基带处理算法数字域消除，此种设计方案可以同时消除由于复数滤波器和放大器的不对称引起的失配，但是由于较高的镜像抑制比需要高精度ADC和高速DSP，此种设计方案是以成本和功耗为代价。 The widely used solution is to eliminate in the digital domain, using ADC and DSP to use a variety of baseband processing algorithms to eliminate in the digital domain. This design can simultaneously eliminate the mismatch caused by the asymmetry of the complex filter and amplifier, but due to A higher image rejection ratio requires a high-precision ADC and a high-speed DSP, and this design scheme is at the cost of cost and power consumption.

在I/Q失配补偿电路中，失配检测功能是最关键的。因此，本领域的技术人员致力于开发一种低中频接收机的I/Q失配检测电路。 In the I/Q mismatch compensation circuit, the mismatch detection function is the most critical. Therefore, those skilled in the art are devoting themselves to developing an I/Q mismatch detection circuit for a low-IF receiver.

实用新型内容 Utility model content

有鉴于现有技术的上述缺陷，本实用新型所要解决的技术问题是提供一种低中频接收机的I/Q失配检测电路，对I/Q失配进行检测。 In view of the above-mentioned defects of the prior art, the technical problem to be solved by the utility model is to provide an I/Q mismatch detection circuit of a low-IF receiver to detect the I/Q mismatch.

假设理想情况下经正交下变频后I/Q两通道的信号I_iedal和Q_iedal分别为：I_iedal＝cos(ω_ct)，Q_iedal＝sin(ω_ct)。由于本地振荡器等器件自身不理想因素，假设Q通道相对I通道具有幅度失配α、相位失配β，则实际I/Q两通道信号I_real和Q_real分别为：I_real＝cos(ω_ct)，Q_real＝αsin(ω_ct-β)。两组信号之间的关系以矩阵形式表示为： Assume ideally that the I/Q two-channel signals _Iiedal and _Qiedal after quadrature down-conversion are respectively: _Iiedal =cos(ω _c t), Q _iedal =sin(ω _c t). Due to the imperfect factors of the local oscillator and other devices, assuming that the Q channel has an amplitude mismatch α and a phase mismatch β relative to the I channel, the actual I/Q two-channel signals I _real and Q _real are respectively: I _real =cos(ω _c t ), Q _real =α sin(ω _c t−β). The relationship between the two sets of signals is expressed in matrix form as:

$[\begin{matrix} {I I}_{real real} \\ {Q Q}_{real real} \end{matrix}] = = [\begin{matrix} 11 & 00 \\ 00 & α α \end{matrix}] [\begin{matrix} 11 & 00 \\ sin sin ((- - β β)) & cos cos ((β β)) \end{matrix}] [\begin{matrix} {I I}_{ideal ideal} \\ {Q Q}_{ideal ideal} \end{matrix}]$

当β∈[-10°,10°]时，有sin(-β)≈-β,cos(β)≈1，因此上式可简化为： When β∈[-10°,10°], sin(-β)≈-β, cos(β)≈1, so the above formula can be simplified as:

$[\begin{matrix} {I I}_{real real} \\ {Q Q}_{real real} \end{matrix}] = = [\begin{matrix} 11 & 00 \\ 00 & α α \end{matrix}] [\begin{matrix} 11 & 00 \\ - - β β & 11 \end{matrix}] [\begin{matrix} {I I}_{ideal ideal} \\ {Q Q}_{ideal ideal} \end{matrix}]$

对上式逆变换后得到： After the inverse transformation of the above formula, we get:

$[\begin{matrix} {I I}_{ideal ideal} \\ {Q Q}_{ideal ideal} \end{matrix}] = = [\begin{matrix} 11 & 00 \\ sin sin ((β β)) & 11 \end{matrix}] [\begin{matrix} 11 & 00 \\ 00 & {α α}^{,, - - 11} \end{matrix}] [\begin{matrix} {I I}_{real real} \\ {Q Q}_{real real} \end{matrix}] - - - - - - ((11))$

I/Q失配检测就是估计出式(1)中的幅度失配α和相位失配β的值。 The I/Q mismatch detection is to estimate the values of amplitude mismatch α and phase mismatch β in formula (1).

为实现上述目的，本实用新型提供了一种低中频接收机的I/Q失配检测电路，用于检测Q通道相对于I通道的幅度失配和相位失配，第一信号来自所述I通道，第二信号来自所述Q通道，其特征在于，由若干运算器按检测运算式构成；所述检测运算式为： In order to achieve the above object, the utility model provides an I/Q mismatch detection circuit of a low-IF receiver, which is used to detect the amplitude mismatch and phase mismatch of the Q channel relative to the I channel, and the first signal comes from the I channel Passage, the second signal comes from described Q channel, it is characterized in that, is formed by detection formula by several arithmetic units; Described detection formula is:

$Di Di = = {Σ Σ}_{n no}^{N N} i i ((n no))$

$Dq Q = = {Σ Σ}_{n no}^{N N} q q ((n no))$

$Xi Xi = = {Σ Σ}_{n no}^{N N} i i {((n no))}^{22}$

$Xq Q = = {Σ Σ}_{n no}^{N N} q q {((n no))}^{22};;$

$Diq Diq = = {Σ Σ}_{n no}^{N N} i i ((n no)) \times \times q q ((n no))$

$GAIN GAIN__MIS MIS = = {α α}^{- - 11} = = \sqrt{\frac{N N \times \times Xi Xi - - {Di Di}^{22}}{N N \times \times Xq Q - - {Dq Q}^{22}}}$

$PHASE PHASE__MIS MIS = = sin sin ((- - β β)) = = \frac{N N \times \times Diq Diq - - Di Di \times \times Dq Q}{((N N \times \times Xq Q - - {Dq Q}^{22})) \times \times GAIN GAIN__MIS MIS}$

其中，1≤n≤N；所述运算器接受N个所述第一信号的采样值i(n)和N个所述第二信号的采样值q(n)，输出相关于所述幅度失配的信号GAIN_MIS和相关于所述相位失配的信号PHASE_MIS。 Wherein, 1≤n≤N; the operator accepts N sampled values i(n) of the first signal and N sampled values q(n) of the second signal, and outputs The matched signal GAIN_MIS and the signal PHASE_MIS related to the phase mismatch.

进一步地，所述运算器包括若干累加器、若干平方累加器、若干平方器、若干除法器、若干乘法器、若干减法器、若干移位器和开方器。 Further, the arithmetic unit includes several accumulators, several square accumulators, several squarers, several dividers, several multipliers, several subtractors, several shifters and square extractors.

进一步地，所述运算器包括第一累加器、第二累加器、第一平方累加器、第二平方累加器、乘累加器、第一平方器、第二平方器、开方器、第一除法器、第二除法器、第一乘法器、第二乘法器、第一减法器、第二减法器、第三减法器、第一左移位器、第二左移位器和第三左移位器； Further, the arithmetic unit includes a first accumulator, a second accumulator, a first square accumulator, a second square accumulator, a multiplication accumulator, a first squarer, a second squarer, a square root, a first divider, second divider, first multiplier, second multiplier, first subtractor, second subtractor, third subtractor, first left shifter, second left shifter, and third left shifter;

所述第一累加器的输入端接受N个所述第一信号的采样值i(n)，其输出端与所述第一平方器的输入端和所述第一乘法器的一个输入端相连； The input terminal of the first accumulator accepts N sampled values i(n) of the first signal, and its output terminal is connected with the input terminal of the first squarer and an input terminal of the first multiplier ;

所述第一平方累加器的输入端接受N个所述第一信号的采样值i(n)，其输出端与所述第一左移位器的输入端相连； The input end of the first square accumulator accepts N sampled values i(n) of the first signal, and its output end is connected to the input end of the first left shifter;

所述第二累加器的输入端接受N个所述第二信号的采样值q(n)，其输出端与所述第二平方器的输入端和所述第一乘法器的另一个输入端相连； The input terminal of the second accumulator accepts N sampling values q(n) of the second signal, and its output terminal is connected to the input terminal of the second squarer and the other input terminal of the first multiplier connected;

所述第二平方累加器的输入端接受N个所述第二信号的采样值q(n)，其输出端与所述第二左移位器的输入端相连； The input terminal of the second square accumulator accepts N sampling values q(n) of the second signal, and its output terminal is connected to the input terminal of the second left shifter;

所述乘累加器的输入端接受N个所述第一信号的采样值i(n)和N个所述第二信号的采样值q(n)，其输出端与所述第三左移位器的输入端相连； The input terminal of the multiply-accumulator accepts N sampled values i(n) of the first signal and N sampled values q(n) of the second signal, and its output terminal is shifted left with the third The input terminal of the device is connected;

所述第一平方器的输出端与所述第一减法器的一个输入端相连，所述第一左移位器的输出端与所述第一减法器的另一个输入端相连，所述第一减法器的输出端与所述第一除法器的一个输入端相连； The output terminal of the first squarer is connected to one input terminal of the first subtractor, the output terminal of the first left shifter is connected to the other input terminal of the first subtractor, and the first an output of a subtractor connected to an input of said first divider;

所述第二平方器的输出端与所述第二减法器的一个输入端相连，所述第二左移位器的输出端与所述第二减法器的另一个输入端相连，所述第二减法器的输出端与所述第一除法器的另一个输入端相连，所述第二减法器的输出端还与所述第二乘法器的一个输入端相连； The output terminal of the second squarer is connected to one input terminal of the second subtractor, the output terminal of the second left shifter is connected to the other input terminal of the second subtractor, and the first The output end of the second subtractor is connected to the other input end of the first divider, and the output end of the second subtractor is also connected to an input end of the second multiplier;

所述第一除法器的输出端与所述开方器的输入端相连，所述开方器的输出端与所述第二乘法器的另一个输入端相连，并且所述开方器的输出端输出所述信号GAIN_MIS； The output end of the first divider is connected to the input end of the square root, the output end of the square root is connected to the other input end of the second multiplier, and the output of the square root The terminal outputs the signal GAIN_MIS;

所述第一乘法器的输出端与所述第三减法器的一个输入端相连，所述第三左移位器的输出端与所述第三减法器的另一个输入端相连，所述第三减法器的输出端与所述第二除法器的一个输入端相连； The output terminal of the first multiplier is connected to one input terminal of the third subtractor, the output terminal of the third left shifter is connected to the other input terminal of the third subtractor, and the first The output end of the three subtractors is connected to an input end of the second divider;

所述第二乘法器的输出端与所述第二除法器的另一个输入端相连，所述第二除法器的输出端输出所述信号PHASE_MIS。 An output terminal of the second multiplier is connected to another input terminal of the second divider, and an output terminal of the second divider outputs the signal PHASE_MIS.

本实用新型还提供了一种低中频接收机的I/Q失配检测电路，用于检测I通道相对于Q通道的幅度失配和相位失配，第一信号来自所述I通道，第二信号来自所述Q通道，其特征在于，由若干运算器按检测运算式构成；所述检测运算式为： The utility model also provides an I/Q mismatch detection circuit of a low-IF receiver, which is used to detect the amplitude mismatch and phase mismatch of the I channel relative to the Q channel, the first signal comes from the I channel, and the second Signal is from described Q channel, is characterized in that, is formed by detection formula by several arithmetic units; Described detection formula is:

$Dq Q = = {Σ Σ}_{n no}^{N N} q q ((n no))$

$Di Di = = {Σ Σ}_{n no}^{N N} i i ((n no))$

$Xq Q = = {Σ Σ}_{n no}^{N N} q q {((n no))}^{22}$

$Xi Xi = = {Σ Σ}_{n no}^{N N} i i {((n no))}^{22};;$

$Diq Diq = = {Σ Σ}_{n no}^{N N} i i ((n no)) \times \times q q ((n no))$

$GAIN GAIN__MIS MIS = = {α α}^{- - 11} = = \sqrt{\frac{N N \times \times Xq Q - - {Dq Q}^{22}}{N N \times \times Xi Xi - - {Di Di}^{22}}}$

$PHASE PHASE__MIS MIS = = sin sin ((- - β β)) = = \frac{N N \times \times Diq Diq - - Di Di \times \times Dq Q}{((N N \times \times Xi Xi - - {Di Di}^{22})) \times \times GAIN GAIN__MIS MIS}$

由此可见，本实用新型的低中频接收机的I/Q失配检测电路通过若干运算器按检测运算式构成功能电路，能快速、高精度地获取幅度失配和相位失配，以利于后续的I/Q失配补偿操作。 It can be seen that the I/Q mismatch detection circuit of the low-IF receiver of the present invention constitutes a functional circuit by a number of arithmetic units according to the detection formula, and can obtain amplitude mismatch and phase mismatch quickly and with high precision, so as to facilitate follow-up I/Q mismatch compensation operation.

以下将结合附图对本实用新型的构思、具体结构及产生的技术效果作进一步说明，以充分地了解本实用新型的目的、特征和效果。 The design of the present utility model, concrete structures and the technical effects produced will be further described below in conjunction with the accompanying drawings, so as to fully understand the purpose, characteristics and effects of the present utility model.

附图说明 Description of drawings

图1是现有技术的一种正交下变频接收机I/Q通道信号失配校准装置的电路图。 FIG. 1 is a circuit diagram of an I/Q channel signal mismatch calibration device for a quadrature down-conversion receiver in the prior art.

图2是现有技术的一种I/Q失配相位校正电路的电路图。 FIG. 2 is a circuit diagram of an I/Q mismatch phase correction circuit in the prior art.

图3是在一个较佳的实施例中，本实用新型的低中频接收机I/Q失配检测电路的电路图。 Fig. 3 is a circuit diagram of the low-IF receiver I/Q mismatch detection circuit of the present invention in a preferred embodiment.

具体实施方式 Detailed ways

本实施中采用的失配检测电路有若干运算器构成，其功能是基于如下的对式(1)的算术表达： The mismatch detection circuit adopted in this implementation is composed of several arithmetic units, and its function is based on the following arithmetic expression of formula (1):

$Di Di = = \frac{11}{N N} Σi Σi ((n no))$

$Dq Q = = \frac{11}{N N} Σq Σq ((n no))$

$Xi Xi = = \frac{11}{N N} Σi Σ i {((n no))}^{22}$

$Xq Q = = \frac{11}{N N} Σq Σq {((n no))}^{22}$

$Diq Diq = = \frac{11}{N N} Σi Σ i ((n no)) \times \times q q ((n no))$ $GAIN GAIN__MIS MIS = = {α α}^{- - 11} = = \sqrt{\frac{Xi Xi - - {Di Di}^{22}}{Xq Q - - {Dq Q}^{22}}}$

$PHASE PHASE__MIS MIS = = sin sin ((- - β β)) = = \frac{Diq Diq - - Di Di \times \times Dq Q}{\sqrt{((Xi Xi - - {Di Di}^{22})) ((Xq Q - - {Dq Q}^{22}))}}$

并且，为尽可能的减少精度损失，对上式进行了如下变形： Moreover, in order to reduce the loss of precision as much as possible, the above formula is modified as follows:

$Di Di = = {Σ Σ}_{n no}^{N N} i i ((n no))$

$Dq Q = = {Σ Σ}_{n no}^{N N} q q ((n no))$

$Xi Xi = = {Σ Σ}_{n no}^{N N} i i {((n no))}^{22}$

$Xq Q = = {Σ Σ}_{n no}^{N N} q q {((n no))}^{22}$

$Diq Diq = = {Σ Σ}_{n no}^{N N} i i ((n no)) \times \times q q ((n no))$

上式中i(n)表示I通道信号的第n个采样点，q(n)表示Q通道信号第n个采样点，N为总采样点数。输出信号GAIN_MIS与幅度失配α相关，信号PHASE_MIS与相位失配β相关。 In the above formula, i(n) represents the nth sampling point of the I channel signal, q(n) represents the nth sampling point of the Q channel signal, and N is the total number of sampling points. The output signal GAIN_MIS is related to the amplitude mismatch α and the signal PHASE_MIS is related to the phase mismatch β.

如图3所示，在一个较佳的实施例中，本实用新型的低中频接收机I/Q失配检测电路包括第一累加器110、第二累加器210、第一平方累加器121、第二平方累加器221、乘累加器310、第一平方器120、第二平方器220、开方器160、第一除法器150、第二除法器250、第一乘法器130、第二乘法器230、第一减法器140、第二减法器240、第三减法器340、第一左移位器131、第二左移位器231和第三左移位器331。其中： As shown in Figure 3, in a preferred embodiment, the I/Q mismatch detection circuit of the low-IF receiver of the present invention comprises a first accumulator 110, a second accumulator 210, a first square accumulator 121, Second square accumulator 221, multiplication accumulator 310, first squarer 120, second squarer 220, square root 160, first divider 150, second divider 250, first multiplier 130, second multiplier 230 , a first subtractor 140 , a second subtractor 240 , a third subtractor 340 , a first left shifter 131 , a second left shifter 231 and a third left shifter 331 . in:

第一累加器110的输入端接受N个第一信号的采样值i(n)，其输出端与第一平方器120的输入端和第一乘法器130的一个输入端相连； The input end of the first accumulator 110 accepts the sampling value i(n) of N first signals, and its output end is connected with the input end of the first squarer 120 and an input end of the first multiplier 130;

第一平方累加器121的输入端接受N个第一信号的采样值i(n)，其输出端与第一左移位器131的输入端相连； The input end of the first square accumulator 121 accepts the sampling value i(n) of N first signals, and its output end is connected with the input end of the first left shifter 131;

第二累加器210的输入端接受N个第二信号的采样值q(n)，其输出端与第二平方器220的输入端和第一乘法器130的另一个输入端相连； The input end of the second accumulator 210 accepts the sampling value q(n) of N second signals, and its output end is connected with the input end of the second squarer 220 and the other input end of the first multiplier 130;

第二平方累加器221的输入端接受N个第二信号的采样值q(n)，其输出端与第二左移位器231的输入端相连； The input end of the second square accumulator 221 accepts the sampling value q(n) of N second signals, and its output end is connected with the input end of the second left shifter 231;

乘累加器310的输入端接受N个第二信号的采样值q(n)和N个第二信号的采样值q(n)，其输出端与第三左移位器331的输入端相连； The input end of multiplication accumulator 310 accepts the sampling value q (n) of N second signal and the sampling value q (n) of N second signal, and its output end is connected with the input end of the 3rd left shifter 331;

第一平方器120的输出端与第一减法器140的一个输入端相连，第一左移位器131的输出端与第一减法器140的另一个输入端相连，第一减法器140的输出端与第一除法器150的一个输入端相连； The output terminal of the first squarer 120 is connected with an input terminal of the first subtractor 140, the output terminal of the first left shifter 131 is connected with the other input terminal of the first subtractor 140, the output of the first subtractor 140 End is connected with an input end of the first divider 150;

第二平方器220的输出端与第二减法器240的一个输入端相连，第二左移位器231的输出端与第二减法器240的另一个输入端相连，第二减法器240的输出端与第一除法器150的另一个输入端相连，第二减法器240的输出端还与第二乘法器230的一个输入端相连； The output terminal of the second squarer 220 is connected with an input terminal of the second subtractor 240, the output terminal of the second left shifter 231 is connected with the other input terminal of the second subtractor 240, the output of the second subtractor 240 terminal is connected with another input terminal of the first divider 150, and the output terminal of the second subtractor 240 is also connected with an input terminal of the second multiplier 230;

第一除法器150的输出端与开方器160的输入端相连，开方器160的输出端与第二乘法器230的另一个输入端相连，并且开方器160的输出端输出信号GAIN_MIS； The output end of the first divider 150 is connected to the input end of the square extractor 160, the output end of the square extractor 160 is connected to the other input end of the second multiplier 230, and the output end of the square extractor 160 outputs a signal GAIN_MIS;

第一乘法器130的输出端与第三减法器340的一个输入端相连，第三左移位器331的输出端与第三减法器340的另一个输入端相连，第三减法器340的输出端与第二除法器250的一个输入端相连； The output terminal of the first multiplier 130 is connected with an input terminal of the third subtractor 340, the output terminal of the third left shifter 331 is connected with the other input terminal of the third subtractor 340, the output of the third subtractor 340 End is connected with an input end of the second divider 250;

第二乘法器230的输出端与第二除法器250的另一个输入端相连，第二除法器250的输出端输出信号PHASE_MIS。 The output terminal of the second multiplier 230 is connected to the other input terminal of the second divider 250 , and the output terminal of the second divider 250 outputs the signal PHASE_MIS.

其中，i(n)被送入第一累加器110以获取Di，并被送入第一平方累加器121以获取Xi；q(n)被送入第二累加器210以获取Dq，并被送入第二平方累加器221以获取Xq；i(n)和q(n)皆被送入第三累加器310以获取Diq。假设幅度失配值α^-1∈[0.875,1.15]，则开方器160可由Taylor展开式的二阶近似得到，即 x∈[-0.25,0.3225]。各个左移位器对累加值进行左移操作，移位的个数与累加的采样点数有关，当每更新周期累加采样点数为N时，则左移位数为log₂(N)，一般选择N为2的幂级数。 Wherein, i(n) is sent into the first accumulator 110 to obtain Di, and is sent into the first square accumulator 121 to obtain Xi; q(n) is sent into the second accumulator 210 to obtain Dq, and is Both i(n) and q(n) are sent to the third accumulator 310 to obtain Diq. Assuming that the amplitude mismatch value α ^-1 ∈ [0.875,1.15], the square root 160 can be obtained by the second-order approximation of the Taylor expansion, namely x∈[-0.25,0.3225]. Each left shifter performs a left shift operation on the accumulated value. The number of shifts is related to the number of accumulated sampling points. When the number of accumulated sampling points per update cycle is N, the number of left shifts is log ₂ (N). Generally, select N is a power series of 2.

以上详细描述了本实用新型的较佳具体实施例。应当理解，本领域的普通技术人员无需创造性劳动就可以根据本实用新型的构思做出诸多修改和变化。因此，凡本技术领域的技术人员依本实用新型的构思在现有技术的基础上通过逻辑分析、推理或者有限的实验可以得到的技术方案，皆应在由权利要求书所确定的保护范围内。 The preferred specific embodiments of the present utility model have been described in detail above. It should be understood that those skilled in the art can make many modifications and changes according to the concept of the present utility model without creative efforts. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the utility model through logical analysis, reasoning or limited experiments on the basis of the prior art should be within the scope of protection defined by the claims .

Claims

1. the I/Q electrical mismatch detection circuit of a low intermediate frequency receiver, for detecting Q channel signal relative to the signal amplitude mismatch α of I passage and phase mismatch β, the first signal is from described I passage, and secondary signal is from described Q passage, it is characterized in that, be made up of some arithmetic units;

Described arithmetic unit accepts the sampled value i (n) of N number of described first signal and the sampled value q (n) of N number of described secondary signal, exports and is relevant to the signal GAIN_MIS of described amplitude mismatch α and is relevant to the signal PHASE_MIS of described phase mismatch β; GAIN_MIS=α ^-1, PHASE_MIS=sin (-β);

Described arithmetic unit comprises the first accumulator, the second accumulator, the first squared accumulator, the second squared accumulator, multiply-accumulator, the first squarer, the second squarer, square root extractor, the first divider, the second divider, the first multiplier, the second multiplier, the first subtracter, the second subtracter, the 3rd subtracter, the first left shifter, the second left shifter and the 3rd left shifter;

The input of described first accumulator accepts the sampled value i (n) of N number of described first signal, and its output is connected with an input of described first multiplier with the input of described first squarer;

The input of described first squared accumulator accepts the sampled value i (n) of N number of described first signal, and its output is connected with the input of described first left shifter;

The input of described second accumulator accepts the sampled value q (n) of N number of described secondary signal, and its output is connected with another input of described first multiplier with the input of described second squarer;

The input of described second squared accumulator accepts the sampled value q (n) of N number of described secondary signal, and its output is connected with the input of described second left shifter;

The input of described multiply-accumulator accepts the sampled value i (n) of N number of described first signal and the sampled value q (n) of N number of described secondary signal, and its output is connected with the input of described 3rd left shifter;

The output of described first squarer is connected with an input of described first subtracter, the output of described first left shifter is connected with another input of described first subtracter, and the output of described first subtracter is connected with an input of described first divider;

The output of described second squarer is connected with an input of described second subtracter, the output of described second left shifter is connected with another input of described second subtracter, the output of described second subtracter is connected with another input of described first divider, and the output of described second subtracter is also connected with an input of described second multiplier;

The output of described first divider is connected with the input of described square root extractor, and the output of described square root extractor is connected with another input of described second multiplier, and the output of described square root extractor exports described signal GAIN_MIS;

The output of described first multiplier is connected with an input of described 3rd subtracter, the output of described 3rd left shifter is connected with another input of described 3rd subtracter, and the output of described 3rd subtracter is connected with an input of described second divider;

The output of described second multiplier is connected with another input of described second divider, and the output of described second divider exports described signal PHASE_MIS.