CN204204376U - Array base palte drive element of the grid, circuit and display device - Google Patents
Array base palte drive element of the grid, circuit and display device Download PDFInfo
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- CN204204376U CN204204376U CN201420679978.0U CN201420679978U CN204204376U CN 204204376 U CN204204376 U CN 204204376U CN 201420679978 U CN201420679978 U CN 201420679978U CN 204204376 U CN204204376 U CN 204204376U
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- transistor
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- clock signal
- array base
- base palte
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Abstract
The utility model provides a kind of array base palte drive element of the grid, circuit and display device.Described array base palte drive element of the grid, comprises input end, opening module, control module, output module and gate drive signal output terminal, and opening module is used for controlling to input described control module from the trigger pip of described input end in opening time section; Described control module exports second clock signal in output time section to output module; Described output module controls the first level in opening time section and exports described gate drive signal output terminal to and export second clock signal to gate drive signal output terminal in output time section, controls the first level export gate drive signal output terminal in the section of holding time; First clock signal and second clock signal inversion.The utility model can realize narrow frame.
Description
Technical field
The utility model relates to display technique field, particularly relates to a kind of array base palte drive element of the grid, circuit and display device.
Background technology
GOA (Gate On Array, array base palte gate driver circuit) be generally applied to LTPS (LowTemperature Poly-silicon, low temperature polycrystalline silicon) display panel, the circuit structure of current most of GOA uses 2 or 3 clock signals usually, and two DC level (high level VHG and low level VGL), realize shift-register functions when scanning grid line step by step.
As shown in Figure 1, the N level array base palte drive element of the grid that the array base palte gate driver circuit of the existing a kind of LTPS of being applied to display panel comprises comprises input end (not showing in Fig. 1), the first transistor T1, transistor seconds T2, third transistor T3, the 4th transistor T4, the 5th transistor T5, the 6th transistor T6, the 7th transistor T7, the first electric capacity C1, the second electric capacity C2 and gate drive signal output terminal G
n, wherein,
T1, T2, T3, T4, T5, T6 and T7 are p-type transistor;
This input end accesses the N-1 level gate drive signal G that N-1 level array base palte drive element of the grid exports
n-1using as trigger pip;
This gate drive signal output terminal G
nexport N level gate drive signal;
N be greater than 1 integer.
Existing array base palte gate driver circuit comprises 7 transistors and 2 memory capacitance, have employed two clock signals (the first clock signal clk and second clock signal CLKB) and two direct current signals (high level VGH and low level VGL).The GOA circuit of existing 7T2C uses more signal wire and transistor, and the narrow border display realizing below 1mm is more difficult.
Utility model content
Fundamental purpose of the present utility model is to provide a kind of array base palte drive element of the grid, circuit and display device, to realize narrow frame.
In order to achieve the above object, the utility model provides a kind of array base palte drive element of the grid, comprises input end, opening module, control module, output module and gate drive signal output terminal, wherein,
Described opening module, for the opening time section in each display cycle, controls to input described control module from the trigger pip of described input end under the control of the first clock signal;
Described control module, for the output time section in each display cycle, under the control of described first clock signal, described first level and described trigger pip, exports second clock signal to described output module;
Described output module, for the opening time section in each display cycle, under the control of described first clock signal, control the first level export described gate drive signal output terminal to, also export described second clock signal to described gate drive signal output terminal for the output time section in each display cycle, also under the control of described first clock signal, control described first level for the section of holding time in each display cycle and export described gate drive signal output terminal to;
Described first clock signal and described second clock signal inversion.
During enforcement, described opening module comprises:
Turn-on transistor, described first clock signal of grid access, the first pole access is from the trigger pip of described input end, and the second pole is connected with described control module.
During enforcement, described control module comprises:
First controls transistor, and grid is connected with described opening module, and described second clock signal is accessed in the first pole;
Second controls transistor, described first clock signal of grid access, described first level of the first pole access, and the second pole controls the second pole of transistor respectively with described first and described output module is connected;
And, maintain electric capacity, be connected to the described first grid and described first controlling transistor and control between the second pole of transistor.
During enforcement, described output module comprises:
First output transistor, described first clock signal of grid access, described first level of the first pole access, the second pole is connected with described gate drive signal output terminal;
Second output transistor, the second pole that grid and described second controls transistor is connected, and the first pole is connected with described gate drive signal output terminal, and described second clock signal is accessed in the second pole.
During enforcement, described turn-on transistor, described first controls transistor, described second control transistor, described first output transistor and described second output transistor is all p-type transistor;
Described first level is high level.
During enforcement, described turn-on transistor, described first controls transistor, described second control transistor, described first output transistor and described second output transistor is all n-type transistor;
Described first level is low level.
The utility model additionally provides a kind of array base palte gate driver circuit, comprises multistage above-mentioned array base palte drive element of the grid;
Except first order array base palte drive element of the grid, the input end of every one-level array base palte drive element of the grid is connected with the gate drive signal output terminal of adjacent upper level array base palte drive element of the grid.
The utility model additionally provides a kind of display device, comprises above-mentioned array base palte gate driver circuit.
Compared with prior art, array base palte drive element of the grid described in the utility model use only five transistors and an electric capacity, and have employed three signal wires and drive, and decreases GOA circuit area, for realizing the display of narrow frame; And while minimizing transistor size and input signal cable, ensure stability and the reliability of GOA circuit; The utility model can use driver' s timing and the integrated circuit (IC) chip of prior art, is conducive to reducing costs.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of existing array base palte gate driver circuit;
Fig. 2 is the structural drawing of the array base palte gate driver circuit described in the utility model embodiment;
Fig. 3 is the circuit diagram of the array base palte gate driver circuit described in the utility model one specific embodiment;
Fig. 4 is the working timing figure of the array base palte gate driver circuit described in this specific embodiment of the utility model.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, be clearly and completely described the technical scheme in the utility model embodiment, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.
As shown in Figure 2, the array base palte drive element of the grid described in the utility model embodiment comprises input end (not showing in Fig. 3), opening module 31, control module 32, output module 33 and gate drive signal output terminal G
n(not showing in Fig. 3), wherein,
Described opening module 31, for the opening time section in each display cycle, controls the trigger pip G from described input end under the control of the first clock signal clk
n-1input described control module 32;
Described control module 32, for the output time section in each display cycle, at described first clock signal clk, described first level V1 and described trigger pip G
n-1control under, export second clock signal CLKB to described output module 33;
Described output module 33, for the opening time section in each display cycle, controls the first level V1 and exports described gate drive signal output terminal G under the control of described first clock signal clk
n, also export described second clock signal to described gate drive signal output terminal G for the output time section in each display cycle
n, also under the control of described first clock signal clk, control described first level V1 for the section of holding time in each display cycle and export described gate drive signal output terminal G to
n;
Described first clock signal clk and described second clock signal CLKB anti-phase.
When practical operation, described trigger pip is the gate drive signal G that adjacent upper level array base palte drive element of the grid exports
n-1.
Array base palte drive element of the grid described in the utility model embodiment only have employed a direct current signal (the first level V1), less signal wire is have employed relative to prior art, GOA circuit area can be reduced, be more conducive to the display realizing narrow frame.
The transistor adopted in all embodiments of the utility model can be all thin film transistor (TFT) or field effect transistor or the identical device of other characteristics.In the utility model embodiment, for distinguishing transistor the two poles of the earth except grid, wherein first can be extremely source electrode or drain electrode, and second can be extremely drain electrode or source electrode.In addition, distinguish transistor can be divided into n-type transistor or p-type transistor according to the characteristic of transistor.In the driving circuit that the utility model embodiment provides; all crystals Guan Jun is the explanation carried out for p-type transistor; it is conceivable that be that those skilled in the art can expect, therefore also in embodiment protection domain of the present utility model easily not making under creative work prerequisite when adopting n-type transistor to realize.
Concrete, described opening module comprises:
Turn-on transistor, described first clock signal of grid access, the first pole access is from the trigger pip of described input end, and the second pole is connected with described control module.
Concrete, described control module comprises:
First controls transistor, and grid is connected with described opening module, and described second clock signal is accessed in the first pole;
Second controls transistor, described first clock signal of grid access, described first level of the first pole access, and the second pole controls the second pole of transistor respectively with described first and described output module is connected;
And, maintain electric capacity, be connected to the described first grid and described first controlling transistor and control between the second pole of transistor.
Concrete, described output module comprises:
First output transistor, described first clock signal of grid access, described first level of the first pole access, the second pole is connected with described gate drive signal output terminal;
Second output transistor, the second pole that grid and described second controls transistor is connected, and the first pole is connected with described gate drive signal output terminal, and described second clock signal is accessed in the second pole.
Below by a specific embodiment, array base palte drive element of the grid described in the utility model is described:
As shown in Figure 3, in the array base palte drive element of the grid described in this specific embodiment of the utility model,
Described opening module 31 comprises:
Turn-on transistor T1, described first clock signal clk of grid access, the first pole access is from the trigger pip of described input end;
Described control module 32 comprises:
First controls transistor T2, and grid is connected with second pole of described turn-on transistor T1, and described second clock signal CLKB is accessed in the first pole;
Second controls transistor T3, described first clock signal clk of grid access, the first pole access high level VGH, and the second pole that the second pole and described first controls transistor T2 is connected;
And, maintain electric capacity C1, be connected to the described first grid and described first controlling transistor T2 and control between second pole of transistor T1;
Described output module 33 comprises:
First output transistor T4, described first clock signal clk of grid access, described high level VGH is accessed in the first pole, the second pole and described gate drive signal output terminal G
nconnect;
Second output transistor T5, the second pole that grid and described second controls transistor T3 is connected, the first pole and described gate drive signal output terminal G
nconnect, described second clock signal CLKB is accessed in the second pole;
T1, T2, T3, T4 and T5 are p-type transistor.
When practical operation, T1, T2, T3, T4 and T5 also can partly or entirely be replaced by N-shaped TFT, only need the control signal of the grid of the above-mentioned transistor of corresponding change, convert to and signal anti-phase when adopting p-type TFT by trigger pip, the first clock signal and second clock signal, and the first level is converted to low level by high level, more than change is the common technology means of this area, does not repeat them here.
In the array base palte drive element of the grid as described in the specific embodiment of Fig. 3, use only five transistors and an electric capacity, and have employed three signal wires and drive, decreasing GOA circuit area, for realizing the display of narrow frame.
The work schedule of the array base palte drive element of the grid described in this specific embodiment of the utility model is identical with the work schedule of existing array base palte drive element of the grid, specifically as shown in Figure 2.
As shown in Figure 4, the array base palte drive element of the grid as described in the specific embodiment of Fig. 3 operationally, in data write phase:
Be low level at opening time section T1, CLK, CLK opens T4, exports high level VGH to G
n; CLK, as start signal, opens T1; G
n-1as trigger pip, G
n-1for low level, then now the grid potential of T2 is low level, and T2 is opened, and CLKB is high level, then now the grid potential of T5 is high level, and T5 is turned off; CLK is low level, and T3 is opened, and the grid access high level VGH of T5, ensures to turn off T5; VGH to G is exported at opening time section T1
n;
Be high level at output time section T2, CLK, CLK turns off T1, G
n-1for low level, make the grid potential of T2 be maintained low level by C1, to make T2 maintain open mode, now CLKB becomes low level, and now the grid potential of T5 is low level, and T5 opens, G
naccess CLKB; CLK turns off transistor T3, makes VGH can not output to the grid of T5, ensures that T5 exports CLKB to G
n; CLK turns off T4 simultaneously, makes VGH not output to G
n;
In the data maintenance stage:
At the section of holding time T3, first clock period, CLK becomes low level, to open T4, exports VGH to G
n; CLK opens T1 simultaneously, makes the grid access G of T2
n-1, now G
n-1for high level, therefore the grid potential of T2 is high level, and T2 turns off; CLK opens T3, grid access VGH, the T5 of T5 is turned off, ensures that VGH is output to G
n; In the next clock period, CLK becomes high level, and T4 turns off, and the grid potential of transistor T5 remains high level by C1, to turn off T5, makes output terminal G
ncurrent potential be maintained high level.
At the procedure for displaying of next frame picture, repeat above-mentioned data write phase and data maintenance stage.
Array base palte drive element of the grid described in this specific embodiment of the utility model operationally, in the part-time of display one frame data, by the grid of CLK control T4, keep the voltage of the suspension node (this suspension node is the node be connected with the grid of T4) of dynamic circuit, ensure that suspension node voltage same as the prior art maintains level, while minimizing transistor size and input signal cable, ensure stability and the reliability of GOA circuit.
Further, the GOA circuit described in the utility model embodiment can use driver' s timing and the integrated circuit (IC) chip of prior art, is conducive to reducing costs.
Array base palte gate driver circuit described in the utility model, comprises multistage above-mentioned array base palte drive element of the grid;
Except first order array base palte drive element of the grid, the input end of every one-level array base palte drive element of the grid is connected with the gate drive signal output terminal of adjacent upper level array base palte drive element of the grid;
The input end access start signal of the first pole array base palte drive element of the grid.
Array base palte gate driver circuit described in the utility model embodiment can be applied in LTPS (LowTemperature Poly-silicon, low-temperature polysilicon silicon technology) display device.
The utility model additionally provides a kind of display device, comprises above-mentioned array base palte gate driver circuit.
Described display device can be LTPS display device.
The above is preferred implementation of the present utility model; should be understood that; for those skilled in the art; under the prerequisite not departing from principle described in the utility model; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.
Claims (8)
1. an array base palte drive element of the grid, is characterized in that, comprises input end, opening module, control module, output module and gate drive signal output terminal, wherein,
Described opening module, for the opening time section in each display cycle, controls to input described control module from the trigger pip of described input end under the control of the first clock signal;
Described control module, for the output time section in each display cycle, under the control of described first clock signal, the first level and described trigger pip, exports second clock signal to described output module;
Described output module, for the opening time section in each display cycle, under the control of described first clock signal, control the first level export described gate drive signal output terminal to, also export described second clock signal to described gate drive signal output terminal for the output time section in each display cycle, also under the control of described first clock signal, control described first level for the section of holding time in each display cycle and export described gate drive signal output terminal to;
Described first clock signal and described second clock signal inversion.
2. array base palte drive element of the grid as claimed in claim 1, it is characterized in that, described opening module comprises:
Turn-on transistor, described first clock signal of grid access, the first pole access is from the trigger pip of described input end, and the second pole is connected with described control module.
3. array base palte drive element of the grid as claimed in claim 2, it is characterized in that, described control module comprises:
First controls transistor, and grid is connected with described opening module, and described second clock signal is accessed in the first pole;
Second controls transistor, described first clock signal of grid access, described first level of the first pole access, and the second pole controls the second pole of transistor respectively with described first and described output module is connected;
And, maintain electric capacity, be connected to the described first grid and described first controlling transistor and control between the second pole of transistor.
4. array base palte drive element of the grid as claimed in claim 3, it is characterized in that, described output module comprises:
First output transistor, described first clock signal of grid access, described first level of the first pole access, the second pole is connected with described gate drive signal output terminal;
Second output transistor, the second pole that grid and described second controls transistor is connected, and the first pole is connected with described gate drive signal output terminal, and described second clock signal is accessed in the second pole.
5. array base palte drive element of the grid as claimed in claim 4, it is characterized in that, described turn-on transistor, described first controls transistor, described second control transistor, described first output transistor and described second output transistor is all p-type transistor;
Described first level is high level.
6. array base palte drive element of the grid as claimed in claim 4, it is characterized in that, described turn-on transistor, described first controls transistor, described second control transistor, described first output transistor and described second output transistor is all n-type transistor;
Described first level is low level.
7. an array base palte gate driver circuit, is characterized in that, comprises multistage array base palte drive element of the grid as described in claim arbitrary in claim 1 to 6;
Except first order array base palte drive element of the grid, the input end of every one-level array base palte drive element of the grid is connected with the gate drive signal output terminal of adjacent upper level array base palte drive element of the grid.
8. a display device, is characterized in that, comprises array base palte gate driver circuit as claimed in claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420679978.0U CN204204376U (en) | 2014-11-06 | 2014-11-06 | Array base palte drive element of the grid, circuit and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420679978.0U CN204204376U (en) | 2014-11-06 | 2014-11-06 | Array base palte drive element of the grid, circuit and display device |
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|---|---|
| CN204204376U true CN204204376U (en) | 2015-03-11 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104318888A (en) * | 2014-11-06 | 2015-01-28 | 京东方科技集团股份有限公司 | Array substrate gate drive unit, method and circuit and display device |
| CN114299872A (en) * | 2022-01-04 | 2022-04-08 | 京东方科技集团股份有限公司 | Driving circuit, driving method thereof and display device |
-
2014
- 2014-11-06 CN CN201420679978.0U patent/CN204204376U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104318888A (en) * | 2014-11-06 | 2015-01-28 | 京东方科技集团股份有限公司 | Array substrate gate drive unit, method and circuit and display device |
| WO2016070546A1 (en) * | 2014-11-06 | 2016-05-12 | 京东方科技集团股份有限公司 | Array substrate gate drive unit, method and circuit and display device |
| US10262572B2 (en) | 2014-11-06 | 2019-04-16 | Boe Technology Group Co., Ltd. | Gate-on-array driving unit, gate-on-array driving method, gate-on-array driving circuit, and display device |
| CN114299872A (en) * | 2022-01-04 | 2022-04-08 | 京东方科技集团股份有限公司 | Driving circuit, driving method thereof and display device |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20150311 |