CN204168278U - A kind of orthogonal lock-in-amplifier system for CPT atomic clock - Google Patents
A kind of orthogonal lock-in-amplifier system for CPT atomic clock Download PDFInfo
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- CN204168278U CN204168278U CN201420472193.6U CN201420472193U CN204168278U CN 204168278 U CN204168278 U CN 204168278U CN 201420472193 U CN201420472193 U CN 201420472193U CN 204168278 U CN204168278 U CN 204168278U
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Abstract
The utility model discloses a kind of orthogonal lock-in-amplifier system for CPT atomic clock, this system comprises sinusoidal wave lock-in amplify unit, for carrying out sinusoidal wave lock-in amplify to measured signal; With square wave lock-in amplify unit, for carrying out square-wave signal lock-in amplify to measured signal.Technical scheme described in the utility model adopts the orthogonal lock-in-amplifier system based on FPGA, and this scheme can complete square wave with sinusoidal wave phase-locked simultaneously; The utility model adopts orthogonal means, and phase-locked precision can reach the precision of 0.05 radian, improves the frequency marking precision of CPT atomic clock; Hardware resource utilization of the present utility model is low, can meet requirement that is miniaturized and low-power consumption; Whole design realizes at numeric field, utilizes on-line analysis technology to facilitate circuit debugging.
Description
Technical field
The utility model relates to a kind of lock-in amplify system, particularly relates to a kind of orthogonal lock-in-amplifier system for CPT atomic clock.
Background technology
Atomic frequency standard system can provide accurate time reference signal, plays a very important role in the field such as satellite navigation and scientific experiment.CPT atomic clock at home and abroad obtains as the focus that miniaturized atomic clock is developed and pays close attention to widely, and it utilizes the CPT phenomenon that double-colored coherent light and the effect of alkali metal atom system produce and a kind of novel frequency marking with small size and low-power consumption realized.In the design of physical system, CPT frequency marking does not need microwave cavity, and can replace the spectrum lamp of traditional passivity Rb atom frequency marking by semiconductor laser tube.
In the design of Circuits System, miniaturized servo system is a difficult point of design.The servo system of CPT atomic clock comprises two parts, laser servo system and microwave servo system, like this when carrying out lock-in amplify to light inspection signal, just needs two cover phase-locked systems.And while ensureing precision, in order to requirement that is miniaturized and low-power consumption, phase-locked system must use fewer hardware resource.
Therefore, need to provide one can realize carrying out lock-in amplify to laser servo system and microwave servo system simultaneously, can ensure that again hardware resource consumption is few, the institute that volume is little thinks amplification system.
Utility model content
The technical problems to be solved in the utility model is to provide a kind of orthogonal lock-in-amplifier system for CPT atomic clock, lock-in amplify can not be carried out to laser servo system and microwave servo system to overcome in prior art simultaneously simultaneously, and ensure that hardware consumption is few, the problem that volume is little, meets the miniaturization of CPT atomic clock servo system, low-power consumption and high-precision demand simultaneously.
For solving the problems of the technologies described above, the utility model adopts following technical proposals.
For an orthogonal lock-in-amplifier system for CPT atomic clock, this system comprises
Sinusoidal wave lock-in amplify unit, for carrying out sinusoidal wave lock-in amplify to measured signal; With
Square wave lock-in amplify unit, for carrying out square-wave signal lock-in amplify to measured signal.
Preferably, this system comprises the first filter further, for carrying out filtering to measured signal, and obtains sine wave signal; Second filter, for carrying out filtering to measured signal, and obtains square-wave signal.
Preferably, described first filter is the FIR filter that 5KHz band is logical, and its pass band width is 800Hz; Described second filter is the FIR filter that 500Hz band is logical, and its pass band width is 200Hz.
Preferably, described sinusoidal wave lock-in amplify unit comprises
Derived reference signal, for generation of the reference signal that two-way is orthogonal;
Phase shifter, for adjusting reference signal phase place, makes it consistent with sine wave signal phase place to be measured;
First multiplier, for being multiplied with first via reference signal by sine wave signal to be measured, obtains amplitude and the phase difference cosine value product of measured signal after being multiplied;
Second multiplier, for being multiplied with the second tunnel reference signal by sine wave signal to be measured, obtains amplitude and the phase difference cosine value product of measured signal after being multiplied;
First divider, carries out division arithmetic for the product exported the first multiplier and the second multiplier, obtains the tangent value of the phase error of two product signals; With
Table look-up device, for the tangent value of described phase error is carried out arctangent cp cp operation, obtains phase error, and adjusts the initial phase of reference signal by this phase error;
Preferably, described sinusoidal wave lock-in amplify unit comprises further
Be connected to the first integrator between the first multiplier and the first divider;
Be connected to the second integral device between the second multiplier and the first divider.
Preferably, described sinusoidal wave lock-in amplify unit comprises
Counter, for time frequency division, obtains the square wave reference signal of preset frequency;
First delayer, for adjusting the phase place of square wave reference signal, making all the other square-wave signal phase places to be measured consistent, and exporting two-way square wave reference signal;
Second delayer, for the wherein road time delay by two-way square wave reference signal, makes the square wave reference signal that two-way square wave reference signal becomes orthogonal;
3rd multiplier, for being multiplied with first via square wave reference signal by square-wave signal to be measured, obtains amplitude and the phase difference cosine value product of square-wave signal to be measured after being multiplied;
4th multiplier, for square-wave signal to be measured and the square wave reference signal orthogonal with first via square wave reference signal being multiplied, obtains amplitude and the phase difference cosine value product of square-wave signal to be measured after being multiplied;
Accumulator, adds up for the product exported the 3rd multiplier and the 4th multiplier, obtains four phase error intervals; With
Second divider, utilizes circulation comparison method to calculate the integer numerical value of business between any two, adjusts the first delayer by this integer numerical value, make square wave reference signal consistent with square-wave signal to be measured.
Preferably, described sinusoidal wave lock-in amplify unit also comprises the interval judging module be connected to before accumulator and the second divider.
A kind of FPGA comprising above-mentioned orthogonal lock-in-amplifier system.
The beneficial effects of the utility model are as follows:
Technical scheme described in the utility model adopts the orthogonal lock-in-amplifier system based on FPGA, and this scheme can complete square wave with sinusoidal wave phase-locked simultaneously; The utility model adopts orthogonal means, and phase-locked precision can reach the precision of 0.05 radian, improves the frequency marking precision of CPT atomic clock; Hardware resource utilization of the present utility model is low, can meet requirement that is miniaturized and low-power consumption; Whole design realizes at numeric field, utilizes on-line analysis technology to facilitate circuit debugging.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, embodiment of the present utility model is described in further detail;
Fig. 1 illustrates the schematic diagram of a kind of orthogonal lock-in-amplifier system for CPT atomic clock described in the utility model.
Embodiment
Below in conjunction with one group of embodiment and accompanying drawing, the utility model is described further.
As shown in Figure 1, the utility model discloses a kind of CPT atomic clock orthogonal lock-in-amplifier device system based on FPGA, this system comprises: the first filter 1, first multiplier 2, second multiplier 3, first integrator 4, first integrator 5, first divider 6, finger 7, phase shifter 9, derived reference signal 8, second filter 10, the 3rd multiplier 11, the 4th multiplier 12, accumulator 13, interval judging module 14, second divider 15, first delayer 16, second delayer 17 sum counter 18.
First filter 1 adopts the band of 5KHz to lead to FIR filter, and pass band width is 800Hz, and the second filter 2 adopts the band of 500Hz to lead to FIR filter, pass band width is 200Hz, a large amount of band external White noise of two filter filterings.In sinusoidal wave lock-in amplify unit, derived reference signal 8 adopts many wave generators DDS, wherein, DDS is for generation of the orthogonal reference signal of two-way, and the effect of phase shifter 9 to be their phase places of adjustment make it consistent with the measured signal phase place inputted, its realization is the address realization by changing DDS internal searching table.First multiplier 2 together completes homophase coherent filtering with first integrator 4, and the result of output is the product of the phase and magnitude difference cosine value of measured signal, and when signal is locked, phase difference is close to 0 phase place, and now Output rusults is the amplitude of measured signal.Second multiplier 3 completes quadrature component coherent filtering with second integral device 5, after semaphore lock, the output of this component is directly proportional to the sine value of phase difference, so export close to 0, this output valve can be used for judging whether reference signal has been locked in measured signal.The output of the first divider 6 is the tangent value of phase error, in order to obtain phase error, need to carry out arctangent cp cp operation, this computing is also not suitable for adopting Digital Logic to realize, native system utilizes table look-up device 7 in the mode of look-up table, by tangent value as address, and phase error is exported as the content corresponding to address, such arctangent cp cp operation to simplification.Look-up table address is totally 8, and in the worst cases, this computing has the error of 0.05 radian, very little on the impact of phase-locked precision, and gain is ideally 99.5%.Square-wave signal lock-in amplify unit, local square wave reference signal is produced by counter 18, counter 18 is by obtaining the square-wave signal of a certain frequency to the frequency division of clock, the time delay that this signal carries out certain clock cycle by the second delayer 17 can obtain the square wave reference signal orthogonal with the square wave reference signal that counter 18 directly exports, the effect of the first delayer 16 is the same with the effect of the phase-locked middle phase shifter 9 of sine wave, be used for adjusting the phase place of square wave reference signal, make it consistent with the tested square-wave signal phase place inputted.When square wave is phase-locked, the cumulative output symbol of the 3rd multiplier 11 and the 4th multiplier 12 can have four kinds of situations, these four kinds of situations are respectively for four phase error intervals, utilize interval judging module 14 can obtain the interval position of phase error, and export the numerical value of each interval for division arithmetic, second divider 15 adopt recycle ratio compared with method obtain both the integer numerical value of business, be used for control first delayer 16, make the square wave reference signal that produced by counter 18 consistent with measured signal phase place.The phase-locked phase-locked precision of this square wave can reach 0.04 radian, and corresponding gain is ideally 99.9%.The output of second integral device 5 and accumulator 13 is for judging whether local reference signal is locked in measured signal, and during locking, it is 0 that second integral device 5 exports with the quadrature component of accumulator 13.These signals can be observed by ChipScope on-line analysis technology.
Orthogonal lock-in-amplifier System Working Principle described in the utility model: first measured signal carries out filtering by the first filter 1 and the second filter 2, respectively the square wave small-signal obtained is sent into square wave lock-in amplify unit, the sinusoidal wave small-signal obtained is sent into sinusoidal wave lock-in amplify unit; Utilize counter 18 to produce the square wave reference signal of preset frequency, recycle the second delayer 17 and square wave reference signal is carried out phase delay, make by the square wave reference signal of the second delayer 17 orthogonal with the square wave reference signal that counter 18 directly exports.The square-wave signal to be measured that two-way square wave reference signal exports with the second filter 2 is respectively multiplied, the result access accumulator 13 obtained, judging module 14 and the second divider 15 between cumulative result bonding pad, interval judging module 14 provides each interval for the numeric reference of division arithmetic for the second divider 15.The phase difference of square wave reference signal and measured signal is calculated by the second divider 15, is input to the first delayer 16, is adjusted the square wave reference signal of counter output, make it consistent in phase place with the square wave content of measured signal by the first delayer 16.DDS exports the mutually orthogonal reference signal of two-way, the sine wave signal to be measured exported with the first filter 1 respectively after phase shift is multiplied, the result be multiplied is respectively through integrator sum-product intergrator, enter the first divider 6 after integration simultaneously, first divider 6 obtains the tangent value of phase difference, phase value is obtained through an arc tangent look-up table, this phase place adjusts by phase shifter 9 initial phase that DDS exports reference signal, makes itself and the first filter 1 export sine wave signal to be measured consistent in phase place.
Filter in native system, DDS, multiplier and table look-up device all adopt the mode of IP kernel to realize, and divider adopts simple and easy approximate division, namely only remains the integer part of business, only causes the gain loss of 0.5%.Native system completes square wave and sinusoidal wave lock-in amplify simultaneously, is all realized by FPGA, flexible when phase-locked debugging; Adopt quadrature technique, precision reaches 0.05 radian; Meanwhile, resource utilization is low, is applicable to Digital Implementation.
In sum, the utility model adopts and can complete square wave with sinusoidal wave phase-locked based on the orthogonal lock-in-amplifier system of FPGA simultaneously, and can ensure that phase-locked precision reaches the precision of 0.05 radian, improves the frequency marking precision of CPT atomic clock; Hardware resource utilization of the present utility model is low, can meet requirement that is miniaturized and low-power consumption; Whole design realizes at numeric field, utilizes on-line analysis technology to facilitate circuit debugging.
Obviously; above-described embodiment of the present utility model is only for the utility model example is clearly described; and be not the restriction to execution mode of the present utility model; for those of ordinary skill in the field; can also make other changes in different forms on the basis of the above description; here cannot give exhaustive to all execution modes, every belong to the technical solution of the utility model the apparent change of extending out or variation be still in the row of protection range of the present utility model.
Claims (8)
1. for an orthogonal lock-in-amplifier system for CPT atomic clock, it is characterized in that, this system comprises
Sinusoidal wave lock-in amplify unit, for carrying out sinusoidal wave lock-in amplify to measured signal; With
Square wave lock-in amplify unit, for carrying out square-wave signal lock-in amplify to measured signal.
2. a kind of orthogonal lock-in-amplifier system according to claim 1, it is characterized in that, this system comprises further
First filter, for carrying out filtering to measured signal, and obtains sine wave signal;
Second filter, for carrying out filtering to measured signal, and obtains square-wave signal.
3. a kind of orthogonal lock-in-amplifier system according to claim 2, is characterized in that,
Described first filter is the FIR filter that 5KHz band is logical, and its pass band width is 800Hz;
Described second filter is the FIR filter that 500Hz band is logical, and its pass band width is 200Hz.
4. a kind of orthogonal lock-in-amplifier system according to claim 1, is characterized in that, described sinusoidal wave lock-in amplify unit comprises
Derived reference signal, for generation of the reference signal that two-way is orthogonal;
Phase shifter, for adjusting reference signal phase place, makes it consistent with sine wave signal phase place to be measured;
First multiplier, for being multiplied with first via reference signal by sine wave signal to be measured, obtains amplitude and the phase difference cosine value product of measured signal after being multiplied;
Second multiplier, for being multiplied with the second tunnel reference signal by sine wave signal to be measured, obtains amplitude and the phase difference cosine value product of measured signal after being multiplied;
First divider, carries out division arithmetic for the product exported the first multiplier and the second multiplier, obtains the tangent value of the phase error of two product signals; With
Table look-up device, for the tangent value of described phase error is carried out arctangent cp cp operation, obtains phase error, and adjusts the initial phase of reference signal by this phase error;
5. a kind of orthogonal lock-in-amplifier system according to claim 1, is characterized in that, described sinusoidal wave lock-in amplify unit comprises further
Be connected to the first integrator between the first multiplier and the first divider;
Be connected to the second integral device between the second multiplier and the first divider.
6. a kind of orthogonal lock-in-amplifier system according to claim 1, is characterized in that, described sinusoidal wave lock-in amplify unit comprises
Counter, for time frequency division, obtains the square wave reference signal of preset frequency;
First delayer, for adjusting the phase place of square wave reference signal, makes all the other square-wave signal phase places to be measured consistent;
Second delayer, carries out time delay for the square wave reference signal directly will exported by counter, and produces the road square wave reference signal orthogonal with the square wave reference signal that counter directly exports;
3rd multiplier, is multiplied for the square wave reference signal directly exported by square-wave signal sum counter to be measured, obtains amplitude and the phase difference cosine value product of square-wave signal to be measured after being multiplied;
4th multiplier, for square-wave signal to be measured and the square wave reference signal orthogonal with the square wave reference signal that counter directly exports being multiplied, obtains amplitude and the phase difference cosine value product of square-wave signal to be measured after being multiplied;
Accumulator, adds up for the product exported the 3rd multiplier and the 4th multiplier, obtains four phase error intervals; With
Second divider, utilizes circulation comparison method to calculate the integer numerical value of business between any two, adjusts the first delayer by this integer numerical value, make square wave reference signal consistent with square-wave signal to be measured.
7. a kind of orthogonal lock-in-amplifier system according to claim 6, is characterized in that, described sinusoidal wave lock-in amplify unit also comprises the interval judging module be connected to before accumulator and the second divider.
8. one kind comprises the FPGA of orthogonal lock-in-amplifier system according to claim 1.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105549375A (en) * | 2016-01-29 | 2016-05-04 | 中国科学院长春光学精密机械与物理研究所 | High-precision satellite-borne time transfer system |
| CN107329052A (en) * | 2017-05-24 | 2017-11-07 | 国网辽宁省电力有限公司电力科学研究院 | An Estimation Method of Discharge Electromagnetic Wave Time Delay Based on Analog Signal |
| CN111443260A (en) * | 2020-04-24 | 2020-07-24 | 国网山西省电力公司吕梁供电公司 | Power grid phase difference detection method and system |
| CN114762301A (en) * | 2019-12-09 | 2022-07-15 | 三菱重工业株式会社 | Signal processing device, signal processing method, and signal processing program |
-
2014
- 2014-08-20 CN CN201420472193.6U patent/CN204168278U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105549375A (en) * | 2016-01-29 | 2016-05-04 | 中国科学院长春光学精密机械与物理研究所 | High-precision satellite-borne time transfer system |
| CN105549375B (en) * | 2016-01-29 | 2017-12-26 | 中国科学院长春光学精密机械与物理研究所 | The spaceborne Time Transmission system of high accuracy |
| CN107329052A (en) * | 2017-05-24 | 2017-11-07 | 国网辽宁省电力有限公司电力科学研究院 | An Estimation Method of Discharge Electromagnetic Wave Time Delay Based on Analog Signal |
| CN114762301A (en) * | 2019-12-09 | 2022-07-15 | 三菱重工业株式会社 | Signal processing device, signal processing method, and signal processing program |
| CN114762301B (en) * | 2019-12-09 | 2024-05-31 | 三菱重工业株式会社 | Signal processing device, signal processing method, and signal processing program |
| CN111443260A (en) * | 2020-04-24 | 2020-07-24 | 国网山西省电力公司吕梁供电公司 | Power grid phase difference detection method and system |
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