CN204144239U - The stack distribution structure of the high-power bare chip of a kind of homalographic - Google Patents
The stack distribution structure of the high-power bare chip of a kind of homalographic Download PDFInfo
- Publication number
- CN204144239U CN204144239U CN201420500232.9U CN201420500232U CN204144239U CN 204144239 U CN204144239 U CN 204144239U CN 201420500232 U CN201420500232 U CN 201420500232U CN 204144239 U CN204144239 U CN 204144239U
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- China
- Prior art keywords
- chip
- pad
- circuit substrate
- upper strata
- homalographic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The utility model discloses the stack distribution structure of the high-power bare chip of a kind of homalographic, comprise circuit substrate, bottom chip, pad and upper strata chip; The back side of bottom chip is gluedd joint by conducting resinl and circuit substrate, the back side of upper strata chip is welded with pad by solder, the another side of pad is gluedd joint by the front of insulating cement and bottom chip, is connected to bonding gold wire between the pad of the pad of bottom chip and the pad of circuit substrate, upper strata chip and the pad of circuit substrate.The utility model is without the need to custom-made laminated chips, pad can be made according to the pad distribution situation of common bare chip, achieve the lamination assembling of homalographic bare chip on the one hand, being beneficial to and realizing miniaturization, also meeting the radiating requirements of high-power chip on the other hand by increasing the good pad of heat conduction.
Description
Technical field
The utility model belongs to electronic assemblies field, particularly the stack distribution structure of the high-power bare chip of a kind of homalographic.
Background technology
Along with the increase of portable electronic system complexity, more and more higher requirement is proposed to the light-duty of VLSI integrated circuit and compact package technology, equally, many aviations and Military Application are also towards this future development, for meeting these requirements, on the two dimension encapsulation basis in X, Y plane, bare chip is laminated on together along Z axis, like this, in miniaturized, great improvement is just achieved.
The current mode realizing chip-stack roughly has several as follows, as the film conduction band on the peripheral interconnect between stacked strips IC, welding edge conduction band, cube face, folding type flexible circuit and wire bond laminated chips.Above-mentioned front four kinds of structures make it there is the problem such as very flexible, restricted application in actual applications by the reason such as special equipment, complicated operation due to needs, wire bond laminated chips structure is the general structure of current Application comparison, namely mother chip serves as the substrate of sub-chip, and chip bonding pad and circuit substrate are interconnected by wire bonding mode.The common feature of this structure is: a) mother chip area is greater than sub-chip, and sub-chip directly can be glued to the landless region of mother chip; B) chip bonding pad is staggered, and if chip is cuboid, lower layer chip pad is distributed in two edges, long limit, and upper strata chip bonding pad is distributed in two short side edge, upper and lower layers of chips square crossing lamination, and this kind of chip needs customization usually; C) directly use insulating cement to realize the interconnected of upper and lower layers of chips, be applicable to the chip not high to cooling requirements.And when need to carry out stack timing to area equation, bare chip that cooling requirements is high, the limitation of said structure just highlights.
Utility model content
In view of the limitation of traditional stack distribution structure, applicant through Improvement, provide a kind of applied widely, be easy to the stack distribution structure of the high-power bare chip of homalographic that realizes.
The technical solution of the utility model is as follows:
A stack distribution structure for the high-power bare chip of homalographic, comprises circuit substrate, bottom chip, pad and upper strata chip; The back side of bottom chip is gluedd joint by conducting resinl and circuit substrate, the back side of upper strata chip is welded with pad by solder, the another side of pad is gluedd joint by the front of insulating cement and bottom chip, is connected to bonding gold wire between the pad of the pad of bottom chip and the pad of circuit substrate, upper strata chip and the pad of circuit substrate.
Its further technical scheme is: described bottom chip is equal with upper strata chip area.
Its further technical scheme is: described pad is insulating material.
Its further technical scheme is: the diameter of described bonding gold wire is 25 μm.
Advantageous Effects of the present utility model is:
Assembly structure of the present utility model have employed the lamination assembling that both economical mode achieves common homalographic bare chip, solves the heat dissipation problem of high-power chip simultaneously.Solve the shortcoming of traditional die stack method of completing the square complicated operation, narrow application range.And the mounting technology of assembly structure of the present utility model involved by whole assembling process is mature technology, is easy to realize, has applied widely, advantage simple to operate.
Accompanying drawing explanation
Fig. 1 is overall structure figure of the present utility model.
Description of reference numerals: 1, circuit substrate; 2, conducting resinl; 3, bottom chip; 4, insulating cement; 5, pad; 6, solder; 7, upper strata chip; 8, bonding gold wire.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described further.
As shown in Figure 1, the utility model comprises circuit substrate 1, conducting resinl 2, bottom chip 3, insulating cement 4, pad 5, solder 6, upper strata chip 7 and bonding gold wire 8.The back side of bottom chip 3 is gluedd joint by conducting resinl 2 and circuit substrate 1, and the back side of upper strata chip 7 is welded with pad 5 by solder 6, and the another side of pad 5 is gluedd joint by the front of insulating cement 4 with bottom chip 3.Bottom chip 3 and upper strata chip 7 area equation.Pad 5 is insulating material and has good heat dissipation characteristics; The bottom shape of pad 5 should be to avoid bottom chip 3 surface pads, does not affect wire bonding; The top surface shape of pad 5 is identical with upper strata chip 7 profile, plays a supporting role to upper strata chip 7, and when avoiding upper strata chip 7 wire bonding, chopper power causes damage to chip.Bonding gold wire 8 is connected between the pad of the pad of bottom chip 3 and the pad of circuit substrate 1, upper strata chip 7 and the pad of circuit substrate 1.The diameter of bonding gold wire 8 is 25 μm.
Installation step of the present utility model is as follows:
1) use conducting resinl 2 that bottom chip 3 is glued to circuit substrate 1, and be heating and curing, condition of cure is 120 DEG C, 45min, realizes electrically and interconnected.
2) pad of bonding gold wire 8 Bonding interconnect bottom chip 3 and the pad of circuit substrate 1 of 25 μm is used.
3) use solder 6 upper strata chip 7 to be soldered to pad 5 to make it to become an independently chip part, and be heating and curing, condition of cure is 120 DEG C, 45min.
4) use DELA9218 insulating cement 4 by step 3) described in chip part be glued to bottom chip 3, and be heating and curing, condition of cure is 100 DEG C, 15min.
5) adopt hot pressing ultrasonic bonding technique, use the pad of bonding gold wire 8 Bonding interconnect upper strata chip 7 and the pad of circuit substrate 1 of 25 μm.
Above-described is only preferred implementation of the present utility model, and the utility model is not limited to above embodiment.Be appreciated that the oher improvements and changes that those skilled in the art directly derive or associate under the prerequisite not departing from spirit of the present utility model and design, all should think and be included within protection range of the present utility model.
Claims (4)
1. a stack distribution structure for the high-power bare chip of homalographic, is characterized in that: comprise circuit substrate (1), bottom chip (3), pad (5) and upper strata chip (7); The back side of bottom chip (3) is gluedd joint by conducting resinl (2) and circuit substrate (1), the back side of upper strata chip (7) is welded with pad (5) by solder (6), the another side of pad (5) is gluedd joint by the front of insulating cement (4) with bottom chip (3), is connected to bonding gold wire (8) between the pad of the pad of bottom chip (3) and the pad of circuit substrate (1), upper strata chip (7) and the pad of circuit substrate (1).
2. the stack distribution structure of the high-power bare chip of homalographic according to claim 1, is characterized in that: described bottom chip (3) and upper strata chip (7) area equation.
3. the stack distribution structure of the high-power bare chip of homalographic according to claim 1, is characterized in that: described pad (5) is insulating material.
4. the stack distribution structure of the high-power bare chip of homalographic according to claim 1, is characterized in that: the diameter of described bonding gold wire (8) is 25 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420500232.9U CN204144239U (en) | 2014-09-01 | 2014-09-01 | The stack distribution structure of the high-power bare chip of a kind of homalographic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420500232.9U CN204144239U (en) | 2014-09-01 | 2014-09-01 | The stack distribution structure of the high-power bare chip of a kind of homalographic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204144239U true CN204144239U (en) | 2015-02-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420500232.9U Expired - Fee Related CN204144239U (en) | 2014-09-01 | 2014-09-01 | The stack distribution structure of the high-power bare chip of a kind of homalographic |
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| Country | Link |
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| CN (1) | CN204144239U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108323009A (en) * | 2018-01-11 | 2018-07-24 | 南昌黑鲨科技有限公司 | Device structure and device layout |
| CN110132453A (en) * | 2019-05-28 | 2019-08-16 | 无锡莱顿电子有限公司 | A kind of pressure sensor bonding method |
-
2014
- 2014-09-01 CN CN201420500232.9U patent/CN204144239U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108323009A (en) * | 2018-01-11 | 2018-07-24 | 南昌黑鲨科技有限公司 | Device structure and device layout |
| CN110132453A (en) * | 2019-05-28 | 2019-08-16 | 无锡莱顿电子有限公司 | A kind of pressure sensor bonding method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150204 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |