CN204103896U - A kind of ring oscillator - Google Patents

Abstract

The utility model discloses a ring oscillator, which is mainly composed of three series-connected differential delay units D1-D3 and one injection unit INJ. A 180-degree phase shift is achieved from the input of the first delay unit to the output of the third series-connected delay unit, and multiple loop feedbacks reduce the delay time and further increase the oscillation frequency. The differential delay unit has a coarse adjustment circuit and a fine adjustment circuit, the coarse adjustment circuit is used to set the minimum time delay or the maximum time delay, and the fine adjustment circuit is used to adjust between the minimum time delay and the maximum time delay. The grid stage of the injection unit injects the sub-harmonic signal of the frequency of the output signal to improve the jitter performance of the oscillator. The utility model has a thick and fine double-tuning function with a wide frequency range, low voltage sensitivity, reduces the influence of bias voltage fluctuations, and can realize a low-jitter output clock signal, which can be applied to a wireless receiver frequency synthesizer or a clock data recovery circuit middle.

Description

a ring oscillator

technical field

The utility model belongs to the field of integrated circuit design, in particular to a ring oscillator.

Background technique

In recent years, electronic products are required to be able to meet the requirements of handheld multi-terminal communication, and almost all communication systems require a stable periodic signal, namely a clock, to provide the basic timing basis. These clock signals are typically generated by frequency synthesis techniques. The core of frequency synthesis technology is oscillator circuit design. There are generally two types of oscillator circuit structures: ring oscillators and LC oscillators. Because the circuit structure of the ring oscillator is simple, the process requirements are not high, and it is easy to integrate, so it has been widely used in the system on chip.

The ring oscillator is composed of several basic differential delay unit circuits connected to form a loop, which is divided into two types of circuit structures: single-ended and differential. Since the differential structure has better anti-noise capability, it is more widely used in high-speed PLLs.

As shown in Figure 1, a method for realizing frequency adjustment of a ring oscillator is a differential delay cell (A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications, IEEE Trans.Circuits Syst.I, Reg.Papers, vol.58, no.6, pp.1225–1238, 2011), in which the PMOS tube is used as a coarse and fine tuning tube to avoid the tail current source Flicker noise, improved tuning linearity. However, when the adjustment voltage becomes smaller and the oscillation frequency becomes higher, this adjustment method usually results in insufficient jitter performance.

Utility model content

The utility model aims to solve the problem that the jitter performance of the existing ring oscillator is not good enough, and provides a ring oscillator, that is, a ring oscillator with multiple feedback and double-tuning injection locking.

In order to solve the above problems, the utility model is achieved through the following technical solutions:

A ring oscillator mainly consists of three differential delay units D1-D3 and one injection unit INJ. The differential non-inverting output terminal VOUT+ of the first differential delay unit D1 is connected to the main loop inverting input terminal VP- of the second differential delay unit D2, and the differential non-inverting output terminal VOUT+ of the second differential delay unit D2 is connected to the third differential delay unit D3 The main loop inverting input terminal VP-, the differential non-inverting output terminal VOUT+ of the third differential delay unit D3 is connected to the main loop inverting input terminal VP- of the first differential delay unit D1. The differential inverting output terminal VOUT- of the first differential delay unit D1 is connected to the main loop non-inverting input terminal VP+ of the second differential delay unit D2, and the differential inverting output terminal VOUT- of the second differential delay unit D2 is connected to the third differential delay unit The main loop non-inverting input terminal VP+ of D3, the differential inverting output terminal VOUT− of the third differential delay unit D3 is connected to the main loop non-inverting input terminal VP+ of the first differential delay unit D1. The non-inverting input terminal VP+ of the main loop of the first differential delay unit D1 is connected to the non-inverting input terminal VS+ of the auxiliary loop of the second differential delay unit D2, and the inverting input terminal VP- of the main loop of the first differential delay unit D1 is connected to the second differential The auxiliary loop inverting input terminal VS- of the delay unit D2. The non-inverting input terminal VS+ of the auxiliary loop of the first differential delay unit D1 is connected to the non-inverting input terminal VP+ of the main loop of the third differential delay unit D3, and the inverting input terminal VS- of the auxiliary loop of the first differential delay unit D1 is connected to the third differential The main loop inverting input terminal VP- of the delay unit D3. The main loop non-inverting input terminal VP+ of the second differential delay unit D2 is connected to the auxiliary loop non-inverting input terminal VS+ of the third differential delay unit D3, and the auxiliary loop non-inverting input terminal VS+ of the second differential delay unit D2 is connected to the third differential delay unit Auxiliary loop inverting input VS- of D3. The coarse adjustment input terminal VCOARSE of the first differential delay unit D1, the coarse adjustment input terminal VCOARSE of the second differential delay unit D2 and the coarse adjustment input terminal VCOARSE of the third differential delay unit D3 are simultaneously connected to the coarse adjustment input signal VCOARSE. The fine-tuning input terminal VFINE of the first differential delay unit D1, the fine-tuning input terminal VFINE of the second differential delay unit D2 and the fine-tuning input terminal VFINE of the third differential delay unit D3 are simultaneously connected to the fine-tuning input signal VFINE. The power supply terminal VDD of the first differential delay unit D1, the power supply terminal VDD of the second differential delay unit D2 and the power supply terminal VDD of the third differential delay unit D3 are simultaneously connected to the power supply VDD. The ground terminal GND of the first differential delay unit D1, the ground terminal GND of the second differential delay unit D2 and the ground terminal GND of the third differential delay unit D3 are simultaneously grounded to GND. The gate of the injection unit INJ is connected to the injection signal input terminal VINJ, the drain of the injection unit INJ is connected to the differential inverting output terminal VOUT- of the third differential delay unit D3, and the source of the injection unit INJ is connected to the differential of the third differential delay unit D3 Non-inverting output VOUT+.

In the above solution, each differential delay unit includes 8 PMOS transistors PM1-PM4 and 4 NMOS transistors NM1-NM4. The source of the first PMOS transistor PM1, the source of the second PMOS transistor PM2, the source of the third PMOS transistor PM3, the source of the fourth PMOS transistor PM4, the source of the fifth PMOS transistor PM5, the sixth PMOS transistor PM6 The source of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are simultaneously connected to the power supply VDD. The source of the first NMOS transistor NM1, the source of the second NMOS transistor NM2, the source of the third NMOS transistor NM3, the source of the fourth NMOS transistor NM4, the gate of the third PMOS transistor PM3, and the fourth PMOS transistor PM4 The gate of the gate is grounded to GND at the same time. The gate of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2 as the coarse adjustment signal input terminal VCOARSE of the differential delay unit. The gate of the fifth PMOS transistor PM5 is connected to the gate of the sixth PMOS transistor PM6 as the fine adjustment signal input terminal VFINE of the differential delay unit. The drain of the first PMOS transistor PM1, the drain of the third PMOS transistor PM3, the drain of the fifth PMOS transistor PM5, the drain of the seventh PMOS transistor PM7, the drain of the first NMOS transistor NM1 and the third NMOS transistor NM3 The drain of is connected as the differential inverting output terminal VOUT- of the differential delay unit. The drain of the second PMOS transistor PM2, the drain of the fourth PMOS transistor PM4, the drain of the sixth PMOS transistor PM6, the drain of the eighth PMOS transistor PM8, the drain of the second NMOS transistor NM2 and the fourth NMOS transistor NM4 The drain of is connected as the differential non-inverting output terminal VOUT+ of the differential delay unit. The gate of the third NMOS transistor NM3 is connected to the drain of the second NMOS transistor NM2 and the drain of the fourth NMOS transistor NM4. The gate of the fourth NMOS transistor NM4 is connected to the drain of the first NMOS transistor NM1 and the drain of the third NMOS transistor NM3. The gate of the seventh PMOS transistor PM7 serves as the non-inverting input terminal VS+ of the auxiliary loop of the differential delay unit. The gate of the eighth PMOS transistor PM8 serves as the auxiliary loop inverting input terminal VS- of the differential delay unit. The gate of the first NMOS transistor NM1 serves as the non-inverting input terminal VP+ of the main loop of the differential delay unit. The gate of the second NMOS transistor NM2 is used as the inverting input terminal VP- of the main loop of the differential delay unit.

In the above solution, the width-to-length ratio of the first PMOS transistor PM1 and the second PMOS transistor PM2 is 5-10 times of the width-to-length ratio of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6.

The utility model comprises three series-connected differential delay units and an injection unit. A 180-degree phase shift is achieved from the input of the first delay unit to the output of the third series-connected delay unit, and multiple loop feedbacks reduce the delay time and further increase the oscillation frequency. The differential delay unit has a coarse adjustment circuit and a fine adjustment circuit, the coarse adjustment circuit is used to set the minimum time delay or the maximum time delay, and the fine adjustment circuit is used to adjust between the minimum time delay and the maximum time delay. The grid stage of the injection unit injects the sub-harmonic signal of the frequency of the output signal to improve the jitter performance of the oscillator. The utility model has a thick and fine double tuning function with a wide frequency range, low voltage sensitivity, reduces the influence of bias voltage fluctuations, and can realize a low-jitter output clock signal, which can be applied to a wireless receiver frequency synthesizer or a clock data recovery circuit middle.

Compared with the prior art, the utility model improves the voltage regulation structure of the differential delay unit circuit, and combines the use of loop feedforward technology, coarse and fine double tuning technology, and sub-harmonic injection locking technology. When the structure of the differential delay unit is determined, the delay is further reduced to achieve high-speed oscillation; through coarse adjustment and fine adjustment, low voltage sensitivity adjustment is realized within the frequency range that needs to be adjusted, reducing the interference of bias voltage fluctuations; injecting low voltage through the injection tube The jittered sub-harmonic oscillation signal improves the jitter performance of the oscillator and reduces the phase noise. It meets the low jitter requirements of mobile portable terminal communication.

Description of drawings

Fig. 1 is an existing DCVSL delay unit.

Fig. 2 is a structural diagram of a ring oscillator circuit of the present invention.

Fig. 3 is a circuit diagram of a differential delay unit of the present invention.

Fig. 4 is a comparison chart of the jitter performance of the utility model with or without injection locking, wherein (a) is without injection locking, and (b) is with injection locking.

Detailed ways

A ring oscillator, as shown in FIG. 2 , is mainly composed of three differential delay units D1-D3 and one injection unit INJ. The differential non-inverting output terminal VOUT+ of the first differential delay unit D1 is connected to the main loop inverting input terminal VP- of the second differential delay unit D2, and the differential non-inverting output terminal VOUT+ of the second differential delay unit D2 is connected to the third differential delay unit D3 The main loop inverting input terminal VP-, the differential non-inverting output terminal VOUT+ of the third differential delay unit D3 is connected to the main loop inverting input terminal VP- of the first differential delay unit D1. The differential inverting output terminal VOUT- of the first differential delay unit D1 is connected to the main loop non-inverting input terminal VP+ of the second differential delay unit D2, and the differential inverting output terminal VOUT- of the second differential delay unit D2 is connected to the third differential delay unit The main loop non-inverting input terminal VP+ of D3, the differential inverting output terminal VOUT− of the third differential delay unit D3 is connected to the main loop non-inverting input terminal VP+ of the first differential delay unit D1. The non-inverting input terminal VP+ of the main loop of the first differential delay unit D1 is connected to the non-inverting input terminal VS+ of the auxiliary loop of the second differential delay unit D2, and the inverting input terminal VP- of the main loop of the first differential delay unit D1 is connected to the second differential The auxiliary loop inverting input terminal VS- of the delay unit D2. The non-inverting input terminal VS+ of the auxiliary loop of the first differential delay unit D1 is connected to the non-inverting input terminal VP+ of the main loop of the third differential delay unit D3, and the inverting input terminal VS- of the auxiliary loop of the first differential delay unit D1 is connected to the third differential The main loop inverting input terminal VP- of the delay unit D3. The main loop non-inverting input terminal VP+ of the second differential delay unit D2 is connected to the auxiliary loop non-inverting input terminal VS+ of the third differential delay unit D3, and the auxiliary loop non-inverting input terminal VS+ of the second differential delay unit D2 is connected to the third differential delay unit Auxiliary loop inverting input VS- of D3. The coarse adjustment input terminal VCOARSE of the first differential delay unit D1, the coarse adjustment input terminal VCOARSE of the second differential delay unit D2 and the coarse adjustment input terminal VCOARSE of the third differential delay unit D3 are simultaneously connected to the coarse adjustment input signal VCOARSE. The fine-tuning input terminal VFINE of the first differential delay unit D1, the fine-tuning input terminal VFINE of the second differential delay unit D2 and the fine-tuning input terminal VFINE of the third differential delay unit D3 are simultaneously connected to the fine-tuning input signal VFINE. The power supply terminal VDD of the first differential delay unit D1, the power supply terminal VDD of the second differential delay unit D2 and the power supply terminal VDD of the third differential delay unit D3 are simultaneously connected to the power supply VDD. The ground terminal GND of the first differential delay unit D1, the ground terminal GND of the second differential delay unit D2 and the ground terminal GND of the third differential delay unit D3 are simultaneously grounded to GND. The gate of the injection unit INJ is connected to the injection signal input terminal VINJ, the drain of the injection unit INJ is connected to the differential inverting output terminal VOUT- of the third differential delay unit D3, and the source of the injection unit INJ is connected to the differential of the third differential delay unit D3 Non-inverting output VOUT+.

Each of the above differential delay units includes 8 PMOS transistors PM1-PM4 and 4 NMOS transistors NM1-NM4. The source of the first PMOS transistor PM1, the source of the second PMOS transistor PM2, the source of the third PMOS transistor PM3, the source of the fourth PMOS transistor PM4, the source of the fifth PMOS transistor PM5, the sixth PMOS transistor PM6 The source of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are simultaneously connected to the power supply VDD. The source of the first NMOS transistor NM1, the source of the second NMOS transistor NM2, the source of the third NMOS transistor NM3, the source of the fourth NMOS transistor NM4, the gate of the third PMOS transistor PM3, and the fourth PMOS transistor PM4 The gate of the gate is grounded to GND at the same time. The gate of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2 as the coarse adjustment signal input terminal VCOARSE of the differential delay unit. The gate of the fifth PMOS transistor PM5 is connected to the gate of the sixth PMOS transistor PM6 as the fine adjustment signal input terminal VFINE of the differential delay unit. The drain of the first PMOS transistor PM1, the drain of the third PMOS transistor PM3, the drain of the fifth PMOS transistor PM5, the drain of the seventh PMOS transistor PM7, the drain of the first NMOS transistor NM1 and the third NMOS transistor NM3 The drain of is connected as the differential inverting output terminal VOUT- of the differential delay unit. The drain of the second PMOS transistor PM2, the drain of the fourth PMOS transistor PM4, the drain of the sixth PMOS transistor PM6, the drain of the eighth PMOS transistor PM8, the drain of the second NMOS transistor NM2 and the fourth NMOS transistor NM4 The drain of is connected as the differential non-inverting output terminal VOUT+ of the differential delay unit. The gate of the third NMOS transistor NM3 is connected to the drain of the second NMOS transistor NM2 and the drain of the fourth NMOS transistor NM4. The gate of the fourth NMOS transistor NM4 is connected to the drain of the first NMOS transistor NM1 and the drain of the third NMOS transistor NM3. The gate of the seventh PMOS transistor PM7 serves as the non-inverting input terminal VS+ of the auxiliary loop of the differential delay unit. The gate of the eighth PMOS transistor PM8 serves as the auxiliary loop inverting input terminal VS- of the differential delay unit. The gate of the first NMOS transistor NM1 serves as the non-inverting input terminal VP+ of the main loop of the differential delay unit. The gate of the second NMOS transistor NM2 is used as the inverting input terminal VP- of the main loop of the differential delay unit. See Figure 3.

In order to adapt to the continuous reduction of the working voltage and reduce its interference noise, the differential delay unit of the present invention removes the tail current tube, thus eliminating the requirement for additional bias voltage. The width-to-length ratio of the first PMOS transistor PM1 and the second PMOS transistor PM2 is set to be 5 to 10 times the width-to-length ratio of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6, so as to facilitate coarse and fine tuning of the oscillation frequency. The gates of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are grounded, so that PM3 and PM4 work in a saturation region, thereby realizing rail-to-rail voltage regulation and expanding the voltage regulation range. The third NMOS transistor NM3 and the fourth NMOS transistor NM4 form a cross-coupling connection to maintain oscillation, which not only improves the switching speed, but also improves the linearity.

The working principle of the utility model is as follows:

In the normal oscillation cycle, when the voltage of the non-inverting input terminal VP+ of the main loop of each differential delay unit is high and the voltage of the inverting input terminal VP- of the main loop is low, the first NMOS transistor NM1 is turned on, and the second NMOS transistor NM1 is turned on. NM2 cut off. At this time, the fourth NMOS transistor NM4 whose gate is controlled by the differential inverting output terminal VOUT- will also be turned on, and the differential non-inverting output terminal VOUT+ will be pulled to the power supply VDD. The first PMOS transistor PM1, the third PMOS transistor PM3, and the fifth The currents of the PMOS transistor PM5 and the seventh PMOS transistor PM7 will all flow through the third NMOS transistor NM3 and the first NMOS transistor NM1, and the working states of the left branch and the right branch will alternate in sequence to complete an oscillation cycle.

The differential signal output by the differential non-inverting output terminal VOUT+ and the differential inverting output terminal VOUT- of the first differential delay unit D1 is input through the main loop non-inverting input terminal VP+ and the main loop inverting input terminal VP- of the second differential delay unit D2 Afterwards, the voltage frequency is controlled by the coarse adjustment input signal VCOARSE and the fine adjustment input signal VFINE, and the phase delay of the output signal of the second differential delay unit D2 relative to the output signal of the first differential delay unit D1 by 60 degrees is realized. The differential signal output by the differential non-inverting output terminal VOUT+ and the differential inverting output terminal VOUT- of the second differential delay unit D2 is input through the main loop non-inverting input terminal VP+ and the main loop inverting input terminal VP- of the third differential delay unit D3 Finally, the voltage frequency is controlled by the coarse adjustment input signal VCOARSE and the fine adjustment input signal VFINE, and the output signal of the third differential delay unit D3 is delayed by 120 degrees relative to the input signal of the second differential delay unit D2, and the phase delay of the first differential delay unit D1 is realized. The phase of the input signal is delayed by 180 degrees, and because the third differential delay unit D3 has a phase shift of 180 degrees when it is negatively fed back to the first delay unit D1, the signal finally meets the condition of a 360-degree phase shift required for Barkhausen oscillation, thereby finally realizing the entire function of the ring oscillation. At the same time, the non-inverting input terminal VS+ and the inverting input terminal VS- of the auxiliary loop of the first differential delay unit D1 transmit signals to the second differential delay unit D2 and the third differential delay unit D3 in advance through feedforward. The non-inverting input terminal VS+ and the inverting input terminal VS- of the auxiliary loop of the second differential delay unit D2 transmit the signal to the third differential delay unit D3 and the first differential delay unit D1 in advance in a feed-forward manner. The non-inverting input terminal VS+ and the inverting input terminal VS- of the auxiliary loop of the third differential delay unit D3 transmit the signal to the first differential delay unit D1 and the second differential delay unit D2 in advance in a feed-forward manner. In this way, the delay time of each differential delay unit for transmitting signals in the main loop is reduced, and the operating frequency of the oscillator is further improved. If the delay time of each differential delay unit is td, then the oscillation frequency of the three-stage differential oscillation is f=1/(2*3*td).

Considering that the jitter of the ring oscillator is larger than that of the LC oscillator, the utility model connects an injection signal unit to the differential output end of the third differential delay unit D3, and the injected signal is the subharmonic of the output frequency of the ring oscillator Signal, that is, use a low-jitter signal to perform a phase correction on the output signal every N cycles of the output signal, thereby avoiding the accumulation of phase errors and effectively reducing the signal jitter output by the ring oscillator. Figure 4(a) and (b) provide a comparison of the jitter performance with or without injection locking. The signal injected into the gate of the injection unit is the sub-harmonic of the output signal, which is expressed in the time domain as the accumulation of the phase error of the oscillation signal. Correction, jitter performance is significantly improved in the range of injection locking.

Claims (3)

1. A ring oscillator, characterized in that: it mainly consists of 3 differential delay units D1～D3 and 1 injection unit INJ; The differential non-inverting output terminal VOUT+ of the first differential delay unit D1 is connected to the main loop inverting input terminal VP- of the second differential delay unit D2, and the differential non-inverting output terminal VOUT+ of the second differential delay unit D2 is connected to the third differential delay unit D3 The main loop inverting input terminal VP-, the differential non-inverting output terminal VOUT+ of the third differential delay unit D3 is connected to the main loop inverting input terminal VP- of the first differential delay unit D1; The differential inverting output terminal VOUT- of the first differential delay unit D1 is connected to the main loop non-inverting input terminal VP+ of the second differential delay unit D2, and the differential inverting output terminal VOUT- of the second differential delay unit D2 is connected to the third differential delay unit The main loop non-inverting input terminal VP+ of D3, the differential inverting output terminal VOUT- of the third differential delay unit D3 is connected to the main loop non-inverting input terminal VP+ of the first differential delay unit D1; The non-inverting input terminal VP+ of the main loop of the first differential delay unit D1 is connected to the non-inverting input terminal VS+ of the auxiliary loop of the second differential delay unit D2, and the inverting input terminal VP- of the main loop of the first differential delay unit D1 is connected to the second differential The auxiliary loop inverting input terminal VS- of the delay unit D2; The non-inverting input terminal VS+ of the auxiliary loop of the first differential delay unit D1 is connected to the non-inverting input terminal VP+ of the main loop of the third differential delay unit D3, and the inverting input terminal VS- of the auxiliary loop of the first differential delay unit D1 is connected to the third differential The inverting input terminal VP- of the main loop of the delay unit D3; The main loop non-inverting input terminal VP+ of the second differential delay unit D2 is connected to the auxiliary loop non-inverting input terminal VS+ of the third differential delay unit D3, and the auxiliary loop non-inverting input terminal VS+ of the second differential delay unit D2 is connected to the third differential delay unit The inverting input terminal VS- of the auxiliary loop of D3; The coarse adjustment input terminal VCOARSE of the first differential delay unit D1, the coarse adjustment input terminal VCOARSE of the second differential delay unit D2 and the coarse adjustment input terminal VCOARSE of the third differential delay unit D3 are simultaneously connected to the coarse adjustment input signal VCOARSE; The fine-tuning input terminal VFINE of the first differential delay unit D1, the fine-tuning input terminal VFINE of the second differential delay unit D2 and the fine-tuning input terminal VFINE of the third differential delay unit D3 are simultaneously connected to the fine-tuning input signal VFINE; The power supply terminal VDD of the first differential delay unit D1, the power supply terminal VDD of the second differential delay unit D2 and the power supply terminal VDD of the third differential delay unit D3 are simultaneously connected to the power supply VDD; the ground terminal GND of the first differential delay unit D1, the second The ground terminal GND of the differential delay unit D2 and the ground terminal GND of the third differential delay unit D3 are simultaneously grounded to GND; The gate of the injection unit INJ is connected to the injection signal input terminal VINJ, the drain of the injection unit INJ is connected to the differential inverting output terminal VOUT- of the third differential delay unit D3, and the source of the injection unit INJ is connected to the differential of the third differential delay unit D3 Non-inverting output VOUT+. 2. A ring oscillator according to claim 1, characterized in that: Each of the above differential delay units includes 8 PMOS transistors PM1~PM4 and 4 NMOS transistors NM1~NM4; the source stage of the first PMOS transistor PM1, the source stage of the second PMOS transistor PM2, and the source stage of the third PMOS transistor PM3 , the source stage of the fourth PMOS transistor PM4, the source stage of the fifth PMOS transistor PM5, the source stage of the sixth PMOS transistor PM6, the source stage of the seventh PMOS transistor PM7 and the source stage of the eighth PMOS transistor PM8 are simultaneously connected to the power supply VDD; The source of the first NMOS transistor NM1, the source of the second NMOS transistor NM2, the source of the third NMOS transistor NM3, the source of the fourth NMOS transistor NM4, the gate of the third PMOS transistor PM3, and the fourth PMOS transistor PM4 The grid of the first PMOS transistor PM1 is connected to the grid of the second PMOS transistor PM2, which is used as the coarse adjustment signal input terminal VCOARSE of the differential delay unit; the grid of the fifth PMOS transistor PM5 and the sixth The gate of the PMOS transistor PM6 is connected as the fine-tuning signal input terminal VFINE of the differential delay unit; the drain of the first PMOS transistor PM1, the drain of the third PMOS transistor PM3, the drain of the fifth PMOS transistor PM5, the seventh The drain of the PMOS transistor PM7, the drain of the first NMOS transistor NM1 and the drain of the third NMOS transistor NM3 are connected as the differential inverting output terminal VOUT- of the differential delay unit; the drain of the second PMOS transistor PM2, the fourth The drain of the PMOS transistor PM4, the drain of the sixth PMOS transistor PM6, the drain of the eighth PMOS transistor PM8, the drain of the second NMOS transistor NM2 and the drain of the fourth NMOS transistor NM4 are connected as a differential delay unit Non-inverting output terminal VOUT+; the gate of the third NMOS transistor NM3 is connected to the drain of the second NMOS transistor NM2 and the drain of the fourth NMOS transistor NM4; the gate of the fourth NMOS transistor NM4 is connected to the drain of the first NMOS transistor NM1 It is connected to the drain of the third NMOS transistor NM3; the gate of the seventh PMOS transistor PM7 is used as the non-inverting input terminal VS+ of the auxiliary loop of the differential delay unit; the gate of the eighth PMOS transistor PM8 is used as the inverting phase of the auxiliary loop of the differential delay unit The input terminal VS-; the gate of the first NMOS transistor NM1 is used as the non-inverting input terminal VP+ of the main loop of the differential delay unit; the gate of the second NMOS transistor NM2 is used as the inverting input terminal VP- of the main loop of the differential delay unit. 3. A ring oscillator according to claim 2, characterized in that: the width-to-length ratio of the first PMOS transistor PM1 and the second PMOS transistor PM2 is equal to the width-to-length ratio of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 5 to 10 times of that.