CN203890050U - Micro electro mechanical system and detection circuit - Google Patents
Micro electro mechanical system and detection circuit Download PDFInfo
- Publication number
- CN203890050U CN203890050U CN201320892445.6U CN201320892445U CN203890050U CN 203890050 U CN203890050 U CN 203890050U CN 201320892445 U CN201320892445 U CN 201320892445U CN 203890050 U CN203890050 U CN 203890050U
- Authority
- CN
- China
- Prior art keywords
- switch
- signal
- circuit
- capacitor
- self
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Measurement Of Resistance Or Impedance (AREA)
Abstract
The utility model provides a micro electro mechanical system and a detection circuit. Self-testing capacitor arrays in the detection circuit output periodically changed charges, so when the self-testing of the detection circuit is carried out, the operation can be carried out through the periodically changed charges output by the self-testing capacitor arrays, and the condition that the detection circuit driving module needs to generate high-pressure driving signals so that micro electro mechanical self-testing capacitors arranged in a micro electro mechanical sensor output periodical charge signals required by the self-testing is avoided. Therefore the participation of the micro electro mechanical sensor is not needed in the self-testing process of the detection circuit, the self-testing flow process of the detection circuit is simplified, and in addition, the self-testing reliability is improved; meanwhile, micro electro mechanical self-testing capacitors are also not needed in the micro electro mechanical sensor, so the design complexity of the micro electro mechanical sensor and the design difficulty of the detection circuit driving module are reduced.
Description
Technical Field
The utility model relates to an integrated circuit technical field, in particular to micro-electromechanical system and detection circuitry.
Background
Micro-electro-mechanical systems (MEMS) are increasingly used, which mainly include a micro-mechanical sensor and a detection circuit, wherein the micro-mechanical sensor needs the detection circuit to detect the change of the sensor and perform corresponding signal processing. Most of the micro-mechanical sensors adopt a capacitance sensing mode, and a detection circuit corresponding to the capacitance sensing mode is used for detecting capacitance change of a micro-mechanical sensing capacitor. In the initial stage of the design of the micro-electromechanical system, it is necessary to determine whether the micro-mechanical sensor and the detection circuit can work normally. The micro mechanical sensor can be tested by a special detection method, but the detection circuit can preferably have a self-test method to judge the quality of the micro mechanical sensor; in addition, in the using process, if the whole micro-electromechanical system is damaged, the self-test function of the detection circuit can also judge whether the micro-electromechanical system is damaged by the micro-mechanical sensor or the detection circuit.
At present, a plurality of micro-electromechanical systems realize the capacitance required by the self-test function of a detection circuit by adopting a micro machine and manufacture the capacitance in a micro-mechanical sensor, so that higher complexity is brought to the design of the micro machine of the micro-mechanical sensor; in addition, driving the micromechanical self-test capacitor generally requires a higher voltage, which increases the difficulty for the driving module of the detection circuit; furthermore, the self-test requires the micromechanical sensor to be involved, which requires the micromechanical sensor to be tested without damage.
Please refer to fig. 1, which is a schematic structural diagram of a conventional mems. As shown in fig. 1, the mems includes a detection circuit 10 and a micromechanical sensor 20, wherein a micromechanical self-test capacitor 21 and a micromechanical sensor capacitor 22 are integrated to form the micromechanical sensor 20; the micromechanical self-test capacitor 21 is the same as the micromechanical sensor capacitor 22. During self-testing, a required self-testing high-voltage driving signal is added to a polar plate of the micro-mechanical self-testing capacitor 21 through the driving module 11; then, the signal reading and processing module 12 of the detection circuit 10 reads the change of the capacitance, and the change of the capacitance is finally reflected at the output end of the signal reading and processing module 12, and is a voltage value different from that in a non-test state under a normal condition; and finally, judging whether the detection circuit 10 works normally or not according to the voltage value.
Thus, the self-test of the detection circuit 10 must be established under the condition that the micro-mechanical sensor 20 can work normally, and if the micro-mechanical sensor 20 cannot work normally due to various reasons, the self-test function of the detection circuit 10 cannot be completed independently; and a high-voltage driving signal required by the self-test of the detection circuit 10 needs to be additionally provided, and the driving signal sometimes needs to be synchronized with a sampling and reading clock of the micromechanical sensor 20, so that the design complexity of the circuit is increased.
Further, please refer to fig. 2, which is a schematic diagram illustrating a self-test implemented by a micro-machine of a conventional micro-mechanical sensor. As shown in fig. 2, 1S and 2S are electrical signal input terminals for self-testing high voltage driving signals, 1I and 2I are micromechanical sensor charge output terminals, and the pair of output terminals is connected with a signal reading and processing module of the detection circuit. Applying a drive signal (e.g., sinusoidal voltage signal) to the 1S and 2S self-test inputs, the sinusoidal voltage signal generating an electrostatic force F through the micromechanical self-test capacitive platesEElectrostatic force FEThe micro-mechanical sensor capacitor is pushed to do sinusoidal vibration, sinusoidally changed charges are output from the 1I and the 2I, the charges are converted into voltage signals through a signal reading and processing module of the detection micro-mechanical sensor, and finally a corresponding voltage value is output to finish self-test.
The existing detection circuit has the big problems that the self-test function cannot be independently completed, and a micro-mechanical sensor needs to be leaned on, so that the inconvenience of a self-test flow and low reliability are caused; in addition, the design difficulty of the detection circuit driving module is increased due to the need of providing high-voltage and synchronous driving signals; the micromechanical sensor also has a set of comb-shaped micromechanical self-test capacitors, so that the design complexity of the micromechanical sensor is increased.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a micro electro mechanical system and a detection circuit, which aims to solve the problems that in the prior art, the detection circuit can not independently complete the self-test function, and needs to lean on a micro mechanical sensor, thus causing inconvenience and low reliability of the self-test flow; in addition, the design difficulty of the detection circuit driving module is increased due to the need of providing high-voltage and synchronous driving signals; the micro-mechanical sensor also solves the problem of increasing the design complexity of the micro-mechanical sensor because a group of comb-shaped micro-mechanical self-test capacitors are additionally designed.
In order to solve the above problem, the present invention provides a micro electro mechanical system, the micro electro mechanical system includes: the detection circuit is connected with the micromechanical sensor; wherein,
the micromechanical sensor comprises a micromechanical sensing capacitance;
the detection circuit includes: the device comprises a self-test capacitor array and a signal reading and processing module connected with the self-test capacitor array; wherein,
the self-test capacitor array is used for outputting periodically-changed charges;
the signal reading and processing module comprises: a charge amplifier, a demodulator and a low-pass filter connected in sequence; the signal reading and processing module is used for outputting a voltage signal according to the periodically changed charges output by the self-test capacitor array, and the voltage signal is used for judging whether the detection circuit works normally or not so as to complete the self-test function.
Optionally, in the mems, the self-test capacitor array includes a magnitude circuit and a period implementation circuit connected to the magnitude circuit; wherein,
the amplitude circuit is used for generating half-cycle change charges with only positive half-cycle change;
the cycle enabling circuit is configured to convert half-cycle varying charge having only positive half-cycles alternating to periodically varying charge having both positive and negative half-cycles.
Optionally, in the micro electro mechanical system, the amplitude circuit includes a first circuit group, the first circuit group includes a plurality of groups of capacitor groups connected in parallel, each group of capacitor groups includes a capacitor, a first switch connected to the capacitor, a second switch connected to the capacitor, and a common mode level Vcm connected to the second switch, wherein a turn-on signal of the first switch is opposite to a turn-on signal of the second switch.
Optionally, in the micro-electromechanical system, a plurality of capacitance values in a plurality of groups of parallel capacitor groups change in a sine wave or a triangular wave manner, and the capacitances in different capacitor groups are selected at different times, so that a half sine wave period change charge or a half triangular wave period change charge with only positive half period change is generated.
Optionally, in the micro electro mechanical system, the amplitude circuit further includes n +1 first adjusting circuits, n second adjusting circuits, and a third adjusting circuit connected in series with the first circuit group, where n is a natural number, and the first adjusting circuit includes a capacitor and a switch controlled by a reset signal connected in parallel, and a common mode level Vcm connected to the capacitor and the switch; the second regulating circuit comprises a capacitor; the third regulating circuit comprises a plurality of groups of capacitor groups connected in parallel, and each group of capacitor groups comprises a capacitor, a third switch connected with the capacitor, a fourth switch connected with the capacitor and a reference level V connected with the fourth switchrefWherein an on signal of the third switch is opposite to an on signal of the fourth switch.
Optionally, in the mems, the amplitude circuit further includes a third adjusting circuit connected in series with the first circuit group, anda fourth regulating circuit, wherein the third regulating circuit comprises a plurality of groups of capacitor sets connected in parallel, each group of capacitor sets comprises a capacitor, a third switch connected with the capacitor, a fourth switch connected with the capacitor and a reference level V connected with the fourth switchrefWherein an on signal of the third switch is opposite to an on signal of the fourth switch; the fourth regulating circuit comprises a switch controlled by a reset signal and a common mode level Vcm connected with the switch.
Optionally, in the mems, the period realization circuit includes a first branch and a second branch connected in parallel with the first branch, wherein,
the first branch comprises a fifth switch and a reference level Vcom connected with the fifth switch;
the second branch circuit comprises a sixth switch and a ground level GND connected with the sixth switch; the opening signal of the sixth switch is opposite to the opening signal of the fifth switch.
Optionally, in the mems, the circuit for forming the on signal of the fifth switch includes: the first parallel circuit comprises a first generating circuit and a second generating circuit which are connected in parallel, the first generating circuit comprises a switch controlled by a sign control signal PH _ Vsin, and the switch controlled by the sign control signal PH _ Vsin is connected with a reading signal PH _ RS; the second generating circuit comprises an inverted signal of a signed control signalControlled switch, said sign-controlled signal being an inverted signalControlled switch and an inverted signal of a read signalConnecting;
the circuit for forming the opening signal of the sixth switch comprises: a second parallel circuit including a third generating circuit and a fourth generating circuit connected in parallel, the third generating circuit including a switch controlled by a sign control signal PH _ Vsin, the switch controlled by the sign control signal PH _ Vsin, and an inverted signal of a read signalConnecting; the fourth generating circuit includes an inverted signal of the sign-controlled signalControlled switch, said sign-controlled signal being an inverted signalThe controlled switch is connected to a read signal PH _ RS.
Optionally, in the mems, the circuit for forming the on signal of the fifth switch further includes a buffer connected to the first parallel circuit; the circuit for forming the on signal of the sixth switch further includes a buffer connected to the second parallel circuit.
Optionally, in the micro-electro-mechanical system,
during the high level of the sign control signal PH _ Vsin, when the charge amplifier is in the reset state, the terminal b is grounded, the terminal a is a virtual ground, and the charges of the two terminals ba are 0, and when the charge amplifier is in the read state, the terminal b is Vcom, the terminal a is a virtual ground, and the charges of the two terminals ba are Vcom Cba, so that the charges Q between the terminals b and abaIncreased Vcom Cba compared to the previous reset state;
during the period that the sign control signal PH _ Vsin is at low level, when the charge amplifier is in reset state, the terminal b is connected with Vcom, the terminal a is virtual ground, the charges at the two terminals ba are Vcom x Cba, when the charge amplifier is in read state, the terminal b is connected with GND, and the terminal a is virtual groundThe electric charge at both ends ba is 0, whereby the electric charge Q between both ends b and abaincreased-Vcom Cba compared to the previous Reset state;
wherein Cba is the capacitance value of ba at both ends.
Optionally, in the micro electro mechanical system, the number of the self-test capacitor arrays is two, and the two self-test capacitor arrays form a differential structure.
Optionally, in the mems, the charge amplifier, the demodulator, and the low-pass filter are all differential structures.
The utility model also provides a detection circuitry, detection circuitry includes: the device comprises a self-test capacitor array and a signal reading and processing module connected with the self-test capacitor array; wherein,
the self-test capacitor array is used for outputting periodically-changed charges;
the signal reading and processing module comprises: a charge amplifier, a demodulator and a low-pass filter connected in sequence; the signal reading and processing module is used for outputting a voltage signal according to the periodically changed charges output by the self-test capacitor array, and the voltage signal is used for judging whether the detection circuit works normally or not so as to complete the self-test function.
Optionally, in the detection circuit, the self-test capacitor array includes an amplitude circuit and a cycle realization circuit connected to the amplitude circuit; wherein,
the amplitude circuit is used for generating half-cycle change charges with only positive half-cycle change;
the cycle enabling circuit is configured to convert half-cycle varying charge having only positive half-cycles alternating to periodically varying charge having both positive and negative half-cycles.
Optionally, in the detection circuit, the amplitude circuit includes a first circuit group, the first circuit group includes a plurality of groups of capacitor groups connected in parallel, each group of capacitor groups includes a capacitor, a first switch connected to the capacitor, a second switch connected to the capacitor, and a common mode level Vcm connected to the second switch, where an on signal of the first switch is opposite to an on signal of the second switch.
Optionally, in the detection circuit, a plurality of capacitance values in a plurality of groups of parallel capacitor groups change in a sine wave or a triangular wave manner, and the capacitances in different capacitor groups are selected at different times, so that a half sine wave period change charge or a half triangular wave period change charge with only positive half period change is generated.
Optionally, in the detection circuit, the amplitude circuit further includes n +1 first adjusting circuits, n second adjusting circuits, and a third adjusting circuit connected in series with the first circuit group, where n is a natural number, and the first adjusting circuit includes a capacitor and a switch controlled by a reset signal connected in parallel, and a common mode level Vcm connected to the capacitor and the switch; the second regulating circuit comprises a capacitor; the third regulating circuit comprises a plurality of groups of capacitor groups connected in parallel, and each group of capacitor groups comprises a capacitor, a third switch connected with the capacitor, a fourth switch connected with the capacitor and a reference level V connected with the fourth switchrefWherein an on signal of the third switch is opposite to an on signal of the fourth switch.
Optionally, in the detection circuit, the amplitude circuit further includes a third adjusting circuit and a fourth adjusting circuit connected in series with the first circuit group, where the third adjusting circuit includes a plurality of groups of capacitors connected in parallel, and each group of capacitors includes a capacitor, a third switch connected to the capacitor, a fourth switch connected to the capacitor, and a reference level V connected to the fourth switchrefWherein an on signal of the third switch is opposite to an on signal of the fourth switch; the fourth regulating circuit comprises a switch controlled by a reset signal and a common mode level Vcm connected with the switch.
Optionally, in the detection circuit, the period implementation circuit includes a first branch and a second branch connected in parallel with the first branch, wherein,
the first branch comprises a fifth switch and a reference level Vcom connected with the fifth switch;
the second branch circuit comprises a sixth switch and a ground level GND connected with the sixth switch; the opening signal of the sixth switch is opposite to the opening signal of the fifth switch.
Optionally, in the detection circuit, the circuit for forming the on signal of the fifth switch includes: the first parallel circuit comprises a first generating circuit and a second generating circuit which are connected in parallel, the first generating circuit comprises a switch controlled by a sign control signal PH _ Vsin, and the switch controlled by the sign control signal PH _ Vsin is connected with a reading signal PH _ RS; the second generating circuit comprises an inverted signal of a signed control signalControlled switch, said sign-controlled signal being an inverted signalControlled switch and an inverted signal of a read signalConnecting;
the circuit for forming the opening signal of the sixth switch comprises: a second parallel circuit including a third generating circuit and a fourth generating circuit connected in parallel, the third generating circuit including a switch controlled by a sign control signal PH _ Vsin, the switch controlled by the sign control signal PH _ Vsin, and an inverted signal of a read signalConnecting; the fourth generating circuit includes an inverted signal of the sign-controlled signalControlled switch, said sign-controlled signal being an inverted signalThe controlled switch is connected to a read signal PH _ RS.
Optionally, in the detection circuit, the circuit for forming the on signal of the fifth switch further includes a buffer connected to the first parallel circuit; the circuit for forming the on signal of the sixth switch further includes a buffer connected to the second parallel circuit.
Optionally, in the detection circuit,
during the high level of the sign control signal PH _ Vsin, when the charge amplifier is in the reset state, the terminal b is grounded, the terminal a is a virtual ground, and the charges of the two terminals ba are 0, and when the charge amplifier is in the read state, the terminal b is Vcom, the terminal a is a virtual ground, and the charges of the two terminals ba are Vcom Cba, so that the charges Q between the terminals b and abaIncreased Vcom Cba compared to the previous reset state;
during the period when the sign control signal PH _ Vsin is at low level, when the charge amplifier is in reset state, the terminal b is connected with Vcom, the terminal a is virtual ground, the charges of the two terminals ba are Vcom × Cba, when the charge amplifier is in read state, the terminal b is connected with GND, the terminal a is virtual ground, the charges of the two terminals ba are 0, thereby the charges Q between the two terminals b and a are all equalbaincreased-Vcom Cba compared to the previous Reset state;
wherein Cba is the capacitance value of ba at both ends.
Optionally, in the detection circuit, the number of the self-test capacitor arrays is two, and the two self-test capacitor arrays form a differential structure.
Optionally, in the detection circuit, the charge amplifier, the demodulator, and the low-pass filter are all differential structures.
The utility model provides an among micro electro mechanical system and detection circuitry, through the charge of the periodic variation of self test capacitor array output among the detection circuitry, from this when carrying out the self test of detection circuitry, through the periodic variation's of self test capacitor array output charge can go on, thereby avoided needing detection circuitry drive module to produce high pressure drive signal and made the micromachine in the micromechanical sensor from the periodic charge signal that the test of test capacitor output self test needs, from this detection circuitry's self test process no longer needs micromechanical sensor to participate in, simplified detection circuitry's self test flow, and improved the self test reliability; meanwhile, a micro-mechanical self-test capacitor is not needed in the micro-mechanical sensor, so that the design complexity of the micro-mechanical sensor and the design difficulty of a detection circuit driving module are reduced.
Drawings
FIG. 1 is a schematic diagram of a conventional MEMS;
FIG. 2 is a simplified schematic diagram of a micromechanical implemented self-test of a prior art micromechanical sensor;
FIG. 3 is a schematic diagram of a MEMS according to an embodiment of the present invention;
fig. 4 is a circuit diagram of a self-test capacitor array in accordance with an embodiment of the present invention;
fig. 5 is a partial circuit diagram of another self-test capacitor array in accordance with an embodiment of the present invention;
fig. 6 is a partial circuit diagram of another self-test capacitor array in accordance with an embodiment of the present invention;
fig. 7 is a circuit diagram of the generation of the on signal of the fifth switch and the on signal of the sixth switch in the cycle implementing circuit according to the embodiment of the present invention;
fig. 8 is a timing diagram of some of the signals in the self-test capacitor array of an embodiment of the present invention;
fig. 9 is a timing diagram of a part of signals in the detection circuit according to the embodiment of the present invention;
fig. 10 is a circuit diagram of two self-test capacitor arrays forming a differential structure according to an embodiment of the present invention;
fig. 11 is a timing comparison diagram of the output signals of two self-test capacitor arrays forming a differential structure according to an embodiment of the present invention;
fig. 12 is a schematic diagram of a partial structure in a detection circuit including a differential structure according to an embodiment of the present invention;
fig. 13 is a timing diagram of a plurality of cycles of a partial signal in a detection circuit including a differential structure according to an embodiment of the present invention.
Detailed Description
The mems and the detection circuit according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.
Please refer to fig. 3, which is a schematic structural diagram of a mems according to an embodiment of the present invention. As shown in fig. 3, the micro-electromechanical system includes: a micromechanical sensor 40 and a detection circuit 30 connected to the micromechanical sensor 40; wherein,
the micromechanical sensor 40 comprises a micromechanical sensor capacitance 41; that is, in this embodiment, the micromechanical sensor 40 may no longer be provided with a micromechanical self-test capacitor;
the detection circuit 30 includes: a self-test capacitor array 31 and a signal reading and processing module 32 connected to said self-test capacitor array 31; wherein,
the self-test capacitor array 31 is used for outputting periodically-changed charges;
the signal reading and processing module 32 comprises: a charge amplifier 321, a demodulator 322, and a low-pass filter 323 connected in this order; the signal reading and processing module 32 is configured to output a voltage signal according to the periodically changing charge output by the self-test capacitor array 31, where the voltage signal is used to determine whether the detection circuit is working normally, so as to complete a self-test function.
Wherein the periodically varying charge comprises a sine wave periodically varying charge or a triangular wave periodically varying charge. In the embodiment of the present application, a sine wave periodically changing charge is taken as an example. The triangular wave periodic variation charge can be realized by changing the capacitance value, and the embodiment of the application is not repeated.
In the utility model provides an among the micro electro mechanical system, through the charge of the periodic variation of self test capacitor array 31 output in the detection circuitry 30, from this when carrying out the self test of detection circuitry 30, through the periodic variation of the charge of self test capacitor array 31 output can go on, thereby avoided needing detection circuitry 30 drive module to produce high pressure drive signal to make the micromachine in the micromechanical sensor from the test capacitor output the periodic charge signal that the self test needs, the self test process of detection circuitry 30 no longer needs micromechanical sensor 40 to participate in from this, the self test flow of detection circuitry 30 has been simplified, and the self test reliability has been improved; meanwhile, a micro-mechanical self-test capacitor is not needed in the micro-mechanical sensor 40, so that the design complexity of the micro-mechanical sensor 40 and the design difficulty of a driving module of the detection circuit 30 are reduced.
In this embodiment, the self-test capacitor array 31 can be implemented by a capacitor in the basic process of the integrated circuit, that is, compared with the prior art that a micro-mechanical self-test capacitor needs to be formed by a micro-mechanical process, the micro-electro-mechanical system provided by this embodiment simplifies the capacitor required in the self-test.
In the mems provided in the present embodiment, the micromechanical sensor 40 is changed mainly in that a micromechanical self-test capacitor may not be provided any more, thereby simplifying the structure of the micromechanical sensor 40; the structure of the detection circuit 30 will be greatly changed, and therefore, in the following description of the present embodiment, the detection circuit 30 will be described with emphasis.
In this embodiment, the detection circuit 30 further includes other modules, specifically including a driving module 33, a timing generation circuit 34, a BIAS circuit 35, and a digital processing module 36, where the driving module 33, the timing generation circuit 34, the BIAS circuit 35, and the digital processing module 36 all use the structure in the prior art, and the functions of the driving module 33, the timing generation circuit 34, the BIAS circuit 35, and the digital processing module 36 in the detection circuit 30 are substantially the same. For example, the timing generation circuit 34 will still generate the sign control signal PH _ Vsin and the read signal PH _ RS, the Reset signal Reset, etc., but it will also generate some control signals required for the self-test capacitor array 31 in the present embodiment, specifically the control signal B0～Bn-1Etc.; the BIAS circuit 35 mainly generates a reference level Vcom and a common mode level Vcm; the digital processing module 36 will generate a control signal D0～Dk-1And the like.
In this embodiment, the charge amplifier 321 reads the periodically varying charges output from the self-test capacitor array 31, the reading process is controlled by the reading signal PH _ RS generated by the timing generation circuit 34, and when the reading signal PH _ RS is at a low level, the charge amplifier 321 is in a Reset state; when the read signal PH _ RS is high, the charge amplifier 321 is in a read state.
Please refer to fig. 4, which is a circuit diagram of a self-test capacitor array according to an embodiment of the present invention. Specifically, the self-test capacitor array 31 can be implemented by a circuit as shown in fig. 4. In this embodiment, the self-test capacitor array 31 includes an amplitude circuit 311a, a cycle realization circuit 312 connected to the amplitude circuit 311 a; wherein the amplitude circuit 311a is configured to generate a half-cycle varying charge with only positive half-cycle transition; the cycle enable circuit 312 is operable to convert the half-cycle varying charge generated by the amplitude circuit 311a that is only in the positive half-cycle into a periodically varying charge that is in both the positive and negative half-cycles.
The amplitude circuit may be implemented by various circuits, and three amplitude circuits are schematically shown in the present embodiment.
First, please refer to fig. 4, specifically, the amplitude circuit 311a includes a first circuit group, the first circuit group includes a plurality of capacitor groups connected in parallel, each capacitor group includes a capacitor, a first switch connected to the capacitor, a second switch connected to the capacitor, and a common mode level Vcm connected to the second switch, wherein a turn-on signal of the first switch is opposite to a turn-on signal of the second switch. For example, the first row capacitor bank includes a capacitor Ct0(for clarity and convenience of presentation, symbol Ct0Also representing the capacitance value of the corresponding capacitance, the same applies hereinafter), and said capacitance Ct0Connected first switch B0(for clarity and convenience of presentation, symbol B0Also representing the control signal controlling the corresponding switch, the same applies hereinafter), and said capacitor Ct0Second switch connected with each otherAnd the second switchA connected common mode level Vcm, wherein the first switch B0Turn-on signal B of0And the second switchOn signal ofThe opposite is true. Here, the electricityContainer Ct0By means of a second switchConnected to a common-mode level Vcm, for the purpose of operating when said capacitor C is presentt0When not selected, the capacitor is not suspended, thereby keeping the capacitor stable. The capacitor C is used in the circuit design of the self-test capacitor arrayt0～Ct（n-1）Capacitance value C oft0～Ct（n-1）The design is based on the variation of the periodic function, for example, Ct 0-Ct (n-1) in FIG. 8, Ct 0-Ct (n-1) are based on the sinusoidal periodic function.
For convenience of presentation, in this application the representation of the capacitance is the same as the representation of its corresponding capacitance value and the representation of the switch is the same as the representation of its corresponding control signal.
Please refer to fig. 8, which is a timing diagram of a part of signals in the self-test capacitor array according to an embodiment of the present invention. As shown in fig. 8, by switch B0～Bn-1Different turn-on sequences (wherein B0～Bn-1High level indicates that the corresponding switch is closed, the capacitor in the same capacitor bank is selected), and the capacitor Ct0～Ct（n-1）Are selected at different times because of the capacitance Ct0～Ct（n-1）Capacitance value C oft0～Ct（n-1）Is designed to vary as a periodic function such that fitting the (total) capacitance across the self-test capacitor array 311 results in a periodically varying capacitance, but only a positive half cycle, as shown by C in fig. 8t0～Ct（n-1）Shown in waveform.
Referring to fig. 4, in the present embodiment, the amplitude circuit 311a further includes two first adjusting circuits, a second adjusting circuit and a third adjusting circuit connected to the first circuit group, wherein the first adjusting circuit includes a capacitor (in the two first adjusting circuits, C is respectively connected to the two first adjusting circuits) connected in parallel1、C3) And a switch controlled by a Reset signal Reset (i.e., a status signal of the charge amplifier 321), and a control circuit for controlling the Reset signal ResetA common mode level Vcm to which the switch is connected; the second regulating circuit comprises a capacitor C2(ii) a The third regulating circuit comprises a plurality of groups of capacitor groups connected in parallel, and each group of capacitor groups comprises a capacitor, a third switch connected with the capacitor, a fourth switch connected with the capacitor and a reference level V connected with the fourth switchrefAnd the opening signal of the third switch is opposite to the opening signal of the fourth switch, and the capacitance values of the capacitors in the multiple groups of parallel capacitor groups are changed in a binary mode. For example, in the third adjusting circuit, the first row capacitance group includes a capacitance C0And the capacitor C0Connected third switch D0And the capacitor C0Fourth switch connected with each otherAnd the fourth switchConnected reference levels VrefWherein the third switch D0Turn-on signal D of0And the four switchesOn signal ofThe opposite is true. Likewise, the capacitance C is described herein0Through a third switchAnd a reference level VrefConnected with the purpose of when said capacitor C is0When not selected, the capacitor is not suspended, thereby keeping the stability. Here, the capacitance C0～2k-1C0The capacitance value of the capacitors in the front row and the back row is changed in a binary mode, namely the difference between the capacitance values is multiplied by 2, and the amplitude value can be controlled and adjusted more conveniently through the binary design.
Here, assuming that the equivalent capacitance magnitude output by the amplitude circuit 311a is represented by Csin, the capacitance magnitude between the b terminal and the a terminal (i.e., the capacitance magnitude output from the self-test capacitor array 31) can be represented as follows:
assuming again that the periodic magnitude coefficient Ksin of Csin, Ksin can be expressed as follows:
Cbacan be simplified as follows:
Cba＝Ksin·Csin
one amplitude circuit is shown in fig. 4, and referring next to fig. 5, fig. 5 shows another amplitude circuit. As shown in fig. 5, the amplitude circuit 311b includes a first circuit group, and n +1 first adjusting circuits, n second adjusting circuits, and a third adjusting circuit connected in series with the first circuit group, where n is a natural number, and the first adjusting circuit includes a capacitor and a switch controlled by a reset signal connected in parallel, and a common mode level Vcm connected to the capacitor and the switch; the second regulating circuit comprises a capacitor; the third regulating circuit comprises a plurality of groups of capacitor groups connected in parallel, and each group of capacitor groups comprises a capacitor, a third switch connected with the capacitor, a fourth switch connected with the capacitor and a reference level V connected with the fourth switchrefWherein an on signal of the third switch is opposite to an on signal of the fourth switch.
Here, the amplitude circuit 311a shown in fig. 4 can be regarded as a special case of the amplitude circuit 311b shown in fig. 5, i.e., a case where n is equal to 1.
Referring to fig. 6, a third amplitude circuit 311c is shown, where the amplitude circuit 311c includes a first circuit group, and a third regulating circuit and a fourth regulating circuit connected in series with the first circuit group, where the third regulating circuit includes a plurality of groups of capacitors connected in parallel, each group of capacitors includes a capacitor, a third switch connected to the capacitor, a fourth switch connected to the capacitor, and a reference level V connected to the fourth switchrefWherein an on signal of the third switch is opposite to an on signal of the fourth switch; the fourth regulation circuit includes a switch controlled by a Reset signal and a common mode level Vcm connected to the switch. The third adjusting circuit is the same as the third adjusting circuit shown in fig. 4, and details thereof are not repeated in this embodiment of the application.
With continued reference to fig. 4, the period implementation circuit 312 includes a first branch and a second branch connected in parallel to the first branch, where the first branch includes a fifth switch PH _ Vcm and a reference level Vcom connected to the fifth switch PH _ Vcm; the second branch comprises a sixth switch PH _ Gnd and a ground level GND connected with the sixth switch PH _ Gnd; the turn-on signal PH _ Gnd of the sixth switch PH _ Gnd is opposite to the turn-on signal PH _ Vcm of the fifth switch PH _ Vcm.
Further, this embodiment also shows a circuit for generating the on signal PH _ Vcm of the fifth switch PH _ Vcm and the on signal PH _ Gnd of the sixth switch PH _ Gnd in the period implementation circuit 312. Specifically, please refer to fig. 7, which is a circuit diagram illustrating the generation of the on signal of the fifth switch and the on signal of the sixth switch in the period realization circuit according to the embodiment of the present invention.
As shown in fig. 7, the circuit for forming the on signal PH _ Vcm of the fifth switch in the period implementation circuit 312 includes: a first parallel circuit including a first generating circuit and a second generating circuit connected in parallel, the first generating circuitThe generating circuit comprises a switch controlled by a sign control signal PH _ Vsin, and the switch controlled by the sign control signal PH _ Vsin is connected with a reading signal PH _ RS; the second generating circuit comprises an inverted signal of a signed control signalControlled switch, said sign-controlled signal being an inverted signalControlled switch and an inverted signal of a read signalConnecting;
the circuit for forming the on signal PH _ Gnd of the sixth switch in the period implementation circuit 312 includes: a second parallel circuit including a third generating circuit and a fourth generating circuit connected in parallel, the third generating circuit including a switch controlled by a sign control signal PH _ Vsin, the switch controlled by the sign control signal PH _ Vsin, and an inverted signal of a read signalConnecting; the fourth generating circuit includes an inverted signal of the sign-controlled signalControlled switch, said sign-controlled signal being an inverted signalThe controlled switch is connected to a read signal PH _ RS.
Further, the circuit for forming the on signal of the fifth switch in the period implementing circuit 312 further includes a buffer connected to the first parallel circuit; the circuit for forming the on signal of the sixth switch in the period realization circuit 312 further includes a buffer connected to the second parallel circuit. The buffer can further increase the driving capability and speed of the opening signal PH _ Vcm of the fifth switch and the opening signal PH _ Gnd of the sixth switch.
Referring to fig. 3 and fig. 4, the period implementing circuit 312 implements outputting the charge with a period variation by: the terminal a in fig. 4 is connected to the input terminal of the operational amplifier in the charge amplifier 321, and corresponds to a virtual ground terminal. As can be seen from fig. 7 and 9, when the level of the sign control signal PH _ Vsin is inverted, the timing levels of the on signal PH _ Vcm of the fifth switch and the on signal PH _ Gnd of the sixth switch are inverted. During the period when the sign control signal PH _ Vsin is high, when the charge amplifier 321 is in the Reset state (i.e. the read signal PH _ RS is low), the b terminal is grounded (i.e. the sixth switch is closed, the b terminal is connected to the ground GND), the a terminal is a virtual ground terminal, so the charges at the two terminals ba are 0, when the charge amplifier 321 is in the read state (i.e. the read signal PH _ RS is high), the b terminal is connected to the Vcom (i.e. the fifth switch is closed), the a terminal is a virtual ground terminal, so the charges at the two terminals ba are Vcom Cba, i.e. the charge Q between the two terminals b and abaIncrease Vcom Cba compared to previous Reset state; similarly, during the period when the sign control signal PH _ Vsin is low, when the charge amplifier 321 is in the Reset state (i.e. when the read signal PH _ RS is low), the terminal b is connected to Vcom, and the terminal a is a virtual ground terminal, so the charges at the two terminals ba are Vcom × Cba, when the charge amplifier 321 is in the read state (i.e. when the read signal PH _ RS is high), the terminal b is connected to GND, the terminal a is a virtual ground terminal, the charges at the two terminals ba are 0, i.e. the charges Q between the two terminals b and a are QbaIncreased by-Vcom Cba compared to the previous Reset state. When charge amplifier 321 is in the read state (i.e., when read signal PH _ RS is high), the charge added from test capacitor array 31 can be represented as follows:
namely:
i.e. periodically varying charges from the test capacitor array 31. The periodically varying charge is transferred to the feedback capacitor Cfb through the charge amplifier 321, and finally the periodically varying voltage signal V is output to the charge amplifier 321CA_OUT. In which the periodically varying voltage signal V output at the charge amplifier 321CA_OUTThe timing diagram of fig. 9 can be referred to; also, fig. 9 shows the periodically varying voltage signal V output at the charge amplifier 321CA_OUTAnother input signal V of the demodulator 322 when passing through the demodulator 322DemoThe timing waveform of (a).
Further, the number of the self-test capacitor arrays 31 may be two, and the two self-test capacitor arrays 31 constitute a differential structure. In this case, the charge amplifier 321, the demodulator 322, and the low-pass filter 323 are all differential structures, so that the formed capacitive sensor detection circuit can have better interference resistance. Fig. 10 shows two self-test capacitor arrays forming a differential structure. As shown in fig. 10, the difference between the two self-test capacitor arrays constituting the differential structure is that the on signal PH _ Vcm of the fifth switch and the on signal PH _ Gnd of the sixth switch in the self-test capacitor array 2 are interchanged with respect to the self-test capacitor array 1. Further, the output signals of the two self-test capacitor arrays constituting the differential structure are shown in fig. 11. As shown in fig. 11, the output signals (i.e., the periodically varying charges) of the two self-test capacitor arrays constituting the differential structure are equal in magnitude and opposite in phase.
Specifically, please refer to fig. 12, which is a schematic diagram of a partial structure of a detection circuit including a differential structure according to an embodiment of the present invention. As shown in FIG. 12, the self-test capacitor array 1 and the self-test capacitor array 2 together generate differential cyclically varying charges, which are converted into differential cycles by charge amplifiersPeriod voltage signal VCA_OUTOutput V of the charge amplifierCA_OUTThen passing through a demodulator where the periodic voltage signal V is differentiatedCA_OUTWith another input signal V of the demodulatorDemo(input signal V)DemoIs a differential periodic voltage signal VCA_OUTPeriodic signals in phase) to demodulate the output signal V of the charge amplifierCA_OUTAmplitude of the periodic envelope signal of (a), the demodulated signal VDemo_OUTOften with high frequency noise, so the high frequency noise is filtered by a low pass filter and finally output VLPF_OUT。
Wherein the output signal V of the charge amplifierCA_OUTCan be expressed as:
wherein C isCARepresenting the magnitude of the feedback capacitance of charge amplifier 321, i.e., CCA=Cfb；
In the present embodiment, the gains of the demodulator and the low-pass filter are both set to 1, and thus, the output signal V of the low-pass filterLPF_OUTI.e. the amplitude of the periodic signal output by the charge amplifier and low-pass filtered, the amplitude of the periodic capacitor Csin is Ct（n-1）Thereby the output signal V of the low-pass filterLPF_OUTThe resulting signal magnitude can be expressed as:
further, please refer to fig. 13, which is a timing diagram illustrating a plurality of periods of partial signals in a detection circuit including a differential structure according to an embodiment of the present invention. Wherein, CbaThe capacitance change of the self-test capacitor array (differential structure) is shown (the self-test capacitor array 1 and the self-test capacitor array 2 convert the capacitance change with only positive half cycle change into the charge change with positive and negative half cycles). In particular, the periodically varying charge outputs a voltage signal V via a capacitive amplifierCA_OUT，VCA_OUTThe envelope of (a) is a periodic signal, and a reset time sequence is arranged in the envelope; in the demodulator VCA_OUTAnd VDemoMultiplying and demodulating VCA_OUTAmplitude V of the periodic envelope signalDemo_OUT，VDemo_OUTHaving high frequency burrs; then, V is filtered by a low pass filterDemo_OUTHigh frequency glitch of, output VLPF_OUT，VLPF_OUTIs a smooth level signal.
When self-testing is carried out, the self-testing capacitor array outputs charges which change periodically; the signal reading and processing module receives the periodically changed charges output by the self-test capacitor array and outputs a voltage signal according to the periodically changed charges, and the voltage signal is used for judging whether the capacitor sensor detection circuit works normally or not to complete the self-test function. If said voltage signal value is equal to V in the above expressionLPF_OUTThe value of (1) indicates that the detection circuit works normally; if said voltage signal value deviates from V in the above expressionLPF_OUTThe value of (b) indicates that the detection circuit is not operating properly. Thereby avoiding the need of the detection circuit driving module to generate a high-voltage driving signal to enable the micro-mechanical self-test capacitor in the micro-mechanical sensor to output a periodic charge signal required by self-test, so that the self-test process of the detection circuit does not need the participation of the micro-mechanical sensor any more,the self-testing process of the detection circuit is simplified, the self-testing reliability is improved, and the design complexity of the micro-mechanical sensor and the design difficulty of the detection circuit driving module are reduced.
Further, outputting the periodically varying charge from the self-test capacitor array includes: the amplitude circuit generates half-cycle change charges with only positive half-cycle change; the period realizing circuit receives the half-period changing charges generated by the amplitude circuit and changed only by the positive half period, and accordingly obtains the periodically changing charges of the positive half period and the negative half period.
When the number of the self-test capacitor arrays is two, and the two self-test capacitor arrays form a differential structure, the outputting of the periodically-changed charges from the self-test capacitor arrays comprises: the two self-test capacitor arrays forming the differential structure both output periodically-changed charges, and the output periodically-changed charges form a differential signal.
In summary, in the mems and the detection circuit provided in the embodiment of the present invention, the periodic variation of the charge is output through the self-test capacitor array in the detection circuit, so that when the self-test of the detection circuit is performed, the periodic variation of the charge output through the self-test capacitor array can be performed, thereby avoiding the need of generating a high-voltage driving signal by the detection circuit driving module to enable the micro-mechanical self-test capacitor in the micro-mechanical sensor to output the periodic charge signal required by the self-test, and thus the self-test process of the detection circuit does not need the participation of the micro-mechanical sensor any more, simplifying the self-test flow of the detection circuit, and improving the reliability of the self-; meanwhile, a micro-mechanical self-test capacitor is not needed in the micro-mechanical sensor, so that the design complexity of the micro-mechanical sensor and the design difficulty of a detection circuit driving module are reduced.
The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.
Claims (24)
1. A microelectromechanical system, comprising: the detection circuit is connected with the micromechanical sensor; wherein,
the micromechanical sensor comprises a micromechanical sensing capacitance;
the detection circuit includes: the circuit comprises a self-test capacitor array for outputting periodically changed charges and a signal reading and processing module which is connected with the self-test capacitor array and outputs a voltage signal according to the periodically changed charges output by the self-test capacitor array, wherein the voltage signal is used for judging whether the detection circuit works normally or not and finishing a self-test function; wherein,
the signal reading and processing module comprises: a charge amplifier, a demodulator and a low-pass filter connected in sequence.
2. The microelectromechanical system of claim 1, wherein the self-test capacitor array includes a magnitude circuit that generates half-cycle varying charge with only positive half-cycles alternating and a cycle effecting circuit coupled to the magnitude circuit that converts the half-cycle varying charge with only positive half-cycles alternating to a periodically varying charge with both positive and negative half-cycles.
3. The mems of claim 2, wherein the amplitude circuit comprises a first circuit group comprising a plurality of parallel capacitor groups, each capacitor group comprising a capacitor, a first switch connected to the capacitor, a second switch connected to the capacitor, and a common mode level Vcm connected to the second switch, wherein a turn-on signal of the first switch is opposite to a turn-on signal of the second switch.
4. The mems of claim 3, wherein a plurality of capacitance values in the plurality of parallel capacitor banks vary in sine or triangle wave form, and the capacitors in different capacitor banks are selected at different times to produce half sine wave or half triangle wave periodically varying charges with only positive half cycles alternating.
5. The mems according to claim 3, wherein the amplitude circuit further comprises n +1 first adjusting circuits, n second adjusting circuits and a third adjusting circuit connected in series with the first circuit group, wherein n is a natural number, the first adjusting circuit comprises a capacitor and a switch controlled by a reset signal connected in parallel, and a common mode level Vcm connected to the capacitor and the switch; the second regulating circuitThe circuit comprises a capacitor; the third regulating circuit comprises a plurality of groups of capacitor groups connected in parallel, and each group of capacitor groups comprises a capacitor, a third switch connected with the capacitor, a fourth switch connected with the capacitor and a reference level V connected with the fourth switchrefWherein an on signal of the third switch is opposite to an on signal of the fourth switch.
6. The mems of claim 3, wherein the amplitude circuit further comprises a third conditioning circuit and a fourth conditioning circuit in series with the first set of circuits, wherein the third conditioning circuit comprises a plurality of sets of capacitors connected in parallel, each set of capacitors comprising a capacitor, a third switch connected to the capacitor, a fourth switch connected to the capacitor, and a reference level V connected to the fourth switchrefWherein an on signal of the third switch is opposite to an on signal of the fourth switch; the fourth regulating circuit comprises a switch controlled by a reset signal and a common mode level Vcm connected with the switch.
7. The MEMS of claim 3, wherein the period effecting circuit comprises a first branch and a second branch in parallel with the first branch, wherein,
the first branch comprises a fifth switch and a reference level Vcom connected with the fifth switch;
the second branch circuit comprises a sixth switch and a ground level GND connected with the sixth switch; the opening signal of the sixth switch is opposite to the opening signal of the fifth switch.
8. The micro-electro-mechanical system of claim 7,
the forming circuit of the opening signal of the fifth switch comprises: a first parallel circuit including a first generating circuit and a second generating circuit connected in parallel, the first generating circuit including a symbol controlledThe switch controlled by the sign control signal PH _ Vsin is connected with a reading signal PH _ RS; the second generating circuit comprises an inverted signal of a signed control signalControlled switch, said sign-controlled signal being an inverted signalControlled switch and an inverted signal of a read signalConnecting;
the circuit for forming the opening signal of the sixth switch comprises: a second parallel circuit including a third generating circuit and a fourth generating circuit connected in parallel, the third generating circuit including a switch controlled by a sign control signal PH _ Vsin, the switch controlled by the sign control signal PH _ Vsin, and an inverted signal of a read signalConnecting; the fourth generating circuit includes an inverted signal of the sign-controlled signalControlled switch, said sign-controlled signal being an inverted signalThe controlled switch is connected to a read signal PH _ RS.
9. The mems of claim 8, wherein the circuit for forming the on signal of the fifth switch further comprises a buffer connected to the first parallel circuit; the circuit for forming the on signal of the sixth switch further includes a buffer connected to the second parallel circuit.
10. The micro-electromechanical system of claim 9,
during the high level of the sign control signal PH _ Vsin, when the charge amplifier is in the reset state, the terminal b is grounded, the terminal a is a virtual ground, and the charges of the two terminals ba are 0, and when the charge amplifier is in the read state, the terminal b is Vcom, the terminal a is a virtual ground, and the charges of the two terminals ba are Vcom Cba, so that the charges Q between the terminals b and abaIncreased Vcom Cba compared to the previous reset state;
during the period when the sign control signal PH _ Vsin is at low level, when the charge amplifier is in reset state, the terminal b is connected with Vcom, the terminal a is virtual ground, the charges of the two terminals ba are Vcom × Cba, when the charge amplifier is in read state, the terminal b is connected with GND, the terminal a is virtual ground, the charges of the two terminals ba are 0, thereby the charges Q between the two terminals b and a are all equalbaincreased-Vcom Cba compared to the previous Reset state;
wherein Cba is the capacitance value of ba at both ends.
11. The mems according to any one of claims 1-10, wherein the number of self-test capacitor arrays is two, and the two self-test capacitor arrays constitute a differential structure.
12. The mems of claim 11, wherein the charge amplifier, demodulator, and low pass filter are all differential structures.
13. A detection circuit, comprising: the circuit comprises a self-test capacitor array for outputting periodically changed charges and a signal reading and processing module which is connected with the self-test capacitor array and outputs a voltage signal according to the periodically changed charges output by the self-test capacitor array, wherein the voltage signal is used for judging whether the detection circuit works normally or not and finishing a self-test function; wherein,
the signal reading and processing module comprises: a charge amplifier, a demodulator and a low-pass filter connected in sequence.
14. The detection circuit of claim 13, wherein the self-test capacitor array includes a magnitude circuit that generates half-cycle varying charge with only positive half-cycles alternating and a cycle effecting circuit connected to the magnitude circuit that converts the half-cycle varying charge with only positive half-cycles alternating to a periodically varying charge with both positive and negative half-cycles.
15. The detection circuit of claim 14, wherein the amplitude circuit comprises a first circuit group comprising a plurality of capacitor groups connected in parallel, each capacitor group comprising a capacitor, a first switch connected to the capacitor, a second switch connected to the capacitor, and a common mode level Vcm connected to the second switch, wherein an on signal of the first switch is opposite to an on signal of the second switch.
16. The detection circuit of claim 15, wherein a plurality of capacitance values in a plurality of parallel capacitor banks vary in sine or triangular wave form, the capacitors in different capacitor banks being selected at different times to produce a half sine wave period varying charge or a half triangular wave period varying charge with only positive half cycle transitions.
17. The detection circuit of claim 15, wherein the amplitude circuit further comprises n +1 first, n second and third adjustment circuits connected in series with the first circuit group, wherein n is a natural number, the first adjustment circuit comprises a capacitor and a switch controlled by a reset signal connected in parallel, and a common mode connected to the capacitor and the switchA level Vcm; the second regulating circuit comprises a capacitor; the third regulating circuit comprises a plurality of groups of capacitor groups connected in parallel, and each group of capacitor groups comprises a capacitor, a third switch connected with the capacitor, a fourth switch connected with the capacitor and a reference level V connected with the fourth switchrefWherein an on signal of the third switch is opposite to an on signal of the fourth switch.
18. The detection circuit of claim 15, wherein the amplitude circuit further comprises a third regulation circuit and a fourth regulation circuit connected in series with the first circuit group, wherein the third regulation circuit comprises a plurality of sets of capacitors connected in parallel, each set of capacitors comprising a capacitor, a third switch connected to the capacitor, a fourth switch connected to the capacitor, and a reference level V connected to the fourth switchrefWherein an on signal of the third switch is opposite to an on signal of the fourth switch; the fourth regulating circuit comprises a switch controlled by a reset signal and a common mode level Vcm connected with the switch.
19. The detection circuit of claim 15, wherein the period realization circuit includes a first branch and a second branch in parallel with the first branch, wherein,
the first branch comprises a fifth switch and a reference level Vcom connected with the fifth switch;
the second branch circuit comprises a sixth switch and a ground level GND connected with the sixth switch; the opening signal of the sixth switch is opposite to the opening signal of the fifth switch.
20. The detection circuit of claim 19,
the forming circuit of the opening signal of the fifth switch comprises: a first parallel circuit including a first generating circuit and a second generating circuit connected in parallel, the first parallel circuitThe generating circuit comprises a switch controlled by a sign control signal PH _ Vsin, and the switch controlled by the sign control signal PH _ Vsin is connected with a reading signal PH _ RS; the second generating circuit comprises an inverted signal of a signed control signalControlled switch, said sign-controlled signal being an inverted signalControlled switch and an inverted signal of a read signalConnecting;
the circuit for forming the opening signal of the sixth switch comprises: a second parallel circuit including a third generating circuit and a fourth generating circuit connected in parallel, the third generating circuit including a switch controlled by a sign control signal PH _ Vsin, the switch controlled by the sign control signal PH _ Vsin, and an inverted signal of a read signalConnecting; the fourth generating circuit includes an inverted signal of the sign-controlled signalControlled switch, said sign-controlled signal being an inverted signalThe controlled switch is connected to a read signal PH _ RS.
21. The detection circuit of claim 20, wherein the circuit for forming the on signal of the fifth switch further comprises a buffer connected to the first parallel circuit; the circuit for forming the on signal of the sixth switch further includes a buffer connected to the second parallel circuit.
22. The detection circuit of claim 21,
during the high level of the sign control signal PH _ Vsin, when the charge amplifier is in the reset state, the terminal b is grounded, the terminal a is a virtual ground, and the charges of the two terminals ba are 0, and when the charge amplifier is in the read state, the terminal b is Vcom, the terminal a is a virtual ground, and the charges of the two terminals ba are Vcom Cba, so that the charges Q between the terminals b and abaIncreased Vcom Cba compared to the previous reset state;
during the period when the sign control signal PH _ Vsin is at low level, when the charge amplifier is in reset state, the terminal b is connected with Vcom, the terminal a is virtual ground, the charges of the two terminals ba are Vcom × Cba, when the charge amplifier is in read state, the terminal b is connected with GND, the terminal a is virtual ground, the charges of the two terminals ba are 0, thereby the charges Q between the two terminals b and a are all equalbaincreased-Vcom Cba compared to the previous Reset state;
wherein Cba is the capacitance value of ba at both ends.
23. The detection circuit of any of claims 13-22, wherein the number of self-test capacitor arrays is two, and the two self-test capacitor arrays constitute a differential structure.
24. The detection circuit of claim 23, wherein the charge amplifier, demodulator, and low pass filter are all differential structures.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320892445.6U CN203890050U (en) | 2013-12-30 | 2013-12-30 | Micro electro mechanical system and detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320892445.6U CN203890050U (en) | 2013-12-30 | 2013-12-30 | Micro electro mechanical system and detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203890050U true CN203890050U (en) | 2014-10-22 |
Family
ID=51716478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320892445.6U Expired - Lifetime CN203890050U (en) | 2013-12-30 | 2013-12-30 | Micro electro mechanical system and detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203890050U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103723673A (en) * | 2013-12-30 | 2014-04-16 | 杭州士兰微电子股份有限公司 | Micro electro mechanical system and detection circuit |
-
2013
- 2013-12-30 CN CN201320892445.6U patent/CN203890050U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103723673A (en) * | 2013-12-30 | 2014-04-16 | 杭州士兰微电子股份有限公司 | Micro electro mechanical system and detection circuit |
| CN103723673B (en) * | 2013-12-30 | 2015-12-16 | 杭州士兰微电子股份有限公司 | MEMS and testing circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3410129B1 (en) | Sensor device and method for continuous fault monitoring of sensor device | |
| JP4178658B2 (en) | Capacitive physical quantity detector | |
| CN203275441U (en) | Sensor circuit | |
| CN107508601B (en) | Noise reduction method based on combined MEMS accelerometer sensor chopping and electronic circuit | |
| US20020027191A1 (en) | Apparatus for sensing position of electrostatic XY-stage through time-division multiplexing | |
| CN103162680B (en) | Based on silicon micromechanical gyroscope performance improvement method and the device of force-balance closed-loop control | |
| JP2008102091A (en) | Capacitive detection circuit | |
| JP2010505102A (en) | Device for measuring yaw rate using vibration sensor | |
| WO2016158469A1 (en) | Signal detecting method for capacitance detection type sensor, mems sensor, and system | |
| JP2003121457A (en) | Capacitance type physical quantity sensor | |
| US6630834B2 (en) | Apparatus and method for measuring change in capacitance | |
| JP2009097932A (en) | Capacitive detector | |
| CN109029409A (en) | Parameter amplification method and its device in a kind of tunable grid structure micromechanical gyro | |
| US8327708B2 (en) | Acceleration sensor | |
| CN108966099B (en) | Excitation circuit, system comprising an excitation circuit and a capacitive transducer and method | |
| CN203890050U (en) | Micro electro mechanical system and detection circuit | |
| CN105606134A (en) | Signal processing device | |
| CN103723673B (en) | MEMS and testing circuit | |
| CN104567850A (en) | Phase-shifting circuit and control method thereof and MEMS (Micro-electromechanical System) gyroscope driving circuit | |
| US4896100A (en) | Signal conditioner for capacitive transducer | |
| JP4269388B2 (en) | Capacitive physical quantity detector | |
| CN109883310B (en) | Self-balancing variable area array capacitance displacement detection device and method | |
| JP4150292B2 (en) | Capacitive sensor device with abnormality detection function | |
| JP6089986B2 (en) | Sensor device | |
| JP2520137B2 (en) | Position detection device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20141022 Effective date of abandoning: 20151216 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |