CN203859112U - Testing structure for defect analysis of metal interconnection structure - Google Patents
Testing structure for defect analysis of metal interconnection structure Download PDFInfo
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- CN203859112U CN203859112U CN201420238913.2U CN201420238913U CN203859112U CN 203859112 U CN203859112 U CN 203859112U CN 201420238913 U CN201420238913 U CN 201420238913U CN 203859112 U CN203859112 U CN 203859112U
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- metal
- metal layer
- defect analysis
- test structure
- via metal
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 281
- 239000002184 metal Substances 0.000 title claims abstract description 281
- 238000012360 testing method Methods 0.000 title claims abstract description 66
- 230000007547 defect Effects 0.000 title claims abstract description 40
- 238000004458 analytical method Methods 0.000 title claims abstract description 36
- 239000000463 material Substances 0.000 claims description 18
- 238000005516 engineering process Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000010410 layer Substances 0.000 abstract description 104
- 238000000034 method Methods 0.000 abstract description 15
- 230000007797 corrosion Effects 0.000 abstract description 4
- 238000005260 corrosion Methods 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 8
- 239000004411 aluminium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010998 test method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The utility model provides a testing structure for the defect analysis of a metal interconnection structure. The testing structure comprises a lower metal layer, an inter layer dielectric, an upper metal layer, and through hole metal formed in the inter layer dielectric, wherein the upper metal layer and the through hole metal are connected and the lower metal layer is provided with an insulated area corresponding to the through hole metal so that the through hole metal and the lower metal layer are enabled to have a preset space therebetween; or the lower metal layer and the through hole metal are connected and the upper metal layer is provided with an insulated area corresponding to the through hole metal so that the through hole metal and the upper metal layer are enabled to have a preset space therebetween. With the testing structure and method of the utility model, the problems of through hole metal attachment defect and corrosion caused by complete coverage of the metal layers and the through hole metal can be detected; and the testing structure is applicable to an FA testing stage of a chip and thus greatly reduces the number of faults of the through hole metal.
Description
Technical field
The utility model belongs to semiconductor test field, particularly relates to a kind of test structure for metal interconnect structure defect analysis.
Background technology
Depositing metal film on integrated circuit chip, and form wiring by photoetching technique, the element of isolation is mutually interconnected into the technique of required circuit by certain requirement.
Requirement to the metal material for integrated circuit interconnection is: resistivity is low, can form good low ohm contact with the electrode of element; To get well with the adhesiveness of silicon dioxide layer; Be convenient to deposit and lithography process and form wiring etc.
Aluminium is the most frequently used integrated circuit interconnection metal material, can meet above-mentioned requirements.The resistivity of aluminium is 2.8 * 10
-6europe centimetre, only a little more than the resistivity of a few metals such as silver, copper.Aluminium can form good ohmic contact, the good adhesion to silicon dioxide with germanium and the silicon of doping.Aluminium is convenient to evaporation deposition formation film and photoetching corrosion is processed to form wiring.Therefore, aluminium is widely used interconnect materials in integrated circuit always for a long time.
Existing a kind of conventional WAT test structure as shown in Figure 1, comprises lower metal layer 10, upper metal layers 20, inter-level dielectric and is formed at the via metal 30 that is also simultaneously connected in described lower metal layer 10 and upper metal layers 20 in described inter-level dielectric.During test, between lower metal layer 10 and upper metal layers 20, add a voltage difference, tested resistance and the conduction property of this WAT test structure.
But in aluminium line backend process, device is easy to suffer the Problem of Failure due to metal level/cause by the covering problem between metal.In metal level/by the covering problem between metal, modal phenomenon comprises via metal incomplete contact and galvanic effect etc. between metal level.Be specially, for example, when upper metal layers can not complete covering the top of via metal of its below, in the follow-up steps such as wet-cleaned, easily there is corrosion reaction in via metal (general material is tungsten) top, thereby in via metal, form hole, as shown in the broken circle frame in Fig. 2; Again for example, when lower metal layer can not complete covering the bottom of via metal of its top, via metal easily through the adhesive layer in through hole directly with its below the sidewall contact of lower metal layer, affect fastness and electric property, as shown in the broken circle frame in Fig. 3.
For existing two kinds of above problems, if adopt conventional WAT test structure to test, in test, be can not be captive.
Therefore, provide a kind of test structure for metal interconnect structure defect analysis that can catch above-mentioned two kinds of problems to be necessary.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is to provide a kind of test structure for metal interconnect structure defect analysis, for solving prior art because the defect that metal level and via metal covering problem cause is difficult to captive problem in conventional WAT test structure test.
For achieving the above object and other relevant objects, the utility model provides a kind of test structure for metal interconnect structure defect analysis, at least comprises:
The lower metal layer stacking gradually, inter-level dielectric, upper metal layers, and be formed at the via metal in inter-level dielectric;
Wherein, described upper metal layers is connected with described via metal, and described lower metal layer has arrange insulating regions corresponding to described via metal, so that have default spacing between described via metal and described lower metal layer.
As a kind of preferred version of the test structure for metal interconnect structure defect analysis of the present utility model, described test structure comprises a plurality of via metal, and described lower metal layer has and a plurality of insulating regions of the corresponding setting of this via metal respectively.
As a kind of preferred version of the test structure for metal interconnect structure defect analysis of the present utility model, described insulating regions is the poroid region that is formed at described lower metal layer.
As a kind of preferred version of the test structure for metal interconnect structure defect analysis of the present utility model, the material of described lower metal layer and upper metal layers is Al, and the material of described via metal is W.
As a kind of preferred version of the test structure for metal interconnect structure defect analysis of the present utility model, the semiconductor technology that is 0.16um for live width, described default spacing is 0.009um.
The utility model also provides a kind of test structure for metal interconnect structure defect analysis, at least comprises:
The lower metal layer stacking gradually, inter-level dielectric, upper metal layers, and be formed at the via metal in inter-level dielectric;
Wherein, described lower metal layer is connected with described via metal, and described upper metal layers has arrange insulating regions corresponding to described via metal, so that have default spacing between described via metal and described upper metal layers.
As a kind of preferred version of the test structure for metal interconnect structure defect analysis of the present utility model, described test structure comprises a plurality of via metal, and described upper metal layers has and a plurality of insulating regions of the corresponding setting of this via metal respectively.
As a kind of preferred version of the test structure for metal interconnect structure defect analysis of the present utility model, described insulating regions is the poroid region that is formed at described upper metal layers.
As a kind of preferred version of the test structure for metal interconnect structure defect analysis of the present utility model, the material of described lower metal layer and upper metal layers is Al, and the material of described via metal is W.
As a kind of preferred version of the test structure for metal interconnect structure defect analysis of the present utility model, the semiconductor technology that is 0.16um for live width, described default spacing is 0.009um.
As mentioned above, the utility model provides a kind of test structure for metal interconnect structure defect analysis, and described test structure comprises: the lower metal layer stacking gradually, inter-level dielectric, upper metal layers, and be formed at the via metal in inter-level dielectric; Wherein, described upper metal layers is connected with described via metal, and described lower metal layer has arrange insulating regions corresponding to described via metal, so that have default spacing between described via metal and described lower metal layer; Or described lower metal layer is connected with described via metal, described upper metal layers has arrange insulating regions corresponding to described via metal, so that have default spacing between described via metal and described upper metal layers.By test structure of the present utility model and method of testing, not only can detect because metal level and via metal are that the caused via metal of complete covering is adhered to defect and the problem such as be corroded, can also, for the FA test phase of chip, greatly reduce the number of times that via metal goes wrong.
Accompanying drawing explanation
Fig. 1 is shown as a kind of conventional WAT test structure schematic diagram of the prior art.
Fig. 2～Fig. 3 is shown as respectively the schematic diagram that the via metal causing due to metal level covering problem produces hole problem and produces attachment issue.
Fig. 4～Fig. 5 is shown as a kind of test structure schematic diagram for metal interconnect structure defect analysis of the present utility model, and wherein, Fig. 5 is A-A ' cross section structure schematic diagram in Fig. 4.
Fig. 6～Fig. 7 is shown as another kind of the present utility model for the test structure schematic diagram of metal interconnect structure defect analysis, and wherein, Fig. 6 is B-B ' cross section structure schematic diagram in Fig. 7.
Fig. 8 is shown as the steps flow chart schematic diagram of the method for testing for metal interconnect structure defect analysis of the present utility model.
Element numbers explanation
10 lower metal layer
20 upper metal layers
30 via metal
40 insulating regions
S11～S13 step 1)～step 3)
Embodiment
By specific instantiation, execution mode of the present utility model is described below, those skilled in the art can understand other advantages of the present utility model and effect easily by the disclosed content of this specification.The utility model can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present utility model.
Refer to Fig. 4～Fig. 8.It should be noted that, the diagram providing in the present embodiment only illustrates basic conception of the present utility model in a schematic way, satisfy and only show with assembly relevant in the utility model in graphic but not component count, shape and size drafting while implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
Embodiment 1
As shown in Fig. 4～Fig. 5, the present embodiment provides a kind of test structure for metal interconnect structure defect analysis, at least comprises:
The lower metal layer 10 stacking gradually, inter-level dielectric, upper metal layers 20, and be formed at the via metal 30 in inter-level dielectric;
Wherein, described upper metal layers 20 is connected with described via metal 30, described lower metal layer 10 has with described via metal 30 is corresponding insulating regions 40 is set, so that there is default spacing between described via metal 30 and described lower metal layer 10, and as shown in Figure 5.
As shown in Figure 4, as example, described test structure comprises a plurality of via metal 30, and described lower metal layer 10 has and a plurality of insulating regions 40 of the corresponding setting of this via metal 30 respectively.
It should be noted that, the test structure of the present embodiment, via metal 30 quantity than other position in wafer manufacture process or conventionally test structure can suitably reduce, the present embodiment is by reducing the manufacture density of described via metal 30, can reduce the impact due to process errors such as photoetching, more be conducive to the stability of enforcement and the accuracy of detection of the test structure of the present embodiment.
As example, described insulating regions 40 is for being formed at the poroid region of described lower metal layer 10.Certainly, described insulating regions 40 can be also poroid region being filled with dielectric etc., and is not limited thereto the example that place is enumerated.
As example, the material of described lower metal layer 10 and upper metal layers 20 is Al, and the material of described via metal 30 is W.Certainly, the material of described lower metal layer 10 and upper metal layers 20 and the material of described via metal 30 can change according to process requirements, are not limited thereto the example that place is enumerated.
It should be noted that, between described via metal 30 and described lower metal layer 10, there is default spacing, refer to all sides of described via metal 30 and the distance between 40 weeks sides of described insulating regions, simultaneously, in general, the upper surface of the bottom of described via metal 30 and described lower metal layer 10 is in the same plane.
Particularly, the semiconductor technology that is 0.16um for live width, the distance between described via metal 30 and described lower metal layer 10 is 0.009um.The meaning of this distance is, the semiconductor technology that is 0.16um for live width, when via metal 30 has skew (its skew generally can surpass 0.009um) or due to when having been penetrated adhesive layer by the complete covering of described lower metal layer 10, it all can contact with the lower metal layer 10 of its below, according to above principle, in lower metal layer 10 and upper metal layers 20, load a voltage difference, when if lower metal layer 10 and via metal 30 are all normal, this Circuit display is open circuit, when if described via metal 30 has skew or hole, this circuit can be shown as short circuit, now, just can differentiate lower metal layer 10 and whether via metal 30 is normal for open circuit or short circuit according to this circuit.
Embodiment 2
As shown in Fig. 6～Fig. 7, the present embodiment provides a kind of test structure for metal interconnect structure defect analysis, at least comprises:
The lower metal layer 10 stacking gradually, inter-level dielectric, upper metal layers 20, and be formed at the via metal 30 in inter-level dielectric;
Wherein, described lower metal layer 10 is connected with described via metal 30, described upper metal layers 20 has with described via metal 30 is corresponding insulating regions 40 is set, so that there is default spacing between described via metal 30 and described upper metal layers 20, and as shown in Figure 7.
As shown in Figure 6, as example, described test structure comprises a plurality of via metal 30, and described upper metal layers 20 has and a plurality of insulating regions 40 of the corresponding setting of this via metal 30 respectively.
It should be noted that, the test structure of the present embodiment, via metal 30 quantity than other position in wafer manufacture process or conventionally test structure can suitably reduce, the present embodiment is by reducing the manufacture density of described via metal 30, can reduce the impact due to process errors such as photoetching, more be conducive to the stability of enforcement and the accuracy of detection of the test structure of the present embodiment.
As example, described insulating regions 40 is for being formed at the poroid region of described upper metal layers 20.Certainly, described insulating regions 40 can be also poroid region being filled with dielectric etc., and is not limited thereto the example that place is enumerated.
As example, the material of described lower metal layer 10 and upper metal layers 20 is Al, and the material of described via metal 30 is W.Certainly, the material of described lower metal layer 10 and upper metal layers 20 and the material of described via metal 30 can change according to process requirements, are not limited thereto the example that place is enumerated.
It should be noted that, between described via metal 30 and described upper metal layers 20, there is default spacing, refer to all sides of described via metal 30 and the distance between 40 weeks sides of described insulating regions, simultaneously, in general, the upper surface of the bottom of described via metal 30 and described upper metal layers 20 is in the same plane.
Particularly, the semiconductor technology that is 0.16um for live width, the distance between described via metal 30 and described upper metal layers 20 is 0.009um.The meaning of this distance is, the semiconductor technology that is 0.16um for live width, when via metal 30 has skew or is formed with hole, its displacement generally can surpass 0.009um, according to above principle, in lower metal layer 10 and upper metal layers 20, load a voltage difference, when if upper metal layers 20 and via metal 30 are all normal, this Circuit display is open circuit, if described via metal 30 has skew or owing to not covered when corrosion occurring producing hole by upper metal layers 20, this circuit can be shown as short circuit, now, just can differentiate upper metal layers 20 and whether via metal 30 is normal for open circuit or short circuit according to this circuit.
Embodiment 3
As shown in Figure 8, the present embodiment provides a kind of method of testing for metal interconnect structure defect analysis, comprises step:
First carry out step 1) S11, chip metal interconnection structure in manufacture process, the test structure for metal interconnect structure defect analysis as described in embodiment 1 and/or embodiment 2 is manufactured in to wafer simultaneously;
Then carry out step 2) S12, gives described lower metal layer 10 and 20 1 voltage differences of upper metal layers, and tests out described lower metal layer 10 and upper metal layers 20 is open circuit or short circuit;
Finally carry out step 3) S13, if open circuit judges that described chip metal interconnection structure is for normal; If short circuit, judges that described chip metal interconnection structure is for abnormal.
As example, the described test structure for metal interconnect structure defect analysis is manufactured in the Cutting Road of wafer.
As example, described chip metal interconnection structure be extremely via metal 30 in wafer not by the complete covering of lower metal layer 10 or via metal 30 not by the complete covering of upper metal layers 20.Particularly, when described via metal 30 is not during by the complete covering of lower metal layer 10, it easily produces attachment issue, easily penetrates adhesive layer and contacts with the lower metal layer 10 of below; When described via metal 30 is not during by the complete covering of upper metal layers 20, in follow-up technical process, as processes such as wet etching and wet-cleaned, the formation hole that can be corroded, makes via metal 30 skew occur and contact with described upper metal layers 20.
As mentioned above, the utility model provides a kind of test structure for metal interconnect structure defect analysis, described test structure comprises: the lower metal layer 10 stacking gradually, inter-level dielectric, upper metal layers 20, and be formed at the via metal 30 in inter-level dielectric; Wherein, described upper metal layers 20 is connected with described via metal 30, and described lower metal layer 10 has with described via metal 30 is corresponding insulating regions 40 is set, so that have default spacing between described via metal 30 and described lower metal layer 10; Or described lower metal layer 10 is connected with described via metal 30, described upper metal layers 20 has with described via metal 30 is corresponding insulating regions 40 is set, so that have default spacing between described via metal 30 and described upper metal layers 20.By test structure of the present utility model and method of testing, not only can detect because metal level and via metal 30 adhered to defect and the problem such as be corroded for the caused via metal 30 of complete covering, can also, for the FA test phase of chip, greatly reduce the number of times that via metal 30 goes wrong.So the utility model has effectively overcome various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present utility model and effect thereof only, but not for limiting the utility model.Any person skilled in the art scholar all can, under spirit of the present utility model and category, modify or change above-described embodiment.Therefore, have in technical field under such as and conventionally know that the knowledgeable modifies or changes not departing from all equivalences that complete under spirit that the utility model discloses and technological thought, must be contained by claim of the present utility model.
Claims (10)
1. for a test structure for metal interconnect structure defect analysis, it is characterized in that, at least comprise:
The lower metal layer stacking gradually, inter-level dielectric, upper metal layers, and be formed at the via metal in inter-level dielectric;
Wherein, described upper metal layers is connected with described via metal, and described lower metal layer has arrange insulating regions corresponding to described via metal, so that have default spacing between described via metal and described lower metal layer.
2. the test structure for metal interconnect structure defect analysis according to claim 1, is characterized in that: comprise a plurality of via metal, described lower metal layer has and a plurality of insulating regions of the corresponding setting of this via metal respectively.
3. the test structure for metal interconnect structure defect analysis according to claim 1, is characterized in that: described insulating regions is the poroid region that is formed at described lower metal layer.
4. the test structure for metal interconnect structure defect analysis according to claim 1, is characterized in that: the material of described lower metal layer and upper metal layers is Al, and the material of described via metal is W.
5. the test structure for metal interconnect structure defect analysis according to claim 1, is characterized in that: the semiconductor technology that is 0.16um for live width, described default spacing is 0.009um.
6. for a test structure for metal interconnect structure defect analysis, it is characterized in that, at least comprise:
The lower metal layer stacking gradually, inter-level dielectric, upper metal layers, and be formed at the via metal in inter-level dielectric;
Wherein, described lower metal layer is connected with described via metal, and described upper metal layers has arrange insulating regions corresponding to described via metal, so that have default spacing between described via metal and described upper metal layers.
7. the test structure for metal interconnect structure defect analysis according to claim 6, is characterized in that: comprise a plurality of via metal, described upper metal layers has and a plurality of insulating regions of the corresponding setting of this via metal respectively.
8. the test structure for metal interconnect structure defect analysis according to claim 6, is characterized in that: described insulating regions is the poroid region that is formed at described upper metal layers.
9. the test structure for metal interconnect structure defect analysis according to claim 6, is characterized in that: the material of described lower metal layer and upper metal layers is Al, and the material of described via metal is W.
10. the test structure for metal interconnect structure defect analysis according to claim 6, is characterized in that: the semiconductor technology that is 0.16um for live width, described default spacing is 0.009um.
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| CN201420238913.2U CN203859112U (en) | 2014-05-09 | 2014-05-09 | Testing structure for defect analysis of metal interconnection structure |
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| CN201420238913.2U CN203859112U (en) | 2014-05-09 | 2014-05-09 | Testing structure for defect analysis of metal interconnection structure |
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Granted publication date: 20141001 Termination date: 20190509 |
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| CF01 | Termination of patent right due to non-payment of annual fee |