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CN203422915U - Shift register unit, shift register and display device - Google Patents

Shift register unit, shift register and display device Download PDF

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Publication number
CN203422915U
CN203422915U CN201320487520.0U CN201320487520U CN203422915U CN 203422915 U CN203422915 U CN 203422915U CN 201320487520 U CN201320487520 U CN 201320487520U CN 203422915 U CN203422915 U CN 203422915U
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pull
transistor
terminal
shift register
down control
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谭文
祁小敬
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Chengdu BOE Optoelectronics Technology Co Ltd
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Abstract

本实用新型提供一种移位寄存单元,该移位寄存单元包括第一驱动信号输入端、第一驱动信号输出端、第一时钟信号输入端、第一上拉晶体管、第一输出下拉晶体管、开关晶体管、复位晶体管和自举电容,其中,移位寄存单元还包括下拉单元,该下拉单元的第一端与开关晶体管的栅极相连,下拉单元的第二端与复位晶体管的栅极相连,下拉单元的第三端与第一输出下拉晶体管的栅极相连,复位晶体管的源极与第二低电平输入端相连,第一输出下拉晶体管的源极与第三低电平输入端相连。本实用新型还提供一种包括移位寄存单元的移位寄存器,一种包括该移位寄存器的栅极驱动器和一种包括该栅极驱动器的显示装置。移位寄存单元中可以使用耗尽型晶体管。

The utility model provides a shift register unit, which comprises a first drive signal input terminal, a first drive signal output terminal, a first clock signal input terminal, a first pull-up transistor, a first output pull-down transistor, A switch transistor, a reset transistor, and a bootstrap capacitor, wherein the shift register unit further includes a pull-down unit, the first end of the pull-down unit is connected to the gate of the switch transistor, and the second end of the pull-down unit is connected to the gate of the reset transistor, The third terminal of the pull-down unit is connected to the gate of the first output pull-down transistor, the source of the reset transistor is connected to the second low-level input terminal, and the source of the first output pull-down transistor is connected to the third low-level input terminal. The utility model also provides a shift register including a shift register unit, a gate driver including the shift register and a display device including the gate driver. Depletion mode transistors may be used in the shift register cells.

Description

移位寄存单元、移位寄存器和显示装置Shift register unit, shift register and display device

技术领域technical field

本实用新型涉及显示领域,具体地,涉及一种移位寄存单元、一种包括该移位寄存单元的移位寄存器和一种包括该移位寄存器的显示装置。The utility model relates to the display field, in particular to a shift register unit, a shift register including the shift register unit and a display device including the shift register.

背景技术Background technique

随着平板显示的发展,高分辨率、窄边框成为发展的潮流,而在显示面板上集成栅极驱动电路是实现高分辨率、窄边框显示最重要的解决办法。With the development of flat panel display, high resolution and narrow bezel have become the trend of development, and integrating gate drive circuits on the display panel is the most important solution to realize high resolution and narrow bezel display.

图1中所示的是现有的基本的移位寄存单元的电路图,如图1所示,该基本的移位寄存单元包括上拉晶体管T100、输出下拉晶体管T200、自举电容C1、上拉控制晶体管T300、下拉控制晶体管T400、第一时钟信号输入端CLK、下拉单元13、驱动信号输入端OUT(n-1)和驱动信号输出端OUT(n)。Shown in Fig. 1 is the circuit diagram of the existing basic shift register unit, as shown in Fig. 1, the basic shift register unit includes pull-up transistor T100, output pull-down transistor T200, bootstrap capacitor C1, pull-up The control transistor T300 , the pull-down control transistor T400 , the first clock signal input terminal CLK, the pull-down unit 13 , the driving signal input terminal OUT(n−1), and the driving signal output terminal OUT(n).

在图1中,上拉节点PU点为与上拉晶体管T100的栅极连接的节点,下拉节点PD为与输出下拉晶体管T200的栅极连接的节点。从驱动信号输入端OUT(n-1)输入起始信号STV,VGL表示低电平。图2中所示的是图1中的移位寄存单元在工作时各信号的时序图,VGH表示高电平。In FIG. 1 , the pull-up node PU is a node connected to the gate of the pull-up transistor T100 , and the pull-down node PD is a node connected to the gate of the output pull-down transistor T200 . The start signal STV is input from the drive signal input terminal OUT (n-1), and VGL indicates a low level. What is shown in FIG. 2 is the timing diagram of each signal when the shift register unit in FIG. 1 is working, and VGH represents a high level.

a-si(非晶硅)和p-si(多晶硅)制成的薄膜晶体管为增强型薄膜晶体管,当使用增强型TFT技术制作该基本的移位寄存单元电路时,图1中所示的移位寄存单元可以正常工作(如图2的实线部分所示)。Thin film transistors made of a-si (amorphous silicon) and p-si (polysilicon) are enhancement-type thin-film transistors. The bit register unit can work normally (shown by the solid line in Figure 2).

近年来,氧化物薄膜晶体管作为一种非常有潜力的半导体技术,相比于p-si工艺更简单,成本更低,相比于a-si迁移率更高,因而越来越受到重视,未来很可能是各种显示面板、尤其是OLED(有机发光二极管)和柔性显示的主流背板驱动技术。然而氧化物薄膜晶体管具有耗尽型的特点,如图2中虚线部分所示,将作为耗尽型薄膜晶体管的氧化物薄膜晶体管直接应用于图1中所示的电路时,并不能正常工作。In recent years, oxide thin film transistors, as a very potential semiconductor technology, are simpler and cheaper than p-si processes, and have higher mobility than a-si, so they are getting more and more attention. In the future It is likely to be the mainstream backplane driving technology for various display panels, especially OLED (Organic Light Emitting Diode) and flexible displays. However, the oxide thin film transistor has a depletion-type characteristic, as shown by the dotted line in FIG. 2 , when the oxide thin-film transistor as a depletion-type thin film transistor is directly applied to the circuit shown in FIG. 1 , it cannot work normally.

原因解释如下:耗尽型薄膜晶体管与增强型薄膜晶体管的差别见图3和图4,图3为增强型薄膜晶体管的特性曲线图,纵轴为薄膜晶体管漏极的电流,横轴为栅源极的电压,从图3中所示的增强型薄膜晶体管的特性曲线图中可以看出,当Vgs(栅源电压)电压为零时,id(漏极电流)为零,说明Vgs为零时,增强型薄膜晶体管完全关闭。图4为耗尽型薄膜晶体管的特性曲线图,同样纵轴为漏极电流,横轴为栅源电压,但该图显示的却是Vgs为零时,id远大于零,而只有在栅源电压为一定的负电压时,id才为零。The reasons are explained as follows: The difference between the depletion-mode TFT and the enhancement-mode TFT is shown in Figure 3 and Figure 4. Figure 3 is the characteristic curve of the enhancement-mode TFT, the vertical axis is the drain current of the TFT, and the horizontal axis is the gate-source It can be seen from the characteristic curve of the enhanced thin film transistor shown in Figure 3 that when the Vgs (gate-source voltage) voltage is zero, id (drain current) is zero, indicating that when Vgs is zero , the enhancement mode TFT is completely turned off. Figure 4 is a characteristic curve of a depletion-mode thin-film transistor. Similarly, the vertical axis is the drain current, and the horizontal axis is the gate-source voltage. However, this figure shows that when Vgs is zero, id is much greater than zero, and only when the gate-source When the voltage is a certain negative voltage, id is zero.

实用新型内容Utility model content

本实用新型的目的在于提供一种移位寄存单元、一种包括该移位寄存单元的移位寄存器、一种包括该移位寄存器的栅极驱动器和一种包括该栅极驱动器的显示装置,所述移位寄存单元中可以使用耗尽型薄膜晶体管。The purpose of the utility model is to provide a shift register unit, a shift register including the shift register unit, a gate driver including the shift register, and a display device including the gate driver, A depletion type thin film transistor may be used in the shift register unit.

为了实现上述目的,作为本实用新型的一个方面,提供一种移位寄存单元,该移位寄存单元包括第一驱动信号输入端、第一驱动信号输出端、第一时钟信号输入端、第一上拉晶体管、第一输出下拉晶体管、开关晶体管、复位晶体管和自举电容,所述开关晶体管的漏极与所述第一驱动信号输入端相连,所述第一输出下拉晶体管的漏极与所述第一驱动信号输出端相连,所述自举电容的一端与所述第一上拉晶体管的栅极相连,另一端与所述第一驱动信号输出端相连,所述第一上拉晶体管的栅极与所述开关晶体管的源极相连,所述第一上拉晶体管的漏极与所述第一时钟信号输入端相连,所述第一上拉晶体管的漏极与所述第一驱动信号输出端相连,所述复位晶体管的漏极与所述开关晶体管的源极相连,其中,所述移位寄存单元还包括下拉单元,该下拉单元的第一端与所述开关晶体管的栅极相连,所述下拉单元的第二端与所述复位晶体管的栅极相连,所述下拉单元的第三端与所述第一输出下拉晶体管的栅极相连,所述复位晶体管的源极与能够输出第二低电平的第二低电平输入端相连,所述第一输出下拉晶体管的源极与能够输出第三低电平的第三低电平输入端相连,在求值阶段,所述下拉单元能够向所述第一输出下拉晶体管的栅极、所述开关晶体管的栅极以及所述复位晶体管的栅极输出第一低电平,所述第一低电平与所述第二低电平的差值小于所述复位晶体管的阈值电压,所述第一低电平与所述第三低电平的差值小于所述第一输出下拉晶体管的阈值电压。In order to achieve the above object, as an aspect of the present invention, a shift register unit is provided, the shift register unit includes a first drive signal input terminal, a first drive signal output terminal, a first clock signal input terminal, a first A pull-up transistor, a first output pull-down transistor, a switch transistor, a reset transistor and a bootstrap capacitor, the drain of the switch transistor is connected to the first drive signal input end, the drain of the first output pull-down transistor is connected to the The first drive signal output end is connected, one end of the bootstrap capacitor is connected to the gate of the first pull-up transistor, and the other end is connected to the first drive signal output end, and the first pull-up transistor The gate is connected to the source of the switch transistor, the drain of the first pull-up transistor is connected to the first clock signal input terminal, and the drain of the first pull-up transistor is connected to the first drive signal The output terminal is connected, the drain of the reset transistor is connected to the source of the switch transistor, wherein the shift register unit further includes a pull-down unit, and the first end of the pull-down unit is connected to the gate of the switch transistor , the second end of the pull-down unit is connected to the gate of the reset transistor, the third end of the pull-down unit is connected to the gate of the first output pull-down transistor, and the source of the reset transistor is connected to the gate capable of outputting The second low level input terminal of the second low level is connected, the source of the first output pull-down transistor is connected with the third low level input terminal capable of outputting the third low level, and in the evaluation stage, the The pull-down unit can output a first low level to the gate of the first output pull-down transistor, the gate of the switch transistor, and the gate of the reset transistor, and the first low level and the second low level The level difference is smaller than the threshold voltage of the reset transistor, and the difference between the first low level and the third low level is smaller than the threshold voltage of the first output pull-down transistor.

优选地,所述移位寄存单元包括第一下拉模块和第二下拉模块,所述第一下拉模块用于在预充电阶段向所述第二端和所述第三端输出第二低电平,该第二低电平与所述第三低电平的差值小于所述第一输出下拉晶体管的阈值电压,所述第二下拉模块用于在所述求值阶段向所述第二端和所述第三端输出所述第一低电平。Preferably, the shift register unit includes a first pull-down module and a second pull-down module, and the first pull-down module is used to output a second low voltage to the second terminal and the third terminal during the precharging phase. level, the difference between the second low level and the third low level is less than the threshold voltage of the first output pull-down transistor, and the second pull-down module is used to send The second terminal and the third terminal output the first low level.

优选地,所述移位寄存单元包括第二驱动信号输出端,该第二驱动信号输出端与所述第一驱动信号输出端同步,且能够输出所述高电平和所述第一低电平,所述第二下拉模块包括第一下拉控制晶体管和第二驱动信号输入端,该第一下拉控制晶体管的栅极与所述第二驱动信号输出端相连,所述第一下拉控制晶体管的源极与所述第一低电平输入端相连,所述第一下拉控制晶体管的漏极与所述第二端和所述第三端连接,所述第二驱动信号输入端与所述第一驱动信号输入端同步,且所述第二驱动信号输入端能够输入高电平和所述第一低电平,所述第二驱动信号输入端与第一端相连。Preferably, the shift register unit includes a second drive signal output terminal, the second drive signal output terminal is synchronized with the first drive signal output terminal, and can output the high level and the first low level , the second pull-down module includes a first pull-down control transistor and a second drive signal input terminal, the gate of the first pull-down control transistor is connected to the second drive signal output terminal, and the first pull-down control transistor The source of the transistor is connected to the first low-level input terminal, the drain of the first pull-down control transistor is connected to the second terminal and the third terminal, and the second drive signal input terminal is connected to the The first drive signal input terminal is synchronous, and the second drive signal input terminal can input high level and the first low level, and the second drive signal input terminal is connected to the first terminal.

优选地,所述第二下拉模块还包括第二下拉控制晶体管,该第二下拉控制晶体管的栅极与所述第二驱动信号输出端相连,所述第二下拉控制晶体管的源极与所述第一低电平输入端相连,所述第二下拉控制晶体管的漏极与所述第一端相连。Preferably, the second pull-down module further includes a second pull-down control transistor, the gate of the second pull-down control transistor is connected to the second drive signal output terminal, and the source of the second pull-down control transistor is connected to the The first low-level input terminal is connected, and the drain of the second pull-down control transistor is connected to the first terminal.

优选地,所述移位寄存单元还包括第二驱动信号输出模块,该第二驱动信号输出模块包括第二上拉晶体管和第二输出下拉晶体管,所述第二上拉晶体管的栅极与所述第一上拉晶体管的栅极相连,所述第二上拉晶体管的漏极与所述第一时钟信号输入端相连,所述第二上拉晶体管的源极与所述第二驱动信号输出端相连,所述第二输出下拉晶体管的栅极与所述第一输出下拉晶体管的栅极相连,所述第二输出下拉晶体管的源极与所述第一低电平输入端相连,所述第二输出下拉晶体管的漏极与所述第二驱动信号输出端相连。Preferably, the shift register unit further includes a second drive signal output module, the second drive signal output module includes a second pull-up transistor and a second output pull-down transistor, the gate of the second pull-up transistor is connected to the The gate of the first pull-up transistor is connected, the drain of the second pull-up transistor is connected to the first clock signal input terminal, the source of the second pull-up transistor is connected to the second drive signal output terminal, the gate of the second output pull-down transistor is connected to the gate of the first output pull-down transistor, the source of the second output pull-down transistor is connected to the first low-level input terminal, and the The drain of the second output pull-down transistor is connected to the second driving signal output terminal.

优选地,所述移位寄存单元还包括第二时钟信号输入端,该第二时钟信号输入端与所述第一时钟信号输入端相反,所述第一下拉模块包括第三下拉控制晶体管和第四下拉控制晶体管,所述第四下拉控制晶体管的电阻小于第三下拉晶体管的电阻,所述第三下拉控制晶体管的栅极和漏极与所述第二时钟信号输入端相连,所述第三下拉控制晶体管的源极与所述第二端相连,所述第四下拉控制晶体管的栅极与所述第二驱动信号输入端相连,所述第四下拉控制晶体管的源极与所述第二低电平输入端相连,所述第四下拉控制晶体管的漏极与所述第二端相连,所述第二端与所述第三端相连。Preferably, the shift register unit further includes a second clock signal input end, which is opposite to the first clock signal input end, and the first pull-down module includes a third pull-down control transistor and A fourth pull-down control transistor, the resistance of the fourth pull-down control transistor is smaller than the resistance of the third pull-down transistor, the gate and drain of the third pull-down control transistor are connected to the second clock signal input terminal, and the first The sources of the three pull-down control transistors are connected to the second terminal, the gate of the fourth pull-down control transistor is connected to the second drive signal input terminal, and the source of the fourth pull-down control transistor is connected to the first terminal. The two low-level input terminals are connected, the drain of the fourth pull-down control transistor is connected to the second terminal, and the second terminal is connected to the third terminal.

优选地,所述移位寄存单元还包括第二时钟信号输入端,该第二时钟信号输入端与所述第一时钟信号输入端相反,所述第一下拉模块包括第三下拉控制晶体管、第四下拉控制晶体管、第五下拉控制晶体管和第六下拉控制晶体管,所述第四下拉控制晶体管的电阻小于第三下拉晶体管的电阻,所述第六下拉控制晶体管的电阻小于所述第五下拉控制晶体管的电阻,所述第三下拉控制晶体管的栅极和漏极与所述第二时钟信号输入端相连,所述第三下拉控制晶体管的源极与所述第四下拉控制晶体管的漏极相连,所述第四下拉控制晶体管的栅极与所述第二驱动信号输入端相连,所述第四下拉控制晶体管的源极与所述第二低电平输入端相连,所述第四下拉控制晶体管的漏极与所述第三下拉控制晶体管的源极相连,所述第五下拉控制晶体管的栅极和漏极与所述第二时钟信号输入端相连,所述第五下拉控制晶体管的源极与所述第二端相连,所述第六下拉控制晶体管的栅极与所述第二时钟信号输入端相连,所述第六下拉控制晶体管的源极与所述第二低电平输入端相连,所述第六下拉控制晶体管的漏极与所述第二端相连,所述第二端与所述第三端相连。Preferably, the shift register unit further includes a second clock signal input end, which is opposite to the first clock signal input end, and the first pull-down module includes a third pull-down control transistor, A fourth pull-down control transistor, a fifth pull-down control transistor, and a sixth pull-down control transistor, the resistance of the fourth pull-down control transistor is smaller than the resistance of the third pull-down transistor, and the resistance of the sixth pull-down control transistor is smaller than that of the fifth pull-down control transistor. Control the resistance of the transistor, the gate and drain of the third pull-down control transistor are connected to the second clock signal input terminal, the source of the third pull-down control transistor is connected to the drain of the fourth pull-down control transistor The gate of the fourth pull-down control transistor is connected to the second drive signal input terminal, the source of the fourth pull-down control transistor is connected to the second low-level input terminal, and the fourth pull-down control transistor is connected to the second low-level input terminal. The drain of the control transistor is connected to the source of the third pull-down control transistor, the gate and drain of the fifth pull-down control transistor are connected to the second clock signal input terminal, and the fifth pull-down control transistor The source is connected to the second end, the gate of the sixth pull-down control transistor is connected to the second clock signal input end, the source of the sixth pull-down control transistor is connected to the second low-level input The drain of the sixth pull-down control transistor is connected to the second terminal, and the second terminal is connected to the third terminal.

优选地,所述移位寄存单元还包括第二时钟信号输入端,该第二时钟信号输入端与所述第一时钟信号输入端相反,所述第一下拉模块包括第七下拉控制晶体管和下拉电容,该下拉电容的电阻大于所述第七下拉控制晶体管的电阻,所述下拉电容的一端与所述第二时钟信号输入端相连,所述下拉电容的另一端与所述第二端相连,所述第七下拉控制晶体管的栅极与所述第二驱动信号输入端相连,所述第七下拉控制晶体管的源极与所述第二低电平输入端相连,所述第七下拉控制晶体管的漏极与所述第二端相连,所述第二端与所述第三端相连。Preferably, the shift register unit further includes a second clock signal input end, which is opposite to the first clock signal input end, and the first pull-down module includes a seventh pull-down control transistor and A pull-down capacitor, the resistance of the pull-down capacitor is greater than the resistance of the seventh pull-down control transistor, one end of the pull-down capacitor is connected to the second clock signal input end, and the other end of the pull-down capacitor is connected to the second end , the gate of the seventh pull-down control transistor is connected to the second drive signal input terminal, the source of the seventh pull-down control transistor is connected to the second low-level input terminal, and the seventh pull-down control transistor The drain of the transistor is connected to the second terminal, and the second terminal is connected to the third terminal.

优选地,所述第一上拉晶体管、第一输出下拉晶体管、开关晶体管、复位晶体管中的至少一个为耗尽型晶体管。Preferably, at least one of the first pull-up transistor, the first output pull-down transistor, the switch transistor and the reset transistor is a depletion transistor.

优选地,所述第一上拉晶体管、第一输出下拉晶体管、开关晶体管、复位晶体管均为N沟道薄膜晶体管。Preferably, the first pull-up transistor, the first output pull-down transistor, the switch transistor and the reset transistor are all N-channel thin film transistors.

作为本实用新型的另一个方面,还提供一种移位寄存器,该移位寄存器包括多级移位寄存单元,其中,所述移位寄存单元为本实用新型所提供的上述移位寄存单元,下一级所述移位寄存单元的第一驱动信号输入端与上一级所述移位寄存单元的第一驱动信号输出端相连。As another aspect of the present invention, a shift register is also provided, which includes a multi-stage shift register unit, wherein the shift register unit is the above-mentioned shift register unit provided by the present invention, The first driving signal input end of the shift register unit of the next stage is connected to the first drive signal output end of the shift register unit of the upper stage.

作为本实用新型的还一个方面,提供一种显示装置,该显示装置包括薄膜晶体管、数据线、栅线和与该栅线电连接的移位寄存器,其中,所述移位寄存器为本实用新型所提供的上述移位寄存器,所述移位寄存器的第一驱动信号输出端与所述栅线连接。As another aspect of the present invention, a display device is provided, which includes a thin film transistor, a data line, a gate line, and a shift register electrically connected to the gate line, wherein the shift register is a In the above-mentioned shift register provided, the first driving signal output end of the shift register is connected to the gate line.

本实用新型所提供的移位寄存单元中,在求值阶段,第一输出下拉晶体管的栅极电位为第一低电平,源极电位为第三低电平,因此,第一输出下拉晶体管在求值阶段完全关闭;复位晶体管的源极电位为第二低电平,栅极电位为第一低电平,因此,复位晶体管完全关闭;开关晶体管的源极电位与上拉节点的电位相同(高于高电平),开关晶体管的栅极电位为第一低电平,因此,开关晶体管也完全关闭。In the shift register unit provided by the utility model, in the evaluation phase, the gate potential of the first output pull-down transistor is the first low level, and the source potential is the third low level, therefore, the first output pull-down transistor It is fully off during the evaluation phase; the source of the reset transistor is at the second low level and the gate is at the first low level, so the reset transistor is fully off; the source of the switching transistor is at the same potential as the pull-up node (higher than the high level), the gate potential of the switching transistor is the first low level, therefore, the switching transistor is also completely turned off.

即使第一输出下拉晶体管、开关晶体管以及复位晶体管均为耗尽型晶体管,该第一输出下拉晶体管、开关晶体管以及复位晶体管也可以在求值极端完全关闭,不会产生漏电,从而可以使上拉节点耦合至较高的电位。Even though the first output pull-down transistor, switch transistor, and reset transistor are all depletion transistors, the first output pull-down transistor, switch transistor, and reset transistor can be completely turned off at the evaluation end without leakage, so that the pull-up The node is coupled to a higher potential.

附图说明Description of drawings

附图是用来提供对本实用新型的进一步理解,并且构成说明书的一部分,与下面的具体实施方式一起用于解释本实用新型,但并不构成对本实用新型的限制。在附图中:The accompanying drawings are used to provide a further understanding of the utility model, and constitute a part of the description, together with the following specific embodiments, are used to explain the utility model, but do not constitute a limitation to the utility model. In the attached picture:

图1是现有基本的移位寄存单元的电路图;Fig. 1 is the circuit diagram of existing basic shift register unit;

图2是图1中所示的移位寄存单元在工作时各信号的时序图;Fig. 2 is the timing diagram of each signal when the shift register unit shown in Fig. 1 works;

图3是增强型晶体管的特性曲线图;Fig. 3 is a characteristic curve diagram of an enhancement transistor;

图4是耗尽型晶体管的特性曲线图;Fig. 4 is a characteristic curve diagram of a depletion mode transistor;

图5是本实用新型所提供的移位寄存单元的原理图;Fig. 5 is a schematic diagram of the shift register unit provided by the utility model;

图6是本实用新型所提供的移位寄存单元第一种实施方式的电路图;Fig. 6 is a circuit diagram of the first embodiment of the shift register unit provided by the present invention;

图7是本实用新型所提供的移位寄存单元的第二种实施方式的电路图;7 is a circuit diagram of a second embodiment of the shift register unit provided by the present invention;

图8是本实用新型所提供的移位寄存单元的第三种实施方式的电路图;Fig. 8 is a circuit diagram of a third embodiment of the shift register unit provided by the present invention;

图9是本实用新型所提供的移位寄存单元的第四种实施方式的电路图;9 is a circuit diagram of a fourth embodiment of the shift register unit provided by the present invention;

图10是本实用新型所提供的移位寄存单元工作时各信号的时序图;Fig. 10 is a timing diagram of each signal when the shift register unit provided by the present invention works;

图11是本实用新型所提供的移位寄存器的示意图。Fig. 11 is a schematic diagram of the shift register provided by the present invention.

附图标记说明Explanation of reference signs

Figure BDA00003646918000061
Figure BDA00003646918000061

Figure BDA00003646918000071
Figure BDA00003646918000071

具体实施方式Detailed ways

以下结合附图对本实用新型的具体实施方式进行详细说明。应当理解的是,此处所描述的具体实施方式仅用于说明和解释本实用新型,并不用于限制本实用新型。The specific embodiment of the utility model will be described in detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to illustrate and explain the utility model, and are not intended to limit the utility model.

如图5所示,作为本实用新型的一个方面,提供一种移位寄存单元,该移位寄存单元包括第一驱动信号输入端10、第一驱动信号输出端11、第一时钟信号输入端CLK、第一上拉晶体管T1、第一输出下拉晶体管T2、开关晶体管T3、复位晶体管T4和自举电容C1,开关晶体管T3的漏极与第一驱动信号输入端10相连,第一输出下拉晶体管T2的漏极与第一驱动信号输出端相连11,自举电容C1的一端与第一上拉晶体管T1的栅极相连,另一端与第一驱动信号输出端11相连,第一上拉晶体管T1的栅极与开关晶体管T3的源极相连,第一上拉晶体管T1的漏极与第一时钟信号输入端CLK相连,第一上拉晶体管T1的漏极与第一驱动信号输出端11相连,复位晶体管T4的漏极与开关晶体管T3的源极相连,其中,所述移位寄存单元还包括下拉单元13,该下拉单元13的第一端a与开关晶体管T3的栅极相连,下拉单元13的第二端b与复位晶体管T4的栅极相连,下拉单元13的第三端c与第一输出下拉晶体管T2的栅极相连,复位晶体管T4的源极与能够输出第二低电平VGL2的第二低电平输入端相连,第一输出下拉晶体管T2的源极与能够输出第三低电平VGL3的第三低电平输入端相连,在求值阶段,下拉单元13可以向第一输出下拉晶体管T2的栅极、开关晶体管T3的栅极以及复位晶体管T4的栅极输出第一低电平VGL1,该第一低电平VGL1与第二低电平VGL2的差值小于复位晶体管T4的阈值电压(即,VGL1-VGL2<Vth,T4),第一低电平VGL1与第三低电平VGL3的差值小于第一输出下拉晶体管T2的阈值电压(即,VGL1-VGL3<Vth,T2)。As shown in Figure 5, as an aspect of the present invention, a shift register unit is provided, which includes a first drive signal input terminal 10, a first drive signal output terminal 11, a first clock signal input terminal CLK, the first pull-up transistor T1, the first output pull-down transistor T2, the switch transistor T3, the reset transistor T4 and the bootstrap capacitor C1, the drain of the switch transistor T3 is connected to the first drive signal input terminal 10, and the first output pull-down transistor The drain of T2 is connected to the first drive signal output end 11, one end of the bootstrap capacitor C1 is connected to the gate of the first pull-up transistor T1, and the other end is connected to the first drive signal output end 11, the first pull-up transistor T1 The gate of the first pull-up transistor T1 is connected to the source of the switching transistor T3, the drain of the first pull-up transistor T1 is connected to the first clock signal input terminal CLK, and the drain of the first pull-up transistor T1 is connected to the first drive signal output terminal 11, The drain of the reset transistor T4 is connected to the source of the switching transistor T3, wherein the shift register unit further includes a pull-down unit 13, the first terminal a of the pull-down unit 13 is connected to the gate of the switching transistor T3, and the pull-down unit 13 The second terminal b of the pull-down unit 13 is connected to the gate of the reset transistor T4, the third terminal c of the pull-down unit 13 is connected to the gate of the first output pull-down transistor T2, and the source of the reset transistor T4 is connected to the second low level VGL2. The second low-level input terminal is connected, and the source of the first output pull-down transistor T2 is connected to the third low-level input terminal capable of outputting the third low level VGL3. In the evaluation phase, the pull-down unit 13 can output to the first The gate of the pull-down transistor T2, the gate of the switching transistor T3 and the gate of the reset transistor T4 output the first low level VGL1, and the difference between the first low level VGL1 and the second low level VGL2 is smaller than that of the reset transistor T4 Threshold voltage (that is, VGL1-VGL2<V th, T4 ), the difference between the first low level VGL1 and the third low level VGL3 is smaller than the threshold voltage of the first output pull-down transistor T2 (that is, VGL1-VGL3<V th ,T2 ).

本领域技术人员应当理解的是,第一上拉晶体管T1的栅极形成为上拉节点PU,第一输出下拉晶体管T2的栅极形成为下拉节点PD,该下拉节点PD与下拉单元13的第三端c重合(参见图6至图9)。Those skilled in the art should understand that the gate of the first pull-up transistor T1 is formed as a pull-up node PU, the gate of the first output pull-down transistor T2 is formed as a pull-down node PD, and the pull-down node PD is connected to the first pull-down node PU of the pull-down unit 13. The three ends c coincide (see Figure 6 to Figure 9).

在求值阶段(即,图10中的阶段②),第一输出下拉晶体管T2的栅极电位为第一低电平VGL1,源极电位为第三低电平VGL3,因此,第一输出下拉晶体管T2在求值阶段完全关闭;复位晶体管T4的源极电位为第二低电平VGL2,栅极电位为第一低电平VGL1,因此,复位晶体管T4完全关闭;开关晶体管T3的源极电位与上拉节点PU的电位相同(高于高电平VGH),开关晶体管T3的栅极电位为第一低电平VGL1,因此,开关晶体管T3也完全关闭。In the evaluation stage (that is, stage ② in Figure 10), the gate potential of the first output pull-down transistor T2 is the first low level VGL1, and the source potential is the third low level VGL3, therefore, the first output pull-down Transistor T2 is completely closed during the evaluation stage; the source potential of reset transistor T4 is the second low level VGL2, and the gate potential is the first low level VGL1, therefore, reset transistor T4 is completely closed; the source potential of switching transistor T3 The potential of the pull-up node PU is the same (higher than the high level VGH), and the gate potential of the switch transistor T3 is the first low level VGL1 , therefore, the switch transistor T3 is also completely turned off.

即使第一输出下拉晶体管T2、开关晶体管T3以及复位晶体管T4均为耗尽型晶体管,该第一输出下拉晶体管T2、开关晶体管T3以及复位晶体管T4也可以在求值极端完全关闭,不会产生漏电,从而可以使上拉节点耦合至较高的电位,使第一上拉晶体管T1开启,并使得第一驱动信号输出端可以输出高电平VGH。Even if the first output pull-down transistor T2, switch transistor T3 and reset transistor T4 are all depletion transistors, the first output pull-down transistor T2, switch transistor T3 and reset transistor T4 can be completely turned off at the evaluation end without leakage , so that the pull-up node can be coupled to a higher potential, the first pull-up transistor T1 can be turned on, and the first driving signal output terminal can output a high level VGH.

应当理解的是,在预充电阶段(即,图10中的阶段①),下拉单元13的第一端a应当可以向开关晶体管T3的栅极输出高电平,使得开关晶体管T3开启,对上拉节点PU进行充电。并且,在预充电阶段,复位晶体管T4和第一输出下拉晶体管T2应当至少大致关闭,以保证预充电阶段的正常进行。It should be understood that, in the pre-charging stage (that is, stage ① in FIG. 10 ), the first terminal a of the pull-down unit 13 should be able to output a high level to the gate of the switching transistor T3, so that the switching transistor T3 is turned on, and the upper Pull node PU to charge. Moreover, in the pre-charging phase, the reset transistor T4 and the first output pull-down transistor T2 should be at least roughly turned off, so as to ensure the normal progress of the pre-charging phase.

还应当理解的是,在复位阶段,下拉单元13的第二端b应当可以向复位晶体管T4的栅极输出高电平VGH,使得复位晶体管T4开启,从而对上拉节点PU进行放电。It should also be understood that in the reset phase, the second terminal b of the pull-down unit 13 should be able to output a high level VGH to the gate of the reset transistor T4, so that the reset transistor T4 is turned on, thereby discharging the pull-up node PU.

下面结合图6至图9描述下拉单元13的具体结构。The specific structure of the pull-down unit 13 is described below with reference to FIGS. 6 to 9 .

如图6至图9中所示,所述移位寄存单元可以包括第一下拉模块13a和第二下拉模块13b,第一下拉模块13a用于在预充电阶段(即,图10中的阶段①)向下拉单元的第二端b和下拉单元的第三端c输出第二低电平VGL2,该第二低电平VGL2与第三低电平VGL3的差值小于第一输出下拉晶体管T2的阈值电压Vth,T2,(即VGL2-VGL3<Vth,T2),第二下拉模块13b用于在所述求值阶段向下拉单元的第一端a、第二端b和第三端c输出第一低电平VGL1。As shown in FIGS. 6 to 9, the shift register unit may include a first pull-down module 13a and a second pull-down module 13b, and the first pull-down module 13a is used for Stage ①) Outputting the second low level VGL2 to the second terminal b of the pull-down unit and the third terminal c of the pull-down unit, the difference between the second low level VGL2 and the third low level VGL3 is smaller than the first output pull-down transistor The threshold voltage V th,T2 of T2, (that is, VGL2-VGL3<V th,T2 ), the second pull-down module 13b is used to pull down the first terminal a, the second terminal b and the third terminal of the unit during the evaluation stage Terminal c outputs the first low level VGL1.

在预充电阶段,第一输出下拉晶体管T2完全关闭,复位晶体管T4大致关闭,因此,可以正常对上拉节点PU进行充电。In the pre-charging stage, the first output pull-down transistor T2 is completely turned off, and the reset transistor T4 is roughly turned off, so the pull-up node PU can be charged normally.

更具体地,为了使得第二下拉模块13b可以在求值阶段向下拉单元的第一端a、第二端b和第三端c输出第一低电平VGL1,如图6至9中所示,所述移位寄存单元还可以包括第二驱动信号输出端12,该第二驱动信号输出端12与第一驱动信号输出端11同步,且能够输出高电平VGH和第一低电平VGL1,第二下拉模块13b可以包括第一下拉控制晶体管T10和第二驱动信号输入端14,该第一下拉控制晶体管T10的栅极与第二驱动信号输出端12相连,第一下拉控制晶体管T10的源极与所述第一低电平输入端相连,第一下拉控制晶体管T10的漏极与所述下拉单元的第二端b和第三端c连接,第二驱动信号输入端14与所述下拉单元的第一端a相连,第二驱动信号输入端14与第一驱动信号输入端10同步,并且第二驱动信号输入端14可以向第一端a输入高电平VGH和第一低电平VGL1。More specifically, in order to enable the second pull-down module 13b to output the first low level VGL1 to the first terminal a, the second terminal b and the third terminal c of the pull-down unit during the evaluation phase, as shown in FIGS. 6 to 9 , the shift register unit may also include a second drive signal output terminal 12, the second drive signal output terminal 12 is synchronized with the first drive signal output terminal 11, and can output a high level VGH and a first low level VGL1 , the second pull-down module 13b may include a first pull-down control transistor T10 and a second drive signal input terminal 14, the gate of the first pull-down control transistor T10 is connected to the second drive signal output terminal 12, and the first pull-down control transistor T10 is connected to the second drive signal output terminal 12. The source of the transistor T10 is connected to the first low-level input terminal, the drain of the first pull-down control transistor T10 is connected to the second terminal b and the third terminal c of the pull-down unit, and the second drive signal input terminal 14 is connected to the first terminal a of the pull-down unit, the second drive signal input terminal 14 is synchronized with the first drive signal input terminal 10, and the second drive signal input terminal 14 can input high level VGH and The first low level VGL1.

第二驱动信号输入端14与第一驱动信号输入端10同步的意思是,当通过第一驱动信号输入端10向开关晶体管T3的漏极输入高电平VGH时,通过第二驱动信号输入端14向开关晶体管T3的栅极输入高电平VGH,当通过第一驱动信号输入端10向开关晶体管T3的漏极输入低电平时,通过第二驱动信号输入端14向开关晶体管T3的漏极输入第一低电平VGL1。The second drive signal input terminal 14 is synchronized with the first drive signal input terminal 10, which means that when a high level VGH is input to the drain of the switching transistor T3 through the first drive signal input terminal 10, the second drive signal input terminal 14 inputs a high level VGH to the gate of the switching transistor T3, and when a low level is input to the drain of the switching transistor T3 through the first drive signal input terminal 10, the VGH is input to the drain of the switching transistor T3 through the second drive signal input terminal 14 Input the first low level VGL1.

第二驱动信号输入端14可以确保开关晶体管T3在预充电阶段开启,并在求值阶段关闭。The second drive signal input 14 can ensure that the switching transistor T3 is turned on during the pre-charging phase and turned off during the evaluation phase.

所谓第二驱动信号输出端12与第一驱动信号输出端11同步是指,当第一驱动信号输出端11输出高电平时,第二驱动信号输出端12也输出高电平,当第一驱动信号输出端11输出低电平时,第二驱动信号输出端12也输出低电平。第一驱动信号输出端11只在求值阶段输出高电平VGH,因此第二驱动信号输出端12也仅在求值阶段输出高电平VGH。The so-called synchronization of the second drive signal output terminal 12 with the first drive signal output terminal 11 means that when the first drive signal output terminal 11 outputs a high level, the second drive signal output terminal 12 also outputs a high level. When the signal output terminal 11 outputs a low level, the second drive signal output terminal 12 also outputs a low level. The first drive signal output terminal 11 only outputs high level VGH during the evaluation phase, so the second drive signal output terminal 12 also outputs high level VGH only during the evaluation phase.

在求值阶段,第一下拉控制晶体管T10的栅极为第二驱动信号输出端12输出的高电平VGH,所以第一下拉控制晶体管T10导通,第一下拉控制晶体管T10的漏极电位为第一低电平VGL1,以能够将所述下拉单元的第二端b和第三端c的电位拉低至第一低电平VGL1。In the evaluation phase, the gate of the first pull-down control transistor T10 is the high level VGH output by the second drive signal output terminal 12, so the first pull-down control transistor T10 is turned on, and the drain of the first pull-down control transistor T10 The potential is the first low level VGL1, so that the potentials of the second terminal b and the third terminal c of the pull-down unit can be pulled down to the first low level VGL1.

为了确保开关晶体管T3在求值阶段关闭,优选地,第二下拉模块13b还可以包括第二下拉控制晶体管T9,该第二下拉控制晶体管T9的栅极与第二驱动信号输出端12相连,第二下拉控制晶体管T9的源极与所述第一低电平输入端相连,第二下拉控制晶体管T9的漏极与所述下拉单元的第一端a相连。In order to ensure that the switch transistor T3 is closed during the evaluation phase, preferably, the second pull-down module 13b may also include a second pull-down control transistor T9, the gate of the second pull-down control transistor T9 is connected to the second drive signal output terminal 12, the second pull-down control transistor T9 The source of the second pull-down control transistor T9 is connected to the first low-level input terminal, and the drain of the second pull-down control transistor T9 is connected to the first terminal a of the pull-down unit.

在求值阶段,第二驱动信号输出端12向第二下拉控制晶体管T9的栅极输出高电平,使第二下拉控制晶体管T9导通,并进一步将所述下拉单元的第二端a的电位下拉至第一低电平VGL1。In the evaluation stage, the second drive signal output terminal 12 outputs a high level to the gate of the second pull-down control transistor T9, so that the second pull-down control transistor T9 is turned on, and further turns on the second terminal a of the pull-down unit. The potential is pulled down to the first low level VGL1.

下面介绍如何通过第二驱动信号输出端12输出与第一驱动信号同步的第二驱动信号。The following describes how to output the second driving signal synchronized with the first driving signal through the second driving signal output terminal 12 .

如图6至图7中所示,移位寄存单元还包括第二驱动信号输出模块15,该第二驱动信号输出模块15包括第二上拉晶体管T5和第二输出下拉晶体管T6,第二上拉晶体管T5的栅极与第一上拉晶体管T1的栅极(上拉节点PU)相连,第二上拉晶体管T5的漏极与第一时钟信号输入端CLK相连,第二上拉晶体管T5的源极与第二驱动信号输出端12相连,第二输出下拉晶体管T6的栅极与第一输出下拉晶体管T2的栅极(下拉节点PD)相连,第二输出下拉晶体管T6的源极与所述第一低电平输入端相连,第二输出下拉晶体管T6的漏极与第二驱动信号输出端12相连。As shown in FIG. 6 to FIG. 7, the shift register unit further includes a second drive signal output module 15, and the second drive signal output module 15 includes a second pull-up transistor T5 and a second output pull-down transistor T6. The gate of the pull-up transistor T5 is connected to the gate of the first pull-up transistor T1 (pull-up node PU), the drain of the second pull-up transistor T5 is connected to the first clock signal input terminal CLK, and the gate of the second pull-up transistor T5 The source is connected to the second drive signal output terminal 12, the gate of the second output pull-down transistor T6 is connected to the gate (pull-down node PD) of the first output pull-down transistor T2, and the source of the second output pull-down transistor T6 is connected to the The first low level input terminal is connected, and the drain of the second output pull-down transistor T6 is connected to the second driving signal output terminal 12 .

如上所述,第二上拉晶体管T5的栅极也上拉节点PU相连,第二输出下拉晶体管T6与下拉节点PD相连因此,在求值阶段,第二驱动信号输出端12可以输出高电平VGH,而在预充电阶段、复位阶段以及非工作阶段,第二驱动信号输出端12可以输出第一低电平VGL1。因此,在预充电阶段、复位阶段以及非工作阶段,第一下拉控制角晶体管T10和第二下拉控制晶体管T9大致关闭(虽然存在漏电流,但很小)。As mentioned above, the gate of the second pull-up transistor T5 is also connected to the pull-up node PU, and the second output pull-down transistor T6 is connected to the pull-down node PD. Therefore, in the evaluation stage, the second drive signal output terminal 12 can output a high level VGH, while in the pre-charging phase, reset phase and non-working phase, the second driving signal output terminal 12 can output the first low level VGL1. Therefore, in the pre-charging phase, the reset phase and the non-working phase, the first pull-down control corner transistor T10 and the second pull-down control transistor T9 are roughly turned off (although there is a leakage current, it is very small).

第一下拉模块13a有如下作用:第一、在复位阶段拉高下拉节点PD处的电位,从而使得复位晶体管T4导通,对上拉节点PU进行放电;第二、在移位寄存单元的非工作阶段,对下拉节点PD进行交流下拉,即下拉节点PD可以处在交变电压状态,避免长时间的直流偏压导致下第一输出下拉晶体管T2的传输曲线向右偏移老化失效,进而提高整个移位寄存单元的使用寿命。The first pull-down module 13a has the following functions: first, pull up the potential at the pull-down node PD in the reset phase, so that the reset transistor T4 is turned on, and discharge the pull-up node PU; second, in the shift register unit In the non-working stage, the pull-down node PD is AC-pull-down, that is, the pull-down node PD can be in an alternating voltage state, so as to avoid the transmission curve of the first output pull-down transistor T2 shifting to the right and aging failure due to long-term DC bias, and then The service life of the entire shift register unit is improved.

下面结合图7至图9介绍第一下拉模块13a的几种具体实施方式。Several specific implementations of the first pull-down module 13a are introduced below with reference to FIG. 7 to FIG. 9 .

在如图7中所示的第一种实施方式中,所述移位寄存单元还包括第二时钟信号输入端CLKB,该第二时钟信号输入端CLKB与第一时钟信号输入端CLK相反,第一下拉模块13a包括第三下拉控制晶体管T7和第四下拉控制晶体管T8,第四下拉控制晶体管T8的电阻小于第三下拉控制晶体管T7的电阻,第三下拉控制晶体管T7的栅极和漏极与第二时钟信号输入端CLKB相连,第三下拉控制晶体管T7的源极与第二端b相连,第四下拉控制晶体管T8的栅极与第二驱动信号输入端14相连,第四下拉控制晶体管T8的源极与所述第二低电平输入端相连,第四下拉控制晶体管T8的漏极与第二端b相连,第二端b与第三端c相连。In the first implementation manner as shown in FIG. 7, the shift register unit further includes a second clock signal input terminal CLKB, which is opposite to the first clock signal input terminal CLK. A pull-down module 13a includes a third pull-down control transistor T7 and a fourth pull-down control transistor T8, the resistance of the fourth pull-down control transistor T8 is smaller than the resistance of the third pull-down control transistor T7, the gate and drain of the third pull-down control transistor T7 It is connected to the second clock signal input terminal CLKB, the source of the third pull-down control transistor T7 is connected to the second terminal b, the gate of the fourth pull-down control transistor T8 is connected to the second drive signal input terminal 14, and the fourth pull-down control transistor T8 is connected to the second drive signal input terminal 14. The source of T8 is connected to the second low-level input terminal, the drain of the fourth pull-down control transistor T8 is connected to the second terminal b, and the second terminal b is connected to the third terminal c.

其中,第一时钟信号输入端CLK和第二时钟信号输入端CLKB相反的意思是,当从第一时钟信号输入端CLK输入高电平时,从第二时钟信号输入端CLKB输入低电平,当从第一时钟信号输入端CLK输入低电平时,从第二时钟信号输入端CLKB输入高电平。Wherein, the opposite meaning of the first clock signal input terminal CLK and the second clock signal input terminal CLKB means that when a high level is input from the first clock signal input terminal CLK, a low level is input from the second clock signal input terminal CLKB, when When a low level is input from the first clock signal input terminal CLK, a high level is input from the second clock signal input terminal CLKB.

下面结合图7和图10具体介绍本实用新型第一种实施方式的移位寄存单元的工作原理。The working principle of the shift register unit in the first embodiment of the present invention will be described in detail below with reference to FIG. 7 and FIG. 10 .

在预充电阶段(图10中的阶段①),通过第一驱动信号输入端10输入高电平VGH,通过第二驱动信号输入端14输入高电平VGH,通过第一时钟信号输入端CLK输入第一低电平VGL1,通过第二时钟信号输入端CLKB输入高电平VGH。In the pre-charging stage (stage ① in Figure 10), a high-level VGH is input through the first drive signal input terminal 10, a high-level VGH is input through the second drive signal input terminal 14, and a high-level VGH is input through the first clock signal input terminal CLK. The first low level VGL1 is input with the high level VGH through the second clock signal input terminal CLKB.

开关晶体管T3导通,对上拉节点PU点进行充电,使该上拉节点PU处的电位为高电平VGH,此时,第一上拉晶体管T1和第二上拉晶体管T5开启,第一驱动信号输入端11和第二驱动信号输出端12均输出由第一时钟信号输入端CLK输入的第一低电平VGL1,因此,第一下拉控制晶体管T10和第二下拉控制晶体管T9大致关闭。在该阶段,第三下拉控制晶体管T7和第四下拉控制晶体管T8均导通。由于第四下拉控制晶体管T8的电阻小于第三下拉控制晶体管T7的电阻,因此,所述下拉单元的第二端b处的电位接近第二低电平VGL2,由于第二端b与第三端c相连,因此,第三端c(即,下拉节点PD)的电位为第二低电平VGL2。因此,第一输出下拉晶体管T2完全关闭,复位晶体管T4大致关闭,充电过程可以正常进行。The switch transistor T3 is turned on to charge the pull-up node PU, so that the potential at the pull-up node PU is a high level VGH. At this time, the first pull-up transistor T1 and the second pull-up transistor T5 are turned on, and the first pull-up transistor T5 is turned on. Both the drive signal input terminal 11 and the second drive signal output terminal 12 output the first low level VGL1 input by the first clock signal input terminal CLK, therefore, the first pull-down control transistor T10 and the second pull-down control transistor T9 are approximately closed . At this stage, both the third pull-down control transistor T7 and the fourth pull-down control transistor T8 are turned on. Since the resistance of the fourth pull-down control transistor T8 is smaller than the resistance of the third pull-down control transistor T7, the potential at the second end b of the pull-down unit is close to the second low level VGL2, because the second end b is connected to the third end c is connected, therefore, the potential of the third terminal c (that is, the pull-down node PD) is the second low level VGL2. Therefore, the first output pull-down transistor T2 is completely turned off, the reset transistor T4 is roughly turned off, and the charging process can proceed normally.

在求值阶段(图10中的阶段②),通过第一驱动信号输入端10输入低电平,通过第二驱动信号输入端14输入第一低电平VGL1,通过第一时钟信号输入端CLK输入高电平VGH,通过第二时钟信号输入端CLKB输入第一低电平VGL1。In the evaluation stage (stage ② in Figure 10), a low level is input through the first drive signal input terminal 10, the first low level VGL1 is input through the second drive signal input terminal 14, and the first low level VGL1 is input through the first clock signal input terminal CLK. The high level VGH is input, and the first low level VGL1 is input through the second clock signal input terminal CLKB.

上拉节点PU处的电位被自举电容C1耦合至更高,使第一上拉晶体管T1和第二上拉晶体管T5开启,第一驱动信号输出端11和第二驱动信号输出端12可以输出高电平VGH,第一下拉控制晶体管T10和第二下拉控制晶体管T9均因栅极电位为第二驱动信号输出端12输出的高电平VGH而导通,因此,第三端c(即,下拉节点PD)和开关晶体管T3的栅极均被下拉至第一低电平VGL1,从而使得第一输出下拉晶体管T2和开关晶体管T3彻底关闭。在求值阶段,第三下拉控制晶体管T7和第四下拉控制晶体管T8关闭,而下拉单元的第二端b和第三端c相连,因此,第二端b的电位与第三端c的电位相同,均为第一低电平VGL1,使得复位晶体管T4彻底关闭。由此可知,在求值阶段,第一输出下拉晶体管T2、开关晶体管T3和复位晶体管T4均彻底关闭,不存在漏电现象,使得上拉节点PU可以具有较高的电位,确保从第一驱动信号输出端11输出足够高的高电平VGH。The potential at the pull-up node PU is coupled to a higher level by the bootstrap capacitor C1, so that the first pull-up transistor T1 and the second pull-up transistor T5 are turned on, and the first drive signal output terminal 11 and the second drive signal output terminal 12 can output High-level VGH, the first pull-down control transistor T10 and the second pull-down control transistor T9 are both turned on because the gate potential is the high-level VGH output by the second drive signal output terminal 12, therefore, the third terminal c (i.e. , the pull-down node PD) and the gate of the switch transistor T3 are both pulled down to the first low level VGL1, so that the first output pull-down transistor T2 and the switch transistor T3 are completely turned off. In the evaluation stage, the third pull-down control transistor T7 and the fourth pull-down control transistor T8 are closed, and the second terminal b of the pull-down unit is connected to the third terminal c, so the potential of the second terminal b is the same as the potential of the third terminal c Same, both are at the first low level VGL1, so that the reset transistor T4 is completely turned off. It can be seen that, in the evaluation stage, the first output pull-down transistor T2, the switch transistor T3 and the reset transistor T4 are all completely turned off, and there is no leakage phenomenon, so that the pull-up node PU can have a higher potential, ensuring that the first drive signal The output terminal 11 outputs a sufficiently high high level VGH.

在复位阶段,通过第一驱动信号输入端10输入低电平,通过第二驱动信号输入端14输入低电平,通过第一时钟信号输入端CLK输入第一低电平VGL1,通过第二时钟信号输入端CLKB输入高电平VGH。In the reset phase, a low level is input through the first drive signal input terminal 10, a low level is input through the second drive signal input terminal 14, a first low level VGL1 is input through the first clock signal input terminal CLK, and a low level is input through the second clock signal input terminal CLK. Signal input terminal CLKB inputs high level VGH.

第二驱动信号输出端12输出低电平,第一下拉控制晶体管T10和第二下拉控制晶体管T9关闭,开关晶体管T3关闭,从第二时钟信号输入端CLKB输入高电平VGH,从第二驱动信号输入端14输入第一低电平VGL1,第三下拉控制晶体管T7打开,第四下拉控制晶体管T8关闭,因此第二端b处电位为高电平VGH,由于第二端b和第三端c相连,因此,第三端c处的电位也为高电平VGH,因此,第一输出下拉晶体管T2、第二输出下拉晶体管T6以及复位晶体管T4均导通,复位晶体管T4对上拉节点PU进行放电,第一驱动信号输出端输出第三低电平VGL3,第二驱动信号输出端输出第一低电平VGL1。The second drive signal output terminal 12 outputs a low level, the first pull-down control transistor T10 and the second pull-down control transistor T9 are turned off, the switching transistor T3 is turned off, and a high level VGH is input from the second clock signal input terminal CLKB, and the second pull-down control transistor T9 is turned off. The drive signal input terminal 14 inputs the first low level VGL1, the third pull-down control transistor T7 is turned on, and the fourth pull-down control transistor T8 is turned off, so the potential at the second end b is a high level VGH, because the second end b and the third The terminal c is connected, therefore, the potential at the third terminal c is also high level VGH, therefore, the first output pull-down transistor T2, the second output pull-down transistor T6 and the reset transistor T4 are all turned on, and the reset transistor T4 is connected to the pull-up node When the PU is discharging, the first driving signal output terminal outputs the third low level VGL3, and the second driving signal output terminal outputs the first low level VGL1.

在非工作阶段,第三下拉控制晶体管T7处于开启和关闭的交替状态,即下拉节点PD可以处在交变电压状态,避免长时间的直流偏压导致下第一输出下拉晶体管T2的传输曲线向右偏移老化失效,进而提高整个移位寄存单元的使用寿命。In the non-operating stage, the third pull-down control transistor T7 is in an alternate state of being on and off, that is, the pull-down node PD can be in an alternating voltage state, so as to avoid the transmission curve of the first output pull-down transistor T2 falling to The aging of the right offset fails, thereby improving the service life of the entire shift register unit.

在图8所示的第二种实施方式中,所述第一下拉模块13a包括第三下拉控制晶体管T7、第四下拉控制晶体管T8、第五下拉控制晶体管T11和第六下拉控制晶体管T12,第四下拉控制晶体管T8的电阻小于第三下拉控制晶体管T7的电阻,第六下拉控制晶体管T12的电阻小于第五下拉控制晶体管T11的电阻,第三下拉控制晶体管T7的栅极和漏极与第二时钟信号输入端CLKB相连,第三下拉控制晶体管T7的源极与第四下拉控制晶体管T8的漏极相连,第四下拉控制晶体管T8的栅极与第二驱动信号输入端14相连,第四下拉控制晶体管T8的源极与所述第二低电平输入端相连,第四下拉控制晶体管T8的漏极与第三下拉控制晶体管T7的源极相连,第五下拉控制晶体管T11的栅极和漏极与第二时钟信号输入端CLKB相连,第五下拉控制晶体管T11的源极与所述下拉单元的第二端b相连,第六下拉控制晶体管T12的栅极与所述第二时钟信号输入端相连,第六下拉控制晶体管T12的源极与所述第二低电平输入端相连,第六下拉控制晶体管T12的漏极与所述下拉单元的第二端b相连,所述下拉单元的第二端b与所述下拉单元的第三端c相连。In the second implementation manner shown in FIG. 8, the first pull-down module 13a includes a third pull-down control transistor T7, a fourth pull-down control transistor T8, a fifth pull-down control transistor T11 and a sixth pull-down control transistor T12, The resistance of the fourth pull-down control transistor T8 is smaller than the resistance of the third pull-down control transistor T7, the resistance of the sixth pull-down control transistor T12 is smaller than the resistance of the fifth pull-down control transistor T11, and the gate and drain of the third pull-down control transistor T7 are the same as the first pull-down control transistor T7. The two clock signal input terminals CLKB are connected, the source of the third pull-down control transistor T7 is connected to the drain of the fourth pull-down control transistor T8, the gate of the fourth pull-down control transistor T8 is connected to the second drive signal input terminal 14, and the fourth The source of the pull-down control transistor T8 is connected to the second low-level input terminal, the drain of the fourth pull-down control transistor T8 is connected to the source of the third pull-down control transistor T7, and the gate of the fifth pull-down control transistor T11 and The drain is connected to the second clock signal input terminal CLKB, the source of the fifth pull-down control transistor T11 is connected to the second terminal b of the pull-down unit, and the gate of the sixth pull-down control transistor T12 is connected to the second clock signal input terminal. terminal, the source of the sixth pull-down control transistor T12 is connected to the second low-level input terminal, the drain of the sixth pull-down control transistor T12 is connected to the second terminal b of the pull-down unit, and the pull-down unit’s The second end b is connected to the third end c of the pull-down unit.

由于在本实施方式中,第二下拉模块13b以及第二驱动信号输出模块15的结构与第一种实施方式中相同,工作原理也相同,因此,此处仅介绍第二下拉模块13b在移位寄存单元的各个工作阶段以及非工作阶段的状态。Since in this embodiment, the structure of the second pull-down module 13b and the second drive signal output module 15 are the same as those in the first embodiment, and the working principle is also the same, therefore, only the second pull-down module 13b is introduced here. The status of each working phase and non-working phase of the registration unit.

在预充电阶段,第三下拉控制晶体管T7、第四下拉控制晶体管T8、第六下拉控制晶体管T12均开启,由于第三下拉控制晶体管T7的电阻大于第四下拉控制晶体管T8的电阻,因此,第五下拉控制晶体管T11的栅极电位为接近第二低电平VGL2,因此,第五下拉控制晶体管T11大致关闭,所以,第六下拉控制晶体管T12的漏极电位(即,所述下拉单元的第二端b)为第二低电平VGL2,因此可以确保第一输出下拉晶体管T2在预充电阶段彻底关闭,以确保预充电阶段的顺利进行。In the pre-charging stage, the third pull-down control transistor T7, the fourth pull-down control transistor T8, and the sixth pull-down control transistor T12 are all turned on. Since the resistance of the third pull-down control transistor T7 is greater than the resistance of the fourth pull-down control transistor T8, therefore, the first The gate potential of the fifth pull-down control transistor T11 is close to the second low level VGL2, therefore, the fifth pull-down control transistor T11 is roughly turned off, so the drain potential of the sixth pull-down control transistor T12 (that is, the first pull-down unit of the pull-down unit The two terminals b) are at the second low level VGL2, so it can ensure that the first output pull-down transistor T2 is completely closed in the pre-charging phase, so as to ensure the smooth progress of the pre-charging phase.

在求值阶段,第三下拉控制晶体管T7、第四下拉控制晶体管T8、第五下拉控制晶体管T11和第六下拉控制晶体管T12均关闭。During the evaluation phase, the third pull-down control transistor T7 , the fourth pull-down control transistor T8 , the fifth pull-down control transistor T11 and the sixth pull-down control transistor T12 are all turned off.

在复位阶段,第三下拉控制晶体管T7和第五下拉控制晶体管T11开启,第四下拉控制晶体管T8和第六下拉控制晶体管T12关闭,所述下拉单元的第二端b处的电位为高电平,可以使复位晶体管T4开启,对上拉节点进行放电。In the reset phase, the third pull-down control transistor T7 and the fifth pull-down control transistor T11 are turned on, the fourth pull-down control transistor T8 and the sixth pull-down control transistor T12 are turned off, and the potential at the second terminal b of the pull-down unit is at a high level , the reset transistor T4 can be turned on to discharge the pull-up node.

在非工作阶段,第三下拉控制晶体管T7和第五下拉控制晶体管T11处于开启和关闭的交替状态,即下拉节点PD可以处在交变电压状态。In the non-working stage, the third pull-down control transistor T7 and the fifth pull-down control transistor T11 are alternately on and off, that is, the pull-down node PD can be in an alternating voltage state.

为了使移位寄存单元的结构更加简单,如图9中所示的第三种实施方式,第一下拉模块13a可以包括第七下拉控制晶体管T13和下拉电容C2,该下拉电容C2的一端与第二时钟信号输入端CLKB相连,下拉电容C2的另一端与所述下拉单元的第二端b相连,第七下拉控制晶体管T13的栅极与第二驱动信号输入端14相连,第七下拉控制晶体管T13的源极与所述第二低电平输入端相连,第七下拉控制晶体管T13的漏极与所述下拉单元的第二端b相连,所述下拉单元的第二端b与所述下拉单元的第三端c相连。In order to make the structure of the shift register unit simpler, in the third implementation manner shown in FIG. The second clock signal input end CLKB is connected, the other end of the pull-down capacitor C2 is connected to the second end b of the pull-down unit, the gate of the seventh pull-down control transistor T13 is connected to the second drive signal input end 14, and the seventh pull-down control transistor T13 is connected to the second drive signal input end 14. The source of the transistor T13 is connected to the second low-level input terminal, the drain of the seventh pull-down control transistor T13 is connected to the second terminal b of the pull-down unit, and the second terminal b of the pull-down unit is connected to the second terminal b of the pull-down unit. The third terminal c of the pull-down unit is connected.

在预充电阶段,下拉电容C2进行充电,第七下拉控制晶体管T13导通,由于下拉电容C2的电阻大于第七下拉控制晶体管T13的电阻,因此所述下拉单元的第二端b处的电位接近第二低电平VGL2。In the pre-charging stage, the pull-down capacitor C2 is charged, and the seventh pull-down control transistor T13 is turned on. Since the resistance of the pull-down capacitor C2 is greater than the resistance of the seventh pull-down control transistor T13, the potential at the second terminal b of the pull-down unit is close to The second low level VGL2.

在求值阶段,第七下拉控制晶体管T13关闭,下拉电容C2停止充电。In the evaluation phase, the seventh pull-down control transistor T13 is turned off, and the pull-down capacitor C2 stops charging.

在复位阶段,第七下拉控制晶体管T13关闭,下拉电容C2充电和,使下拉单元的第二端b处的电位为高电平VGH,使复位晶体管T4开启,对上拉节点PU进行放电。In the reset phase, the seventh pull-down control transistor T13 is turned off, the pull-down capacitor C2 is charged and the potential at the second terminal b of the pull-down unit is high level VGH, the reset transistor T4 is turned on, and the pull-up node PU is discharged.

在非工作阶段,第七下拉控制晶体管T13关闭,下拉电容C2交替地处于充电和断电的状态,从而对下拉节点PD进行交流下拉。In the non-working stage, the seventh pull-down control transistor T13 is turned off, and the pull-down capacitor C2 is alternately in the state of charging and power-off, thereby performing AC pull-down on the pull-down node PD.

优选地,在本实用新型所提供的移位寄存单元中,第一上拉晶体管T1、第一输出下拉晶体管T2、开关晶体管T3和复位晶体管T4中的至少一者为耗尽型晶体管。进一步优选地,第一上拉晶体管T1、第一输出下拉晶体管T2、开关晶体管T3和复位晶体管T4均可以为耗尽型晶体管。背景技术中已经描述了耗尽型晶体管的优点,这里不再赘述。Preferably, in the shift register unit provided by the present invention, at least one of the first pull-up transistor T1, the first output pull-down transistor T2, the switch transistor T3 and the reset transistor T4 is a depletion transistor. Further preferably, the first pull-up transistor T1, the first output pull-down transistor T2, the switch transistor T3 and the reset transistor T4 may all be depletion transistors. The advantages of depletion-mode transistors have been described in the background art, and will not be repeated here.

在本实用新型所提供的几种实施方式中,第一上拉晶体管T1、第一输出下拉晶体管T2、开关晶体管T3和复位晶体管T4均为N沟道薄膜晶体管。In several implementation manners provided by the present invention, the first pull-up transistor T1 , the first output pull-down transistor T2 , the switch transistor T3 and the reset transistor T4 are all N-channel thin film transistors.

作为本实用新型的另外一个方面,如图11所示,还提供一种移位寄存器,该移位寄存器包括多级移位寄存单元,其中,所述移位寄存单元为本实用新型所提供的上述移位寄存单元,下一级所述移位寄存单元的第一驱动信号输入端10(n)与上一级所述移位寄存单元的第一驱动信号输出端11(n-1)相连。此处,n代表的是自然数。As another aspect of the present invention, as shown in FIG. 11 , a shift register is also provided, which includes a multi-stage shift register unit, wherein the shift register unit is provided by the present invention In the aforementioned shift register unit, the first drive signal input terminal 10(n) of the shift register unit at the next stage is connected to the first drive signal output terminal 11(n-1) of the shift register unit at the previous stage . Here, n represents a natural number.

应当理解的是,10(1)代表的是第一级移位寄存单元的第一驱动信号输入端,11(1)代表的是第一级移位寄存单元的第一驱动信号输出端,10(n-1)代表的是第(n-1)级移位寄存单元的第一驱动信号输入端,11(n-1)代表的是第(n-1)级移位寄存单元的第一驱动信号输出端,10(n)代表的是第n级移位寄存单元的第一驱动信号输入端,11(n)代表的是第n级移位寄存单元的第一驱动信号输出端,Vdd和Vss分别代表的是为移位寄存单器供电的电源的正极和负极。It should be understood that 10(1) represents the first drive signal input end of the first-stage shift register unit, 11(1) represents the first drive signal output end of the first-stage shift register unit, and 10 (n-1) represents the first drive signal input terminal of the (n-1)th stage shift register unit, 11(n-1) represents the first drive signal input terminal of the (n-1) stage shift register unit The drive signal output terminal, 10(n) represents the first drive signal input terminal of the nth shift register unit, 11(n) represents the first drive signal output terminal of the nth stage shift register unit, V dd and V ss respectively represent the positive and negative poles of the power supply for the shift register unit.

当所述移位寄存单元包括第二驱动信号输出模块时,上一级移位寄存单元的第二驱动信号输出端12(n-1)与下一级移位寄存单元的第二驱动信号输入端14(n)连接。When the shift register unit includes a second drive signal output module, the second drive signal output terminal 12 (n-1) of the shift register unit at the upper stage is connected to the second drive signal input terminal 12 (n-1) of the shift register unit at the next stage. Terminal 14(n) is connected.

在图11中,14(1)代表第一级移位寄存单元的第二驱动信号输入端,12(1)代表第一级移位寄存单元的第二驱动信号输出端;14(n-1)代表第(n-1)级移位寄存单元单元的第二驱动信号输入端,12(n-1)代表第(n-1)级移位寄存单元的第二驱动信号输出端;14(n)代表第n级移位寄存单元的第二驱动信号输入端,12(n)代表第n级移位寄存单元的第二驱动信号输出端。In Fig. 11, 14(1) represents the second drive signal input end of the first stage shift register unit, 12(1) represents the second drive signal output end of the first stage shift register unit; 14(n-1 ) represents the second drive signal input end of the (n-1)th stage shift register unit, 12(n-1) represents the second drive signal output end of the (n-1) stage shift register unit; 14( n) represents the second drive signal input end of the shift register unit of the nth stage, and 12(n) represents the second drive signal output end of the shift register unit of the nth stage.

可以将耗尽型晶体管应用于本实用新型所提供的移位寄存单元中。The depletion transistor can be applied to the shift register unit provided by the utility model.

作为本实用新型的还一个方面,提供一种显示装置,该显示装置包括薄膜晶体管、数据线、栅线和与该栅线电连接的移位寄存器,其中,所述移位寄存器为本实用新型所提供的上述移位寄存器,所述移位寄存器的驱动信号输出端与所述栅线连接。As another aspect of the present invention, a display device is provided, which includes a thin film transistor, a data line, a gate line, and a shift register electrically connected to the gate line, wherein the shift register is a In the above-mentioned shift register provided, the driving signal output end of the shift register is connected to the gate line.

与现有技术中一样,所述显示装置可以包括多条栅线和多条数据线,多条数据线和多条栅线交叉形成多个像素单元,每个像素单元中都设置有一个薄膜晶体管,每一级移位寄存单元与一条栅线对应连接,通过向栅线提供高电平VGH而将薄膜晶体管打开。As in the prior art, the display device may include a plurality of gate lines and a plurality of data lines, the plurality of data lines and the plurality of gate lines intersect to form a plurality of pixel units, and each pixel unit is provided with a thin film transistor , each stage of shift register unit is correspondingly connected to a gate line, and the thin film transistor is turned on by providing a high level VGH to the gate line.

在所述显示装置中,栅极驱动器中所用到的第一上拉晶体管T1、第一输出下拉晶体管T2、开关晶体管T3和复位晶体管T4均可以为耗尽型晶体管。背景技术中已经描述了耗尽型晶体管的优点,这里不再赘述。In the display device, the first pull-up transistor T1 , the first output pull-down transistor T2 , the switch transistor T3 and the reset transistor T4 used in the gate driver may all be depletion transistors. The advantages of depletion-mode transistors have been described in the background art, and will not be repeated here.

可以理解的是,以上实施方式仅仅是为了说明本实用新型的原理而采用的示例性实施方式,然而本实用新型并不局限于此。对于本领域内的普通技术人员而言,在不脱离本实用新型的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本实用新型的保护范围。It can be understood that, the above embodiments are only exemplary embodiments adopted to illustrate the principles of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present utility model, and these variations and improvements are also regarded as the protection scope of the present utility model.

Claims (12)

1.一种移位寄存单元,该移位寄存单元包括第一驱动信号输入端、第一驱动信号输出端、第一时钟信号输入端、第一上拉晶体管、第一输出下拉晶体管、开关晶体管、复位晶体管和自举电容,所述开关晶体管的漏极与所述第一驱动信号输入端相连,所述第一输出下拉晶体管的漏极与所述第一驱动信号输出端相连,所述自举电容的一端与所述第一上拉晶体管的栅极相连,另一端与所述第一驱动信号输出端相连,所述第一上拉晶体管的栅极与所述开关晶体管的源极相连,所述第一上拉晶体管的漏极与所述第一时钟信号输入端相连,所述第一上拉晶体管的漏极与所述第一驱动信号输出端相连,所述复位晶体管的漏极与所述开关晶体管的源极相连,其特征在于,所述移位寄存单元还包括下拉单元,该下拉单元的第一端与所述开关晶体管的栅极相连,所述下拉单元的第二端与所述复位晶体管的栅极相连,所述下拉单元的第三端与所述第一输出下拉晶体管的栅极相连,所述复位晶体管的源极与能够输出第二低电平的第二低电平输入端相连,所述第一输出下拉晶体管的源极与能够输出第三低电平的第三低电平输入端相连,在求值阶段,所述下拉单元能够向所述第一输出下拉晶体管的栅极、所述开关晶体管的栅极以及所述复位晶体管的栅极输出第一低电平,所述第一低电平与所述第二低电平的差值小于所述复位晶体管的阈值电压,所述第一低电平与所述第三低电平的差值小于所述第一输出下拉晶体管的阈值电压。  1. A shift register unit comprising a first drive signal input terminal, a first drive signal output terminal, a first clock signal input terminal, a first pull-up transistor, a first output pull-down transistor, and a switch transistor , a reset transistor and a bootstrap capacitor, the drain of the switching transistor is connected to the first drive signal input terminal, the drain of the first output pull-down transistor is connected to the first drive signal output terminal, and the self One end of the lifting capacitor is connected to the gate of the first pull-up transistor, the other end is connected to the first drive signal output end, the gate of the first pull-up transistor is connected to the source of the switching transistor, The drain of the first pull-up transistor is connected to the first clock signal input end, the drain of the first pull-up transistor is connected to the first drive signal output end, and the drain of the reset transistor is connected to the first clock signal input end. The source of the switch transistor is connected, and it is characterized in that the shift register unit also includes a pull-down unit, the first end of the pull-down unit is connected to the gate of the switch transistor, and the second end of the pull-down unit is connected to the gate of the switch transistor. The gate of the reset transistor is connected, the third end of the pull-down unit is connected to the gate of the first output pull-down transistor, and the source of the reset transistor is connected to a second low voltage capable of outputting a second low level. connected to the flat input terminal, the source of the first output pull-down transistor is connected to the third low-level input terminal capable of outputting the third low level, and in the evaluation stage, the pull-down unit can pull down the first output The gate of the transistor, the gate of the switching transistor, and the gate of the reset transistor output a first low level, and the difference between the first low level and the second low level is smaller than that of the reset transistor threshold voltage, the difference between the first low level and the third low level is smaller than the threshold voltage of the first output pull-down transistor. the 2.根据权利要求1所述的移位寄存单元,其特征在于,该移位寄存单元包括第一下拉模块和第二下拉模块,所述第一下拉模块用于在预充电阶段向所述第二端和所述第三端输出第二低电平,该第二低电平与所述第三低电平的差值小于所述第一输出下拉晶体管的阈值电压,所述第二下拉模块用于在所述求值阶段向所述第二端和所述第三端输出所述第一低电平。  2. The shift register unit according to claim 1, wherein the shift register unit comprises a first pull-down module and a second pull-down module, and the first pull-down module is used to supply The second terminal and the third terminal output a second low level, the difference between the second low level and the third low level is less than the threshold voltage of the first output pull-down transistor, and the second The pull-down module is used to output the first low level to the second terminal and the third terminal during the evaluation phase. the 3.根据权利要求2所述的移位寄存单元,其特征在于,该移位寄存单元包括第二驱动信号输出端,该第二驱动信号输出端与所述第一驱动信号输出端同步,且能够输出高电平和所述第一低电平,所述第二下拉模块包括第一下拉控制晶体管和第二驱动信号输入端,该第一下拉控制晶体管的栅极与所述第二驱动信号输出端相连,所述第一下拉控制晶体管的源极与所述第一低电平输入端相连,所述第一下拉控制晶体管的漏极与所述第二端和所述第三端连接,所述第二驱动信号输入端与所述第一驱动信号输入端同步,且所述第二驱动信号输入端能够输入高电平和所述第一低电平,所述第二驱动信号输入端与第一端相连。  3. The shift register unit according to claim 2, characterized in that the shift register unit comprises a second drive signal output terminal, the second drive signal output terminal is synchronized with the first drive signal output terminal, and Able to output high level and the first low level, the second pull-down module includes a first pull-down control transistor and a second drive signal input terminal, the gate of the first pull-down control transistor is connected to the second drive The signal output terminal is connected, the source of the first pull-down control transistor is connected to the first low-level input terminal, and the drain of the first pull-down control transistor is connected to the second terminal and the third terminal. terminal connection, the second drive signal input terminal is synchronous with the first drive signal input terminal, and the second drive signal input terminal can input high level and the first low level, the second drive signal input terminal The input end is connected with the first end. the 4.根据权利要求3所述的移位寄存单元,其特征在于,所述第二下拉模块还包括第二下拉控制晶体管,该第二下拉控制晶体管的栅极与所述第二驱动信号输出端相连,所述第二下拉控制晶体管的源极与所述第一低电平输入端相连,所述第二下拉控制晶体管的漏极与所述第一端相连。  4. The shift register unit according to claim 3, wherein the second pull-down module further comprises a second pull-down control transistor, the gate of the second pull-down control transistor is connected to the second drive signal output terminal The source of the second pull-down control transistor is connected to the first low-level input terminal, and the drain of the second pull-down control transistor is connected to the first terminal. the 5.根据权利要求3或4所述的移位寄存单元,其特征在于,该移位寄存单元还包括第二驱动信号输出模块,该第二驱动信号输出模块包括第二上拉晶体管和第二输出下拉晶体管,所述第二上拉晶体管的栅极与所述第一上拉晶体管的栅极相连,所述第二上拉晶体管的漏极与所述第一时钟信号输入端相连,所述第二上拉晶体管的源极与所述第二驱动信号输出端相连,所述第二输出下拉晶体管的栅极与所述第一输出下拉晶体管的栅极相连,所述第二输出下拉晶体管的源极与所述第一低电平输入端相连,所述第二输出下拉晶体管的漏极与所述第二驱动信号输出端相连。  5. The shift register unit according to claim 3 or 4, characterized in that, the shift register unit further comprises a second drive signal output module, and the second drive signal output module comprises a second pull-up transistor and a second An output pull-down transistor, the gate of the second pull-up transistor is connected to the gate of the first pull-up transistor, the drain of the second pull-up transistor is connected to the first clock signal input terminal, the The source of the second pull-up transistor is connected to the second drive signal output terminal, the gate of the second output pull-down transistor is connected to the gate of the first output pull-down transistor, and the gate of the second output pull-down transistor is The source is connected to the first low-level input terminal, and the drain of the second output pull-down transistor is connected to the second drive signal output terminal. the 6.根据权利要求3或4所述的移位寄存单元,其特征在于,所述移位寄存单元还包括第二时钟信号输入端,该第二时钟信号输入端与所述第一时钟信号输入端相反,所述第一下拉模块包括第三下拉控 制晶体管和第四下拉控制晶体管,所述第四下拉控制晶体管的电阻小于第三下拉晶体管的电阻,所述第三下拉控制晶体管的栅极和漏极与所述第二时钟信号输入端相连,所述第三下拉控制晶体管的源极与所述第二端相连,所述第四下拉控制晶体管的栅极与所述第二驱动信号输入端相连,所述第四下拉控制晶体管的源极与所述第二低电平输入端相连,所述第四下拉控制晶体管的漏极与所述第二端相连,所述第二端与所述第三端相连。  6. The shift register unit according to claim 3 or 4, characterized in that, the shift register unit further comprises a second clock signal input terminal, which is connected to the first clock signal input terminal On the contrary, the first pull-down module includes a third pull-down control transistor and a fourth pull-down control transistor, the resistance of the fourth pull-down control transistor is smaller than the resistance of the third pull-down transistor, and the gate of the third pull-down control transistor The pole and the drain are connected to the second clock signal input terminal, the source of the third pull-down control transistor is connected to the second terminal, the gate of the fourth pull-down control transistor is connected to the second drive signal The input terminal is connected, the source of the fourth pull-down control transistor is connected to the second low-level input terminal, the drain of the fourth pull-down control transistor is connected to the second terminal, and the second terminal is connected to the second low-level input terminal. The third ends are connected. the 7.根据权利要求3或4所述的移位寄存单元,其特征在于,所述移位寄存单元还包括第二时钟信号输入端,该第二时钟信号输入端与所述第一时钟信号输入端相反,所述第一下拉模块包括第三下拉控制晶体管、第四下拉控制晶体管、第五下拉控制晶体管和第六下拉控制晶体管,所述第四下拉控制晶体管的电阻小于第三下拉晶体管的电阻,所述第六下拉控制晶体管的电阻小于所述第五下拉控制晶体管的电阻,所述第三下拉控制晶体管的栅极和漏极与所述第二时钟信号输入端相连,所述第三下拉控制晶体管的源极与所述第四下拉控制晶体管的漏极相连,所述第四下拉控制晶体管的栅极与所述第二驱动信号输入端相连,所述第四下拉控制晶体管的源极与所述第二低电平输入端相连,所述第四下拉控制晶体管的漏极与所述第三下拉控制晶体管的源极相连,所述第五下拉控制晶体管的栅极和漏极与所述第二时钟信号输入端相连,所述第五下拉控制晶体管的源极与所述第二端相连,所述第六下拉控制晶体管的栅极与所述第二时钟信号输入端相连,所述第六下拉控制晶体管的源极与所述第二低电平输入端相连,所述第六下拉控制晶体管的漏极与所述第二端相连,所述第二端与所述第三端相连。  7. The shift register unit according to claim 3 or 4, characterized in that, the shift register unit further comprises a second clock signal input terminal, which is connected to the first clock signal input terminal On the contrary, the first pull-down module includes a third pull-down control transistor, a fourth pull-down control transistor, a fifth pull-down control transistor and a sixth pull-down control transistor, and the resistance of the fourth pull-down control transistor is smaller than that of the third pull-down transistor. resistance, the resistance of the sixth pull-down control transistor is smaller than the resistance of the fifth pull-down control transistor, the gate and drain of the third pull-down control transistor are connected to the second clock signal input end, and the third pull-down control transistor The source of the pull-down control transistor is connected to the drain of the fourth pull-down control transistor, the gate of the fourth pull-down control transistor is connected to the second drive signal input terminal, and the source of the fourth pull-down control transistor connected to the second low-level input terminal, the drain of the fourth pull-down control transistor is connected to the source of the third pull-down control transistor, and the gate and drain of the fifth pull-down control transistor are connected to the source of the third pull-down control transistor. The second clock signal input end is connected, the source of the fifth pull-down control transistor is connected to the second end, the gate of the sixth pull-down control transistor is connected to the second clock signal input end, the The source of the sixth pull-down control transistor is connected to the second low-level input terminal, the drain of the sixth pull-down control transistor is connected to the second terminal, and the second terminal is connected to the third terminal . the 8.根据权利要求3或4所述的移位寄存单元,其特征在于,所述移位寄存单元还包括第二时钟信号输入端,该第二时钟信号输入端与所述第一时钟信号输入端相反,所述第一下拉模块包括第七下拉控制晶体管和下拉电容,该下拉电容的电阻大于所述第七下拉控制晶体 管的电阻,所述下拉电容的一端与所述第二时钟信号输入端相连,所述下拉电容的另一端与所述第二端相连,所述第七下拉控制晶体管的栅极与所述第二驱动信号输入端相连,所述第七下拉控制晶体管的源极与所述第二低电平输入端相连,所述第七下拉控制晶体管的漏极与所述第二端相连,所述第二端与所述第三端相连。  8. The shift register unit according to claim 3 or 4, characterized in that, the shift register unit further comprises a second clock signal input terminal, which is connected to the first clock signal input terminal On the contrary, the first pull-down module includes a seventh pull-down control transistor and a pull-down capacitor, the resistance of the pull-down capacitor is greater than the resistance of the seventh pull-down control transistor, and one end of the pull-down capacitor is connected to the second clock signal The input end is connected, the other end of the pull-down capacitor is connected to the second end, the gate of the seventh pull-down control transistor is connected to the second drive signal input end, and the source of the seventh pull-down control transistor It is connected with the second low level input terminal, the drain of the seventh pull-down control transistor is connected with the second terminal, and the second terminal is connected with the third terminal. the 9.根据权利要求1所述的移位寄存单元,其特征在于,所述第一上拉晶体管、第一输出下拉晶体管、开关晶体管、复位晶体管中的至少一个为耗尽型晶体管。  9. The shift register unit according to claim 1, wherein at least one of the first pull-up transistor, the first output pull-down transistor, the switch transistor and the reset transistor is a depletion transistor. the 10.根据权利要求9所述的移位寄存单元,其特征在于,所述第一上拉晶体管、第一输出下拉晶体管、开关晶体管、复位晶体管均为N沟道薄膜晶体管。  10. The shift register unit according to claim 9, wherein the first pull-up transistor, the first output pull-down transistor, the switch transistor and the reset transistor are all N-channel thin film transistors. the 11.一种移位寄存器,该移位寄存器包括多级移位寄存单元,其特征在于,所述移位寄存单元为权利要求1至10中任意一项所述的移位寄存单元,下一级所述移位寄存单元的第一驱动信号输入端与上一级所述移位寄存单元的第一驱动信号输出端相连。  11. A shift register, the shift register comprising a multi-stage shift register unit, characterized in that, the shift register unit is the shift register unit described in any one of claims 1 to 10, the next The first drive signal input end of the shift register unit of the stage is connected to the first drive signal output end of the shift register unit of the previous stage. the 12.一种显示装置,该显示装置包括薄膜晶体管、数据线、栅线和与该栅线电连接的移位寄存器,其特征在于,所述移位寄存器为权利要求11所述的移位寄存器,所述移位寄存器的第一驱动信号输出端与所述栅线连接。  12. A display device comprising a thin film transistor, a data line, a gate line and a shift register electrically connected to the gate line, wherein the shift register is the shift register according to claim 11 , the first drive signal output end of the shift register is connected to the gate line. the
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CN103440839A (en) * 2013-08-09 2013-12-11 京东方科技集团股份有限公司 Shift registering unit, shift register and display device
CN104810003A (en) * 2015-05-21 2015-07-29 合肥京东方光电科技有限公司 Shifting register, driving method of shifting register, grid driving circuit and display device
WO2016141652A1 (en) * 2015-03-09 2016-09-15 京东方科技集团股份有限公司 Shift register unit, shift register, display panel and display device
CN108010494A (en) * 2016-10-31 2018-05-08 乐金显示有限公司 Gate drivers and the display device using the gate drivers

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103440839A (en) * 2013-08-09 2013-12-11 京东方科技集团股份有限公司 Shift registering unit, shift register and display device
WO2015018149A1 (en) * 2013-08-09 2015-02-12 京东方科技集团股份有限公司 Shift register unit, shift register, gate driver and display panel
CN103440839B (en) * 2013-08-09 2016-03-23 京东方科技集团股份有限公司 Shifting deposit unit, shift register and display device
US9396813B2 (en) 2013-08-09 2016-07-19 Boe Technology Group Co., Ltd. Shift register cell, shift register, gate driver and display panel
WO2016141652A1 (en) * 2015-03-09 2016-09-15 京东方科技集团股份有限公司 Shift register unit, shift register, display panel and display device
US10403228B2 (en) 2015-03-09 2019-09-03 Boe Technology Group Co., Ltd. Shift register unit, shift register, display panel and display device
CN104810003A (en) * 2015-05-21 2015-07-29 合肥京东方光电科技有限公司 Shifting register, driving method of shifting register, grid driving circuit and display device
US10121437B2 (en) 2015-05-21 2018-11-06 Boe Technology Group Co., Ltd. Shift register and method for driving the same, gate driving circuit and display device
CN108010494A (en) * 2016-10-31 2018-05-08 乐金显示有限公司 Gate drivers and the display device using the gate drivers

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