CN203289399U - CMOS delaying over-temperature protection circuit - Google Patents

Abstract

The utility model discloses a CMOS delaying over-temperature protection circuit comprising a core over-temperature control circuit 1 constituted by a PNP transistor Q0, a resistor R2, a resistor R3, a resistor R4, and a PMOS switch tube M11. The PMOS switch tube M11 grid voltage can be used to output the voltage Vout to a protection circuit, and the PMOS switch tube M11 is parallely connected with the resistor R4, in addition, one end of the above mentioned parallel connection is connected with the power supply voltage, and the other end of the parallel connection is connected with one end of the resistor R3. The other end of the resistor R3 is connected with a base electrode of a PNP transistor, and an emitter electrode of the PNP transistor Q0 is connected with the power supply voltage. A collector electrode of the PNP transistor Q0 is connected with one end of the resistor R2, and the other end of the resistor R2 is connected with a ground voltage.

Description

CMOS hysteresis over temperature protection circuit

technical field

The utility model relates to an realized over-temperature protection circuit with hysteresis characteristics, which is suitable for hysteresis over-temperature protection integrated in power management chips and other circuits with large local power consumption and high junction temperature that greatly affects chip performance. the

Background technique

With the wide application of integrated circuit technology and the continuous increase of integration, the power consumption of integrated circuit chips continues to increase, causing the local temperature of the chip to rise too fast, affecting the performance of the chip circuit, and even causing permanent damage to the chip. the

In order to protect the chip from high temperature damage, on the one hand, low power supply voltage and low power consumption circuit design technology can be used, on the other hand, a temperature sensor is installed inside the chip for over-temperature protection. When the chip temperature exceeds a certain value, the work of the main power consumption devices of the chip circuit is turned off, so as to cool down the chip and avoid burning the chip. the

The traditional overheat protection circuit is realized in two parts. The first part is to use the temperature sensor to detect the internal temperature of the chip and convert the temperature signal into an electrical signal. The second part is to compare the detected electrical signal with the reference signal through a comparator. , if it exceeds the reference value, it will output the opposite voltage signal, so that the subsequent circuit will stop working normally. The function of the hysteresis circuit in the overheat protection circuit is to change the flipping threshold voltage of the comparator, thereby preventing the power device from being turned on and off frequently at the flipping point, and improving the reliability of the work. The hysteresis characteristic of the temperature work is generally through the Schmitt trigger accomplish. the

Contents of the invention

In order to overcome the shortcomings of the existing over-temperature protection circuit with complex structure and large number of components, the utility model provides an available CMOS technology with simple circuit structure, no need for comparators and Schmitt triggers, and a small number of components. Integrated hysteretic over-temperature protection circuit. the

The technical scheme that the utility model solves its technical problem adopts is:

A CMOS hysteresis over-temperature protection circuit, comprising a core over-temperature control circuit 1 composed of a PNP transistor Q0, a resistor R2, a resistor R3, a resistor R4, and a PMOS switch tube M11, the gate voltage of the PMOS switch tube M11 being the output voltage Vout of the protection circuit, The PMOS switch tube M11 is connected in parallel with the resistor R4, one end of the parallel connection is connected to the power supply voltage, the other end of the parallel connection is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the base of the PNP transistor, and the PNP transistor Q0 The emitter of the PNP transistor Q0 is connected to the power supply voltage, the collector of the PNP transistor Q0 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the ground voltage. the

As a preferred solution: the hysteresis over-temperature protection circuit also includes cascode constant current generation cascode constant current generation branch 2, composed of resistor R1, NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, NMOS transistor M4, NMOS transistor M5 and NMOS transistor M6 are composed. One end of the resistor R1 is connected to the power supply, the other end of the resistor R1 is connected to the drain end of the NMOS transistor M1, the drain end and the gate end of the NMOS transistor M1 are connected in parallel, and are connected to the NMOS transistor M2 and the NMOS transistor M1 The gate terminal of the transistor M5 is connected, the source terminal of the NMOS transistor M1 is connected to the drain terminal of the NMOS transistor M3, the drain terminal and the gate terminal of the NMOS transistor M3 are connected in parallel, and are connected with the NMOS transistor M4 and the NMOS transistor M4. The gate terminal of the transistor M6 is connected, the drain terminal of the NMOS transistor M2 is connected to the power supply, the source terminal of the NMOS transistor M2 is connected to the drain terminal of the NMOS transistor M4, and the source terminal of the NMOS transistor M5 is connected to the NMOS transistor M5 The drain terminals of the transistor M6 are connected, the source terminals of the NMOS transistors M3, M4, and M6 are respectively grounded, and the drain terminals of the NMOS transistor M5 are used as the output terminal of the cascode constant current generation branch 2 and the PNP transistor Q0 connected to the base. the

As another preferred solution: the hysteresis over-temperature protection circuit also includes an output signal level control branch 3, which is composed of a PMOS transistor M7, a PMOS transistor M9, an NMOS transistor M8 and an NMOS transistor M10, and the PMOS transistor M7 , the gate of the NMOS transistor M8 is connected to the collector of the PNP transistor, the drain of the PMOS transistor M7 is connected to the drain of the PMOS switch M11, the drain of the PMOS transistor M7 is connected to the NMOS The drain terminal of the transistor M8 is connected and connected in parallel with the gate terminals of the PMOS transistor M9 and the NMOS transistor M10, the source terminal of the NMOS transistor M8 is grounded, the source terminal of the PMOS transistor M9 is connected to a power supply, and the The drain terminal of the PMOS transistor M9 is connected to the drain terminal of the NMOS transistor M10 and connected to the gate terminal of the PMOS switch M11 to form a Vout output terminal, and the source terminal of the NMOS transistor is grounded. the

The technical concept of the utility model is: apply the temperature characteristics of the transistor BE junction threshold voltage and the switching characteristics of the MOS tube to the over-temperature protection circuit, making them a new hysteresis over-temperature protection circuit (as shown in Figure 1). The hysteresis over-temperature control circuit is mainly composed of a bipolar transistor Q0, resistors R2, R3, R4 and a PMOS switch MOS transistor M11, which functions as a hysteresis over-temperature protection by controlling the closing and opening of the PMOS switch M11. Its characteristics are as follows: Q0 is a temperature-sensitive device in the main circuit of over-temperature protection. Its base and collector are connected to one end of resistors R2 and R3 respectively, and the BE junction bias circuit of transistor Q0 is composed of resistors R3 and R4. According to Chip temperature changes, the threshold voltage of the BE junction changes, and the transistor Q0 is turned on and off according to the BE junction bias voltage and threshold voltage, thereby changing the high and low level control of the output voltage VR2 on the resistor R2. It should be noted that the transistor Q0 suitable for the bipolar over-temperature protection circuit is a PNP transistor. the

In order to obtain the hysteresis characteristics of the over-temperature protection circuit, a voltage feedback branch is added between the output terminal of the circuit and the over-temperature protection circuit. The high and low levels of the output terminal voltage control the on and off of the PMOS transistor M11, changing the BE junction of Q0 The size of the bias voltage provides two different threshold voltages, thereby realizing the hysteresis characteristic of the over-temperature protection circuit. In order to obtain the ideal output high and low levels, a two-stage inverting buffer circuit is added between the output of the resistor R2 and the circuit output, consisting of MOS transistors M7, M8, M9, and M10 (as shown in Figure 1). In order to obtain a stable bias current I0, the cascode cascade structure is used to improve the output circuit to increase the stability of the current, which is composed of MOS transistors M1, M2, M3, M4, M5, M6 and resistor R1 (as shown in Figure 1). the

The beneficial effects of the utility model are mainly manifested in: the CMOS over-temperature protection circuit proposed by the utility model has a hysteresis over-temperature protection function, the circuit structure is simple, the number of components is small, and functional circuits such as comparators and Schmitt triggers are not required , when the chip temperature exceeds T ₂ , the circuit outputs a high-level turn-off signal, and when the chip temperature drops to T ₁ , the circuit outputs a low-level turn-on signal, with a hysteresis range of T ₂ -T ₁ , and the chip turn-off and turn-on temperatures are determined according to the circuit Design parameters are adjustable. It is very suitable for integration in power management, LED driver and other chips.

Description of drawings

Figure 1 is a schematic diagram of the CMOS hysteresis over-temperature protection circuit

Figure 2 is the simulation curve of the CMOS hysteresis over-temperature protection circuit

Detailed ways

Below in conjunction with accompanying drawing, the utility model is further described. the

Example

Referring to Fig. 1, a bipolar transistor type hysteresis over-temperature protection circuit includes a core over-temperature control circuit 1 composed of a PNP transistor Q0, a resistor R2, a resistor R3, a resistor R4 and a PMOS switch tube M11, and the gate voltage of the PMOS switch tube M11 is In order to protect the output voltage Vout of the circuit, the PMOS switch tube M11 is connected in parallel with the resistor R4, one end of the parallel connection is connected to the power supply voltage, the other end of the parallel connection is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the base of the PNP transistor The emitter of the PNP transistor is connected to the power supply voltage, the collector of the PNP transistor is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the ground voltage. The hysteresis over-temperature protection circuit also includes cascode constant current generation cascode constant current generation branch 2, as shown in Figure 1, composed of resistor R1, NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, NMOS Transistor M4, NMOS transistor M5 and NMOS transistor M6 are composed. One end of the resistor R1 is connected to the power supply, the other end of the resistor R1 is connected to the drain end of the NMOS transistor M1, the drain end and the gate end of the NMOS transistor M1 are connected in parallel, and are connected to the NMOS transistor M2 and the NMOS transistor M1 The gate terminal of the transistor M5 is connected, the source terminal of the NMOS transistor M1 is connected to the drain terminal of the NMOS transistor M3, the drain terminal and the gate terminal of the NMOS transistor M3 are connected in parallel, and are connected with the NMOS transistor M4 and the NMOS transistor M4. The gate terminal of the transistor M6 is connected, the drain terminal of the NMOS transistor M2 is connected to the power supply, the source terminal of the NMOS transistor M2 is connected to the drain terminal of the NMOS transistor M4, and the source terminal of the NMOS transistor M5 is connected to the NMOS transistor M5 The drain ends of the transistor M6 are connected, the source ends of the NMOS transistors M3, M4, and M6 are respectively grounded, and the drain ends of the NMOS transistor M5 are used as the output end of the cascode constant current generation branch 2 and the output end of the PNP transistor connected to the base. the

The hysteresis over-temperature protection circuit also includes an output signal level control branch 3, which is composed of a PMOS transistor M7, a PMOS transistor M9, an NMOS transistor M8 and an NMOS transistor M10, and the gate terminals of the PMOS transistor M7 and the NMOS transistor M8 are connected to each other. , and connected to the collector of the PNP transistor, the drain of the PMOS transistor M7 is connected to the drain of the PMOS switch M11, the drain of the PMOS transistor M7 is connected to the drain of the NMOS transistor M8, and The gate terminals of the PMOS transistor M9 and the NMOS transistor M10 are connected in parallel, the source terminal of the NMOS transistor M8 is grounded, the source terminal of the PMOS transistor M9 is connected to a power supply, and the drain terminal of the PMOS transistor M9 is connected to the The drain terminal of the NMOS transistor M10 is connected to the gate terminal of the PMOS switch M11 to form a Vout output terminal, and the source terminal of the NMOS transistor is grounded. the

FIG. 2 is a typical working waveform diagram of the CMOS hysteresis over-temperature protection circuit in Embodiment 1. The working principle of the circuit is as follows:

(1) Temperature rise stage: when the circuit is powered on, the chip operating temperature is at room temperature, the PNP transistor Q0 is cut off, the output voltage VR2 of the resistor R2 is low, and the output voltage Vout is low. At this time, the core power consumption circuit of the chip It does not play a control role; the PMOS transistor M11 is turned on, and the resistor R4 is short-circuited, and the BE junction voltage of the transistor Q0 drops to I0×R3. When the chip temperature is low, the voltage drop is not enough to make the transistor Q0 turn on. As the temperature of the chip rises, the turn-on voltage drop of the transistor Q0BE junction decreases linearly. In this embodiment, the turn-on voltage drop of the BE junction at T2=150°C is 0.55V, and the circuit design parameters make I0×R3=0.55V, Then the transistor is turned on at T2=150°C, generating emitter current, the voltage drop VR2 on the resistor R2 becomes high level, the output voltage Vout jumps from low level to high level, and the core power consumption circuit of the chip is turned off . At the same time, the PMOS transistor M11 is turned off, and the voltage drop on the transistor Q0BE junction becomes I0×(R3+R4). the

(2) Temperature drop stage: After the core power consumption circuit on the chip is turned off, the chip temperature drops slowly, and the conduction voltage drop of the transistor Q0BE junction rises. When the chip temperature drops to T ₁ , the conduction voltage drop of the transistor Q0BE junction When rising to I0×(R3+R4), the transistor Q0 is turned off, the voltage drop VR2 on the resistor R2 changes from high level to low level, the output voltage Vout changes from high level to low level, and the PMOS transistor M11 is turned on , The voltage drop across the transistor Q0BE junction is I0×R3. In this embodiment, the conduction voltage drop of the BE junction at T ₂ =130°C is 0.58V, and the circuit parameters are designed so that I0×(R3+R4)=0.58V.

(3) As the operating temperature of the chip changes within the range of T ₂ and T ₁ , the designed over-temperature protection circuit outputs high level or low level, and there is a hysteresis range of T ₂ -T ₁ , the chip temperature protection interval can pass The parameter values of current I0, resistors R3 and R4 in the circuit design are adjusted.

Claims (3)

1.CMOS sluggish thermal-shutdown circuit, it is characterized in that: comprise by PNP transistor Q0, resistance R 2, resistance R 3, the core that resistance R 4 and PMOS switching tube M11 form is crossed temperature control circuit (1), PMOS switching tube M11 gate voltage is protective circuit output voltage V out, described PMOS switching tube M11 is in parallel with resistance R 4, a termination power voltage in parallel, the other end in parallel is connected with described resistance R 3 one ends, the other end of described resistance R 3 is connected with the transistorized base stage of PNP, the emitter of described PNP transistor Q0 is connected with supply voltage, the collector electrode of described PNP transistor Q0 is connected with an end of described resistance R 2, the other end of described resistance R 2 is connected with ground voltage.

2. the sluggish thermal-shutdown circuit of CMOS as claimed in claim 1, it is characterized in that: described sluggish thermal-shutdown circuit also comprises that the cascade constant current produces branch road (2), by resistance R 1, nmos pass transistor M1, nmos pass transistor M2, nmos pass transistor M3, nmos pass transistor M4, nmos pass transistor M5 and nmos pass transistor M6 form, one end of described resistance R 1 is connected with power supply, the other end of described resistance R 1 is connected with the drain terminal of nmos pass transistor M1, the drain terminal of described nmos pass transistor M1, the grid end is in parallel, and with the grid end of described nmos pass transistor M2 and described nmos pass transistor M5, be connected, the source of described nmos pass transistor M1 is connected with the drain terminal of described nmos pass transistor M3, the drain terminal of described nmos pass transistor M3, the grid end is in parallel, and with the grid end of described nmos pass transistor M4 and described nmos pass transistor M6, be connected, the drain terminal of described nmos pass transistor M2 is connected with power supply, the source of described nmos pass transistor M2 is connected with the drain terminal of described nmos pass transistor M4, the source of described nmos pass transistor M5 is connected with the drain terminal of described nmos pass transistor M6, described nmos pass transistor M3, M4, the source of M6 is ground connection respectively, the drain terminal of described nmos pass transistor M5 is connected with the base stage of described PNP transistor Q0 as the output that the cascade constant current produces branch road (2).

3. the sluggish thermal-shutdown circuit of CMOS as claimed in claim 2, it is characterized in that: described sluggish thermal-shutdown circuit also comprises an output signal level control branch road (3), by PMOS transistor M7, PMOS transistor M9, nmos pass transistor M8 and nmos pass transistor M10 form, described PMOS transistor M7, the grid end of nmos pass transistor M8 is connected, and with the transistorized collector electrode of PNP, be connected, the drain terminal of described PMOS transistor M7 is connected with the drain terminal of described PMOS switching tube M11, the drain terminal of described PMOS transistor M7 is connected with the drain terminal of described nmos pass transistor M8, and with the grid end of described PMOS transistor M9 and described nmos pass transistor M10 and connect, the source ground connection of described nmos pass transistor M8, the source of described PMOS transistor M9 is connected with power supply, the drain terminal of described PMOS transistor M9 is connected with the drain terminal of described nmos pass transistor M10, and with the grid end of described PMOS switching tube M11, be connected, form the Vout output, the source ground connection of described nmos pass transistor.

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