CN203275920U

CN203275920U - Linear CCD data acquisition circuit with wireless data transmission function

Info

Publication number: CN203275920U
Application number: CN 201320059853
Authority: CN
Inventors: 杨祥龙; 鲁琛
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2013-01-30
Filing date: 2013-01-30
Publication date: 2013-11-06
Anticipated expiration: 2023-01-30

Abstract

The utility model discloses a linear array CCD data acquisition circuit with wireless data transmission function. The circuit is composed of timing signal output and analog signal amplification circuit, USB interface circuit, analog-to-digital conversion circuit and wireless circuit. The timing circuit generates various timing signals; the USB interface circuit stores the parallel output signals, and in the USB mode, communicates with the host computer via USB; in the wireless mode, communicates with the CC2430 wireless single-chip microcomputer to control its output clock frequency To change the output frequency of TCD1252AP or send the stored sampling data to CC2430; the analog-to-digital conversion circuit inverts and amplifies the output analog signal; the wireless circuit changes the clock signal output by itself through serial port communication. The utility model supports the USB2.0 protocol and the upper computer for data transmission, overcomes the bottleneck of the interface circuit conforming to the serial protocol standard; supports the wireless working mode, and can send the data collected by the linear array CCD in time, so that it is not affected by the line array CCD. Array CCD data acquisition circuit system is limited in the size of the storage space.

Description

Linear Array CCD Data Acquisition circuit with wireless data transmission function

Technical field

The utility model belongs to radio sensing network, analog-digital hybrid circuit design and embedded system circuit design field.

Background technology

The Linear Array CCD Data Acquisition circuit is the requisite electronic section of spectrometer, and therefore designing linear array ccd data Acquisition Circuit has very high practical value.

At present common Linear Array CCD Data Acquisition circuit has following deficiency: 1, the employing of the interface circuit of most Linear Array CCD Data Acquisition circuit and host computer meet RS ?the serial protocol chip of 232 standards, and the maximum baud rate that meets this standard of common singlechip chip support is only 115200 bps, transfer rate is lower, form difference with the high handling property of host computer, become the bottleneck of data transmission; 2, adopt the chip such as Flash as temporary storage spare in most Linear Array CCD Data Acquisition circuit, can be subjected to like this restriction of storage size.

Summary of the invention

The utility model provides a kind of Linear Array CCD Data Acquisition circuit, and this circuit is subjected to the deficiency of storage space limitations during the too low and independent image data of speed when also having overcome to the host computer the transmission of data except possessing the Linear Array CCD Data Acquisition function.

Realize that technical scheme of the present invention is:

The Linear Array CCD Data Acquisition circuit is comprised of clock signal output circuit and amplifying circuit of analog signal, usb circuit, analog to digital conversion circuit, radio-circuit.

The acp chip of sequential circuit be model be EPL7064SLC44 ?10 CPLD (CPLD), by the output clock of wireless singlechip CC2430 is counted produce drive required clock signal, the model of line array CCD device TCD1252AP be the USB chip operation of CY7C68013A ?128AC under SlaveFIFO (from genotype first in first out memory block, FIFO refers to the first in first out memory block) pattern clock signal and the sampled clock signal of modulus conversion chip AD9220.

The acp chip of usb circuit be model be CY7C68013A ?the USB chip of 128AC, be used for the parallel output signal of AD9920 is changed, stored and exports, if this circuit working is under the USB pattern, be packaged as the blocks of data transformat of usb protocol, then carry out usb communication with host computer; If this circuit working under wireless mode, carries out serial communication with the CC2430 wireless singlechip, control it and change the output clock frequency with the output frequency of change TCD1252AP or give CC2430 with the sampling data transmitting of storage.

The acp chip of analog to digital conversion circuit is modulus conversion chip AD8031, and the outputting analog signal of TCD1252AP is carried out anti-phase amplification, makes it to meet 0～5 volt of the convertible scope of AD9220.

The acp chip of radio-circuit is wireless chip CC2430, by serial communication change self export to EPL7064SLC44 ?10 clock signal, under wireless mode, receive CY7C68013A ?the sampled data of 128AC storage, and send by antenna.

The beneficial effects of the utility model:

The utility model designed complete Linear Array CCD Data Acquisition circuit, and chip and the electronic component of having selected each sub-circuits to adopt have provided detailed connected mode, effect and the mode of operation of clear and definite each chip and element.

The utility model supports USB2.0 agreement and host computer to carry out data transmission fully, upwards make the transfer rate of the interface circuit of Linear Array CCD Data Acquisition circuit and host computer satisfy the requirement of the high handling property of host computer fully, the data that the CCD sampling is obtained can in time be packed, thereby have overcome the bottleneck of the interface circuit that meets the serial protocol standard.

The utility model is supported wireless mode of operation fully, can the data that line array CCD collects in time be sent, thereby is not subjected to the restriction of the storage size of Linear Array CCD Data Acquisition Circuits System.

Description of drawings

Fig. 1 is TCD1252AP type line array CCD connecting circuit figure of the present utility model.

Fig. 2 is the connecting circuit figure of AD8031 of the present utility model.

Fig. 3 is jtag interface connecting circuit figure of the present utility model.

Fig. 4 be EPL7064SLC44 of the present utility model ?10 connecting circuit figure.

Fig. 5 be CY7C68013A of the present utility model ?the peripheral circuit diagram of 128AC.

Fig. 6 is the connecting circuit figure of USB interface of the present utility model.

Fig. 7 be CY7C68013A of the present utility model ?the connecting circuit figure of 128AC.

Fig. 8 is the connecting circuit figure of AD9220 of the present utility model.

Fig. 9 is filtering circuit figure of the present utility model.

Figure 10 is the filtering circuit figure of AD9220 of the present utility model.

Figure 11 is generation reference voltage circuit figure of the present utility model.

Figure 12 is LT1117 connecting circuit figure of the present utility model.

Figure 13 is radio-circuit part schematic diagram of the present utility model.

Embodiment

The present invention is described further below in conjunction with the drawings and specific embodiments.

Figure 1 ?Figure 13 be the Linear Array CCD Data Acquisition circuit diagram that has wireless data transmission function in the utility model, shown a kind of embodiment of the present utility model.

Fig. 1, Fig. 2, Fig. 3, Fig. 4 are required various clock signal output circuits and amplifying circuit of analog signal of generation Linear Array CCD Data Acquisition circuit of the present utility model.model be EPL7064SLC44 ?the counting clock pin 43 (seeing Fig. 4) of 10 CPLD chip connect the I/O output pin 11 (seeing Figure 13) of CC2430,

31, 33, 24, 19 produce the required a few road clock signal Fi1 (phase place 1) of driving TCD1252AP type line array CCD (Fig. 1), Fi2 (phase place 2), SH (shift gate), RS (restarting door), pin 5 produces the sampled clock signal of modulus conversion chip AD9220 (seeing Fig. 8), pin one, 44, 18, 37, 36 produce EZ ?the clock signal RESET (restart) of USB chip CY7C68013A (seeing Fig. 7) under the SlaveFIFO pattern, SLWREN (SlaveFIFO write-enable), SLWR (SlaveFIFO writes), FADDR1 (fifo address 1), FADDR0 (fifo address 0), PKTEND (packet end), be used for controlling the read-write of CY7C68013A FIFO,

32, 38, 13, 7 connect respectively the respective pins (seeing Fig. 3) on jtag interface, be used for EPL7064SLC44 ?the download of 10 programs.The output signal of line array CCD device TCD1252 is as the input signal of signal amplification chip AD8031, the output pin 7 of AD8031 and input pin 3 form reverse amplification circuit by resistance R _ f and R7, be used for input signal OS is amplified (seeing Fig. 2), pin two practice midwifery living reference voltage circuit reference voltage pin VIN ?(seeing Figure 11).

Fig. 5, Fig. 6, Fig. 7 are usb circuits of the present utility model.CY7C68013A ?

128AC

44, 45, 46, 47, 54, 55, 56, 57, 103, 104, 405 pins (seeing Fig. 7) connect respectively the BIT12 of modulus conversion chip AD9220 (seeing Fig. 8)～BIT1 pin, be used for reading the digital signal that AD9220 produces, pin one 01, 99 connect respectively and draw resistance R 2, R3, be used for guaranteeing that the level of these two pins can not dragged down and is waken up or restarts, pin 82 connect EPL7064SLC44 ?10 SH signal (seeing Fig. 4) for generation of interruption, pin 51, 52 connect respectively the pin one 3 of CC2430, 14, be used for carrying out with CC2430 the serial communication (seeing Figure 13) that software flow is controlled, pin one 8, 19 connect respectively pin 3 and the pin 2 (seeing Fig. 6) of USBHeder (USB interface), be used for carrying out usb communication with host computer.the pin 1 of USBHeader meets voltage transitions chip LT1117 (seeing Figure 12), be used for this circuit working and provide electric energy for whole circuit in the USB pattern,

36, 37, 101, 73 connect respectively CY7C68013A ?the resistance R 8 of peripheral circuit of 128AC, R9, R2, R1 (seeing Fig. 5), CY7C68013A ?the 128AC chip support USB2.0, maximum transmission rate is 480Mbps (MBPS) in theory, also can reach tens of Mbps during normal operation, therefore can satisfy the highest output frequency that TCD1252 and AD9220 combination can reach fully, do not make the data of generation become the bottleneck of Linear CCD data acquisition system to the transfer rate of host computer.

Fig. 8, Fig. 9, Figure 10, Figure 11, Figure 12 are analog to digital conversion circuits of the present utility model.modulus conversion chip AD9220 (seeing Fig. 8) pin one 8, 24 connect by capacitor C 15, the filtering circuit that C16 is formed in parallel, pin two 0, 21 connect respectively by C12, C13, CAPB end and the CAPT end (seeing Fig. 9) of the filtering circuit that C14 forms, pin one 8, 24 connect by C15, the filtering circuit of the AD9220 that C16 (seeing Figure 10) forms, the filtering circuit of AD9220, ground connection after the external filter capacitor C9 of pin two 2, the operating voltage input pin 15 of access AD9220 mimic channel after the voltage process C8 filtering of 5 volts, through E1, C10, the operating voltage input pin 28 of the digital circuit of access AD9220 after the filtering circuit that C11 forms, 17 of AD9220, 19, 25, the 27 direct ground connection of pin, the input pin of LT1117 (seeing Figure 12) connects the pin 1 of USBHeader (seeing Fig. 6), output pin is used as 3.3 volts of outputs after meeting filter capacitor E3.

Figure 13 is radio-circuit part of the present utility model.RED is the red LED pilot lamp, LED is green indicating lamp, and crystal oscillator Y1, Y2 are used to the CC2430 wireless singlechip that clock is provided, and forms radio transmitter by L100, L101, L102, C112 and PCR (emitting antenna), under the CC2430 peak power, wireless transmission distance can reach 200 meters.Pin one 3,14 is used for and CY7C68013A ?128AC carries out the serial communication that software flow is controlled, following two effects are arranged: 1. with resolve host computer issue CY7C68013A ?the control command of 128AC, thereby change the frequency of the CLK (output clock) of pin one 1 output, finally reach the purpose that changes the TCD1252 output frequency; 2. when this circuit working at wireless mode the time, be used for receiving CY7C68013A ?the sampled data of 128AC storage, and finally send with wireless form.Pin two 8,29,30,31,35,36,37,38,39,40 connects ground connection after the filtering circuit that is comprised of filter capacitor C102 and C103,

42,47 connects ground connection after the filtering circuit that is comprised of C121 and C134, and pin two 3,24 connects respectively ground connection after C134, C135.Pin one 0 connects and draws resistance R 100, can not be restarted to guarantee CC2430.

Obviously, above-described embodiment of the present utility model is only for the utility model example clearly is described, and is not to be restriction to embodiment of the present utility model.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here need not also can't give all embodiments exhaustive.And these belong to apparent variation or the change that connotation of the present utility model extends out and still belong to protection domain of the present utility model.

Claims

1. A linear array CCD data acquisition circuit is characterized in that it comprises a sequential signal output circuit, an analog signal amplification circuit, an analog-to-digital conversion circuit, a USB interface circuit and a wireless circuit, and the core chip of the sequential circuit is a model EPL7064SLC44-10 The CPLD, by counting the output clock of the wireless microcontroller CC2430, generates the timing signals required to drive the line array CCD device TCD1252AP, the timing signals of the USB chip of the model CY7C68013A-128AC working in the slave type first-in-first-out storage area mode, and The sampling clock signal of the analog-to-digital conversion chip AD9220; the core chip of the USB interface circuit is a USB chip of the model CY7C68013A-128AC, which is used to convert, store and output the parallel output signal of the AD9920. If the circuit works in USB mode, Pack it into the block data transmission format of the USB protocol, and then communicate with the host computer via USB; when the circuit works in the wireless mode, CY7C68013A-128AC communicates with the CC2430 wireless single-chip microcomputer to control it to change the output clock frequency to Change the output frequency of TCD1252AP or send the stored sampling data to CC2430; the core chip of the analog-to-digital conversion circuit is the analog-to-digital conversion chip AD8031, which inverts and amplifies the output analog signal of TCD1252AP to make it conform to the convertible range of AD9220 0- 5 volts; the core chip of the wireless circuit is the wireless chip CC2430, which changes the clock signal output to EPL7064SLC44-10 through serial port communication. In wireless mode, it receives the sampled data stored by CY7C68013A-128AC and sends it out through the antenna.

2. linear array CCD data acquisition circuit according to claim 1, is characterized in that, described model is the CPLD chip of EPL7064SLC44-10, and its counting clock pin 43 connects the I/O output pin 11 of CC2430, tube Pins 31, 33, 24, and 19 generate the timing signals required to drive the TCD1252AP linear array CCD. Sampling clock signal, pins 1, 44, 18, 37, 36 generate the timing signal of EZ-USB chip CY7C68013A in slave FIFO storage area mode Restart RESET, SlaveFIFO write enable SLWREN, SlaveFIFO write SLWR, FIFO Addresses FADDR1 and FADDR0, data packet end PKTEND, used to control the reading and writing of FIFO in CY7C68013A, pins 32, 38, 13, and 7 are respectively connected to corresponding pins on the JTAG interface, and are used for downloading EPL7064SLC44-10 program; line array The output signal of the CCD device TCD1252 is used as the input signal of the signal amplifier chip AD8031. The output pin 7 and the input pin 3 of the AD8031 form a reverse amplification circuit through the resistors Rf and R7, which is used to amplify the input signal OS. The pin 2 is connected to Reference voltage pin VIN-.

3. The linear array CCD data acquisition circuit according to claim 1, characterized in that, the USB interface circuit, 44, 45, 46, 47, 54, 55, 56, 57, 103, 104 of CY7C68013A-128AC , 405 pins are respectively connected to the BIT12-BIT1 pins of the analog-to-digital conversion chip AD9220, which are used to read the digital signal generated by the AD9220, and the pins 101 and 99 are respectively connected to the pull-up resistors R2 and R3 to ensure that the two pins The level will not be pulled low to be woken up or restarted. Pin 82 is connected to the SH signal of EPL7064SLC44-10 to generate an interrupt. Pins 51 and 52 are respectively connected to pins 13 and 14 of CC2430 for software communication with CC2430. Flow-controlled serial communication, pins 18 and 19 are respectively connected to pins 3 and 2 of the USB interface for USB communication with the host computer; pin 1 of the USB interface is connected to the voltage conversion chip LT1117 for the operation of this circuit In USB mode, it provides power for the entire circuit, and the CY7C68013A-128AC chip supports USB2.0.

4. linear array CCD data acquisition circuit according to claim 1, is characterized in that, described analog-to-digital conversion circuit, analog-to-digital conversion chip AD9220 pin 18,24 connects the filter circuit formed by electric capacity C15, C16 parallel connection , pins 20 and 21 are respectively connected to the CAPB and CAPT terminals of the filter circuit composed of C12, C13 and C14, and the pin 22 is connected to the external filter capacitor C9 and grounded, and the 5 volt voltage is filtered by C8 and then connected to the AD9220 analog circuit. The voltage input pin 15 is connected to the working voltage input pin 28 of the digital circuit of the AD9220 after passing through the filter circuit composed of E1, C10, and C11. The 17, 19, 25, and 27 pins of the AD9220 are directly grounded, and the input pins of the LT1117 Connect to pin 1 of the USBHeader, and the output pin is connected to the filter capacitor E3 for 3.3V output.

5. the linear array CCD data acquisition circuit according to claim 1, is characterized in that, described wireless circuit, RED is red LED indicator light, and LED is green indicator light, and crystal oscillator Y1, Y2 are used for providing CC2430 wireless single-chip microcomputer The clock consists of L100, L101, L102, C112 and the transmitting antenna PCR to form a wireless transmitting circuit. Pins 13 and 14 are used for serial communication with CY7C68013A-128AC for software flow control. It has the following two functions: 1) to analyze the host computer Send the control command to CY7C68013A-128AC to change the frequency of the clock output by pin 11, and finally achieve the purpose of changing the output frequency of TCD1252; 2) When the circuit works in wireless mode, it is used to receive samples stored by CY7C68013A-128AC The data is finally sent out in the form of wireless. Pins 28, 29, 30, 31, 35, 36, 37, 38, 39, and 40 are connected to the filter circuit composed of filter capacitors C102 and C103 and then grounded. Pins 42, 47 is connected to the filter circuit composed of C121 and C134 and grounded; pins 23 and 24 are connected to C134 and C135 respectively and then grounded; pin 10 is connected to pull-up resistor R100 to ensure that CC2430 will not be restarted.