CN203269551U - Integrated chip of MEMS and integrated circuit - Google Patents
Integrated chip of MEMS and integrated circuit Download PDFInfo
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- CN203269551U CN203269551U CN 201320247175 CN201320247175U CN203269551U CN 203269551 U CN203269551 U CN 203269551U CN 201320247175 CN201320247175 CN 201320247175 CN 201320247175 U CN201320247175 U CN 201320247175U CN 203269551 U CN203269551 U CN 203269551U
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- 239000000758 substrate Substances 0.000 claims abstract description 63
- 238000004806 packaging method and process Methods 0.000 claims description 58
- 238000002955 isolation Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 229910052732 germanium Inorganic materials 0.000 claims description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 229910045601 alloy Inorganic materials 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000002210 silicon-based material Substances 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 5
- 239000010410 layer Substances 0.000 description 112
- 238000000034 method Methods 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 238000002360 preparation method Methods 0.000 description 7
- 230000035945 sensitivity Effects 0.000 description 7
- 238000001259 photo etching Methods 0.000 description 6
- 238000001514 detection method Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
The utility model relates to an integrated chip of an MEMS (micro electro mechanical system) and an integrated circuit. The integrated chip comprises a first chip, the first chip comprises a substrate, an MEMS device layer, a first lead wire layer and a first electric bonding point, wherein the MEMS device layer is provided with a movable sensing part and arranged on the substrate, the first lead wire layer is arranged below the movable sensing part, the first electric bonding point is arranged on the MEMS device layer, the integrated chip of the MEMS and the integrated circuit further comprises a second chip and an electrical connecting layer, the second chip is provided with an IC (integrated circuit) and arranged on the first chip, the electrical connection layer is arranged on the first chip, the second chip comprises a second lead wire layer and a second electric bonding point in bonding with the first electric bonding point, the second lead wire layer and the first lead wire layer are symmetrically arranged on two sides of the movable sensing part, and the first chip further comprises an electrical connection part which is used for electrical connection of the first electric bonding point and the electrical connection layer.
Description
Technical field
The utility model relates to the integrated chip of a kind of MEMS and integrated circuit.
Background technology
MEMS (Micro-Electro-Mechanical Systems writes a Chinese character in simplified form MEMS) technology is a new and high technology of high speed development in recent years.Compare with the respective devices of being made by conventional art, the device that micro electro mechanical system (MEMS) technology is made is in volume, power consumption, weight and fairly obvious advantage is arranged in price, and it adopts the sophisticated semiconductor manufacturing process, can realize the batch manufacturing of mems device, on market, the main application example of mems device comprises pressure sensor, accelerometer, gyroscope, reaches silicon microphone etc. at present.
Mems device need to be connected with integrated circuits (CMOS/Bipolar) such as driving, detection, signal processing and integrates to become a system with complete standalone feature.Present existing Integrated Solution is of a great variety, and circuit and mems device are produced on that to be called monolithic on same chip integrated, and the integrated sequencing by making device of monolithic can be divided into Pre-CMOS and POST-CMOS.Pre-CMOS makes integrated circuit after referring to first make mems device, and the shortcoming of this kind scheme is that mems device can have pollution problem to follow-up integrated circuit technology, and may pollute manufacturing equipment, causes the ic failure of following process; POST-CMOS reprocesses mems device after the integrated circuit that completes, but the processing mems device generally needs high-temperature technology, and high-temperature technology will cause the circuit malfunction of completion of processing.Though above-mentioned each problem can take certain method to solve, and generally can cause process complications again, cost increases, so the scope of application of monolithic integrated technique is restricted, so cause the device of considerable part can not adopt this kind method.
Another kind of integrated scheme is that mems device and the multi-chip module of integrated antenna package in same shell is integrated.at first this scheme is made mems device and integrated circuit separately respectively, then both are adjacent to be arranged on same substrate, and by Bonding, both are electrically connected, carry out again pottery or Metal Packaging integrated to complete, the shortcoming one of this kind scheme is by realizing than long lead due between the two electrical connection, can introduce more interfering signal, and then cause overall performance to descend, the 2nd, because mems device is generally that size is at the movable member of the micron quantity utmost point, and these parts are comparatively fragile, therefore can not adopt Plastic Package during encapsulation and integration, and need adopt pottery or Metal Packaging, increased like this cost, the packaging cost of common mems device is 10 ~ 100 times of the own cost of mems device.
Therefore, how to solve the shortcoming that prior art exists and become to realize low-cost integrated scheme the technical task that those skilled in the art need to be resolved hurrily.
The utility model content
The purpose of this utility model is to provide a kind of MEMS of sensitivity and integrated chip of integrated circuit of improving.
for realizing aforementioned purpose, the utility model adopts following technical scheme: the integrated chip of a kind of MEMS and integrated circuit, comprise the first chip, described the first chip comprises substrate, be arranged on described substrate and have the mems device layer of movable sensitive section, be arranged on the first trace layer of described movable sensitive subordinate side, and be arranged on the first electrical bond chalaza on described mems device layer, the integrated chip of described MEMS and integrated circuit also comprises the second chip that is arranged on the first chip and has the IC integrated circuit, and be arranged on electrical connection layer on the first chip, described the second chip comprises the second trace layer, and with the second electrical bond chalaza of described the first electrical bond chalaza bonding, described the second trace layer and the first trace layer are symmetricly set on the both sides of described movable sensitive section, described the first chip also comprises the electric connection part that is electrically connected in order to the first electrical bond chalaza and electrical connection layer.
As further improvement of the utility model, described the first chip also comprises the isolation part that is arranged in described substrate and is around in the electric connection part periphery.
As further improvement of the utility model, described isolation part comprises the through hole that connects substrate, be positioned at the polysilicon layer of described through hole and be around in the silicon oxide layer of described polysilicon layer periphery.
As further improvement of the utility model, described isolation part comprises the through hole that connects substrate and the silica of filling described through hole.
As further improvement of the utility model, described substrate comprises that described electrical connection layer is arranged on the back side of described substrate towards the front and the relative described positive back side that arranges of described the second chip.
As further improvement of the utility model, the described substrate of perforation is extended from the back side that just faces described substrate of described substrate in described isolation part.
As further improvement of the utility model, described isolation part ringwise.
As further improvement of the utility model, described the second electrical bond chalaza is positioned at the outside of described movable sensitive section.
As further improvement of the utility model, also comprise the first packaging ring that is arranged on described mems device layer and is positioned at the described first electrical bond chalaza outside on described the first chip, described the second chip also comprises with described the first packaging ring bonding and is positioned at second packaging ring in the described second electrical bond chalaza outside.
As further improvement of the utility model, described the first electrical bond chalaza and the first packaging ring are formed by germanium material, with described the second electrical bond chalaza and second packaging ring of bonding are formed by aluminum respectively by formed the first electrical bond chalaza of germanium material and the first packaging ring; Perhaps, described the first electrical bond chalaza and the first packaging ring are formed by gold copper-base alloy, with described the second electrical bond chalaza and second packaging ring of bonding are formed by polycrystalline silicon material respectively by formed the first electrical bond chalaza of gold copper-base alloy and the first packaging ring.
The beneficial effects of the utility model are: the integrated chip of MEMS of the present utility model and integrated circuit is by being provided with the second chip with the first chip bonding, the second chip has the second trace layer, and the second trace layer and the first trace layer are symmetricly set on movable sensitive section both sides, so can rationally utilize the bonding gap between the first chip and the second chip, parasitic capacitance effectively is utilized as Detection capacitance, has improved the sensitivity of the integrated chip of MEMS and integrated circuit.
Description of drawings
Fig. 1 is the structural representation of the integrated chip of MEMS in the utility model specific embodiment and integrated circuit.
Fig. 2 to Fig. 7 is the flow chart of the first chip of the integrated chip of the preparation MEMS of Fig. 1 and integrated circuit.
Fig. 8 is the structure chart of the second chip of the integrated chip of the MEMS of Fig. 1 and integrated circuit.
Fig. 9 to Figure 19 is the part flow chart of the integrated chip of MEMS and integrated circuit in preparation Fig. 1.
Figure 20 is the top view of the first chip in the mems device of another embodiment in the utility model specific embodiment.
Figure 21 is the top view of the first chip of mems device in another embodiment in the utility model specific embodiment.
Figure 22 is the another kind of structural representation in the substrate preparation process of the first chip of Fig. 6.
The specific embodiment
See also Fig. 1, the MEMS in the utility model one embodiment and the integrated chip 10 of integrated circuit comprise the first chip 1, with the first chip 1 bonding setting and have the second chip 2 of IC integrated circuit (not shown) and be arranged on the first chip 1 in order to the electrical connection layer 3 of external circuitry electrical connection.In the present embodiment, the external circuitry of electrical connection layer 3 correspondence is the ASIC circuit.
The first chip 1 comprises the first substrate 11, be arranged on oxide layer 12 on the first substrate 11, be arranged on the first trace layer 13, sacrifice layer 14 and mems device layer 15 on oxide layer 12, be arranged on the first electrical bond chalaza 16 and the first packaging ring 17 on mems device layer 15, be arranged on the electric connection part 18 in the first substrate 11 and be arranged in the first substrate 11 and be around in the isolation part 19 of electric connection part 18 peripheries.The first substrate 11 has front 111 and the back side 112 that is oppositely arranged.Oxide layer 12 is positioned at the front 111 of the first substrate 11.Electrical connection layer 3 is arranged on the back side 112 of the first substrate 11.The front 111 of the first substrate 11 is towards the second chip 2.The first trace layer 13 realizes signal output.This first substrate 11 can be silicon substrate.
Above-mentioned the first chip 1 can be considered MEMS (MEMS) device, and the first chip 1 can be the mems devices such as accelerator or gyroscope.Mems device layer 15 is bascule.Mems device layer 15 comprises narrow groove 151, formed by narrow groove 151 movable sensitive section 152 and the fixed part 153 that is positioned at movable sensitive section 152 outsides.Narrow groove 151 obtains by photoetching and etching.The first trace layer 13 is positioned at the below of movable sensitive section 152.The first electrical bond chalaza 16 and the first packaging ring 17 are fixed on fixed part 153, and the first packaging ring 17 is positioned at the outside of the first electrical bond chalaza 16.The material of above-mentioned the first electrical bond chalaza 16 is germanium or gold, and the material of the first packaging ring 17 is with the material of the first electrical bond chalaza 16.
In this example, isolation part 19 comprises the through hole 191 that connects the first substrate 11, is positioned at the polysilicon layer 192 of through hole 191 and is around in the silicon oxide layer 193 of polysilicon layer 192 peripheries.Really, above-mentioned polysilicon layer 192 and silicon oxide layer 193 also can replace by the silica that is filled in through hole 191.
The second trace layer 24 on the second surface 25 that the second chip 2 comprises the second substrate 21 with the first surface 26 that is oppositely arranged and second surface 25, be arranged on the second substrate 21 and be arranged on the second electrical bond chalaza 22 and the second packaging ring 23 on the second surface 25 of the second substrate 21.The second packaging ring 23 is positioned at the outside of the second electrical bond chalaza 22.The second surface 25 of the second chip 2 is towards the first chip 1.The second electrical bond chalaza 22 and the first electrical bond chalaza 16 bondings, the second packaging ring 23 and the first packaging ring 17 bondings.The second trace layer 24 is identical with the first trace layer 13, in order to realize the output of signal.The first trace layer 24 and the second trace layer 13 as symmetry axis, are symmetricly set on the both sides of movable sensitive section 152 with movable sensitive section 152.
Be symmetricly set on the both sides of movable sensitive layer 152 due to the second trace layer 24 and the first trace layer 13, so, the change in displacement that the plane motion of the mems device layer 15 in the first chip 1 can be brought is converted into laterally zygomorphic minute poor capacitance variations, thereby effectively raise the sensitivity of the first chip 1, and then improve the sensitivity of the integrated chip 10 of MEMS and integrated circuit.In the present embodiment, the second chip 2 is arranged on the top of the first chip 1, and electrical connection layer 3 is positioned at the below of the first chip 1, and the first trace layer 13 and the second trace layer 13 are oppositely arranged on respectively the both sides up and down of movable sensitive layer 152.
In the present embodiment, the material of above-mentioned the first electrical bond chalaza 16, the first packaging ring 17, the second electrical bond chalaza 22 and the second packaging ring 23 can be selected as follows: when the first electrical bond chalaza 16 and the first packaging ring 17 are formed by germanium material, with the second electrical bond chalaza 22 and 23 of second packaging rings of bonding are formed by aluminum respectively by formed the first electrical bond chalaza 16 of germanium material and the first packaging ring 17.When the first electrical bond chalaza 16 and the first packaging ring 17 are formed by gold copper-base alloy, with the second electrical bond chalaza 22 and 23 of second packaging rings of bonding are formed by polycrystalline silicon material respectively by formed the first electrical bond chalaza 16 of gold copper-base alloy and the first packaging ring 17.By adopting above-mentioned material, make the first electrical bond chalaza 16, the second electrical bond chalaza 22 and the first packaging ring 17, the second packaging ring 23 thin thickness, thereby reduced the volume of integrated chip 10 integral body of MEMS and integrated circuit.
Electrical connection layer 3 comprises the pedestal 4 that adopts BGA (Ball Grid Array is called for short BGA) encapsulation technology to form.
Because the integrated chip 10 of above-mentioned MEMS and integrated circuit is provided with the second chip 2 with the first chip 1 bonding, the second chip 2 has the second trace layer 24, and the second trace layer 24 and the first trace layer 13 are symmetricly set on movable sensitive section 152 both sides, so can rationally utilize the bonding gap between the first chip 1 and the second chip 2, parasitic capacitance effectively is utilized as Detection capacitance, has improved the sensitivity of the integrated chip 10 of MEMS and integrated circuit.
The preparation method of the integrated chip 10 of MEMS of the present utility model and integrated circuit comprises that S1 step described as follows is to the S6 step.
Please in conjunction with Fig. 7, S1: the first chip 1 is provided.the first chip 1 comprises having the front 111 that is oppositely arranged and first substrate 11 at the back side 112, be arranged on the oxide layer 12 in the first substrate 11 fronts 111, be arranged on the first trace layer 13 on oxide layer 12, sacrifice layer 14 and mems device device layer 15, be arranged on the first electrical bond chalaza 16 and the first packaging ring 17 on mems device layer 15, be arranged on the first substrate 11 and from the front 111 of the first substrate 11 towards the back side 112 isolation parts that extend to form 19, and be formed in isolation part 19 and with the electric connection part 18 of mems device layer 15 electrical connection.The first trace layer 13 can realize signal output.This first substrate 11 can be silicon substrate.
Above-mentioned mems device layer 15 comprises narrow groove 151, formed by narrow groove 151 movable sensitive section 152 and the fixed part 153 that is positioned at movable sensitive section 152 outsides.Narrow groove 151 obtains by photoetching and etching.The first trace layer 13 is positioned at the below of movable sensitive layer 152.The first electrical bond chalaza 16 and the first packaging ring 17 are fixed on fixed part 153, and the first packaging ring 17 is positioned at the outside of the first electrical bond chalaza 16.This first chip 1 can be considered mems device, and this mems device can be the mems devices such as accelerator or gyroscope.
Please in conjunction with Fig. 2 to Fig. 7, the first concrete employing as following S11 step to S16 process of chip 1 in above-mentioned S1 step realized.
Please in conjunction with Fig. 2, S11: the first substrate 11 is provided.The first substrate 11 comprises front 111 and the back side 112 that is oppositely arranged, and carries out oxidation and obtain oxide layer 113 on the front 111 of the first substrate 1.This oxide layer 113 is silica material.The formation of this oxide layer 113 can be adopted low-pressure chemical vapor phase deposition (LPCVD) or the technology modes such as plasma chemical vapor deposition (PECVD) or thermal oxide.
Please in conjunction with Fig. 3, S12: on the oxide layer 113 that obtains in the S11 step, mapping forms a via hole image 114.In this step, via hole image 114 is main by photoetching, dry etching, and perhaps the partial oxygen SiClx on the technique such as photoetching, wet etching removal oxide layer 113 obtains.In the present embodiment, be formed with altogether four via hole images 114 on oxide layer 113, and this via hole image 114 ringwise.Main its mask effect of oxide layer 113.
Please in conjunction with Fig. 4, S13: adopt deep trouth examples of reactions etching (DRIE) thus technique is carried out etching and is formed through hole 115 according to obtaining via hole image in the S12 step on the first substrate 11, meanwhile, the electric connection part 18 that is formed at through hole 115 centres and is surrounded by this through hole 115.Can find out from this step, this electric connection part 18 is to isolate formed on the first substrate 11 by through hole 115.Owing to being formed with four via hole images and via hole image ringwise in step S12 step, so in this step, the corresponding through hole 115 that forms four annulars, simultaneously, the cross sectional shape of four corresponding electric connection parts 18 be circle.
Please in conjunction with Fig. 5, S14: first deposit one deck silicon oxide layer 191 in the through hole that obtains in the S13 step, the through hole that then will be deposited with silicon oxide layer 191 with polysilicon fills up to form polysilicon layer 192, and silicon oxide layer 191 and polysilicon layer 192 are combined to form isolation part 19.Owing to being formed with four ringwise through holes in step S13, so in this step, correspondence forms four ringwise isolation parts 19.
See also Fig. 6, S15: remove the oxide layer that forms in the S11 step.
See also Fig. 7, S16: forming mems device layer 15 with movable sensitive section 152 on the front 111 of the first substrate 11 of removing oxide layer, be positioned at below movable sensitive section 152 and can realizing first trace layer 13 etc. of signal output.Form on mems device layer 15 with the S13 step in electric connection part 18 electrical connections that form the first electrical bond chalaza 16 and form the first packaging ring 17 on mems device layer 15.In this step, mems device layer 15 and the first trace layer 13 etc. is conventional means in prior art, as, mems device layer 15 can adopt the extension polysilicon process, therefore do not giving unnecessary details at this.
Above-mentioned S14 step can also adopt following steps to replace: S14 ': in the through hole that obtains in the S13 step, silicon oxide deposition is to form isolation part 19 '.See also Figure 22.
Please in conjunction with Fig. 8, S2: the second chip 2 with IC integrated circuit is provided.The second chip 2 comprises the second substrate 21 with the first surface 26 that is oppositely arranged and second surface 25, be arranged on the second trace layer 24 on the second substrate 21 and be arranged on the second electrical bond chalaza 22 and the second packaging ring 23 on the second substrate 26.The second trace layer 24 is the same with the first trace layer, can realize signal output.The second electrical bond chalaza 22 is positioned at the outside of the second trace layer 24, and the second packaging ring 23 is positioned at the outside of the second electrical bond chalaza 22.
See also Fig. 9 and Figure 10, S3: with the first electrical bond chalaza 16 and the second electrical bond chalaza 22 bondings, the first packaging ring 17 and the second packaging ring 23 bondings, the first trace layer 13 and the second trace layer 24 symmetries are in the both sides of movable sensitive section 152.In the present embodiment, the second chip 2 is arranged on the top of the first chip 1, and the first trace layer 13 and the second trace layer 24 are oppositely arranged on the both sides up and down of movable sensitive section 152.
See also Figure 11 and Figure 12, S4: the first substrate 11 of the first chip 1 after S3 step bonding 112 is carried out attenuate and operates to expose isolation part 19 in the back side.In this step, the mode by the CMP attenuate realizes the attenuate to the first substrate 11.After attenuate, the attenuate face that is oppositely arranged with the front 111 of the first substrate 11 still is called the back side 112.
Because four cross sectional shapes that form in S23 step and S24 step are circular electric connection part 18, so the back side 112 in the first substrate 11 can be observed, cross sectional shape is the electric connection part 18 of four circles, and in the present embodiment, this electric connection part 18 is symmetricly set on the two ends of the first substrate 11.Really, this electric connection part 18 ' can also be arranged to other shapes and quantity, be arranged to six cross sections as quantity and be quadrangle or oval-shaped electric connection part 18 ', and the isolation part 19 ' corresponding with it also is other shapes, arrangement mode also can form other arrangement mode according to concrete design, see also Figure 20 and Figure 21.
See also Figure 19, S5: form the electrical connection layer 3 with the external circuitry electrical connection on the back side 112 of the first substrate 11 after described S4 step attenuate.
Please in conjunction with Figure 13 to Figure 19, the concrete employing as following S51 step to S55 process of the electrical connection layer in above-mentioned S5 step realized.
Please in conjunction with Figure 13, S51: silicon oxide deposition forms oxide layer 301 on the back side 112 of the first substrate 111 after S4 step attenuate.This oxide layer 301 mainly plays the mask effect.The preparation method of oxide layer 301 is the various depositing technics of employing, as: the processes such as low-pressure chemical vapor phase deposition (LPCVD) or plasma chemical vapor deposition (PECVD) or thermal oxide.
Please in conjunction with Figure 14 to Figure 16, S52: by photoetching, dry etching, perhaps the technique such as photoetching, wet etching is removed partial oxidation layer 301 to expose electric connection part 18.Then deposit the first metal layer 302 and form metal routing 303.Metal routing 303 middle parts are divided into the electrical connection signal routing.Metal routing 303 can be adjusted the wiring form according to the different structure form of different design needs, external circuitry.Its purpose is the electric connecting point of rationally arranging, and realizes being connected with the optimization of external circuitry etc.In the present embodiment, the external circuitry of electrical connection layer 3 correspondence is the ASIC circuit.
S53: deposit one deck passivation layer (not shown) is as protective layer again.This passivation layer can adopt silica or silicon nitride material.Its preparation method adopts various depositing technics, as: the processes such as low-pressure chemical vapor phase deposition (LPCVD) or plasma chemical vapor deposition (PECVD) or thermal oxide.Its purpose plays shielding for the metal routing 303 that will form in the S52 step separates with the external world.
Please in conjunction with Figure 17 and Figure 18, S54: the passivation layer that forms in removal part S53 step makes and needs in metal routing 303 to expose with the part of extraneous bonding, simultaneously deposit the second metal level 304 on the metal routing 303 that exposes.The material of formed the second metal level 304 is aluminium or gold in this step.
See also Figure 19, S55: adopt the BGA Package technology to form pedestal 4 on the second metal level 305.
In above-mentioned S1 and S2 step, when the material that forms the first electrical bond chalaza 16 was germanium, the material that forms the second electrical bond chalaza 22 was aluminium; When the material that forms the first electrical bond chalaza 16 be gold, the material of formation the second electrical bond chalaza 22 is polysilicon.Form the material of the second packaging ring 23 with the collocation of the material that forms the second electrical bond chalaza 22 by the employing above-mentioned material, make the thin thickness of the first electrical bond chalaza 16, the second electrical bond chalaza 22 and the first packaging ring 17, the second packaging ring 23, thereby reduce the volume of mems device 10 integral body.
the manufacture method of the integrated chip 10 by above-mentioned MEMS and integrated circuit can realize wafer level integration packaging (Wafer Level Chip Scale Packaging, be called for short WLCSP), reduced the size of the integrated chip 10 of MEMS and integrated circuit, again owing to making the first chip 1 and the second chip 2 bondings, by the second trace layer 24 is set on the second chip 2, and this second trace layer 24 and the first trace layer 13 are symmetricly set on the both sides of movable sensitive section 152, thereby rationally utilized the bonding gap between mems device layer 15 and integrated circuit, parasitic capacitance effectively is utilized as Detection capacitance, improved the sensitivity of the integrated chip 10 of this MEMS and integrated circuit.
In sum: the integrated chip 10 of MEMS of the present utility model and integrated circuit has following advantage:
1, realize the wafer level integration packaging of the integrated chip 10 of MEMS and integrated circuit, reduced the volume of the integrated chip 10 of MEMS and integrated circuit.
2, by the second trace layer 24 is set on the second chip 2, and this second trace layer 24 and the first trace layer 13 are symmetricly set on the both sides of movable sensitive section 152, thereby rationally utilized the bonding gap between mems device layer 15 and integrated circuit, parasitic capacitance effectively is utilized as Detection capacitance, has improved the sensitivity of the integrated chip 10 of this MEMS and integrated circuit.
3, owing to adopting the first chip 1 and the second chip 2 bondings and the movable sensitive section 152 of the first chip 1 being formed in seal cavity, and scribing is carried out after the integrated chip 10 of MEMS and integrated circuit is sealed, be easy to impaired problem so can solve the movable sensitive section 152 of the integrated chip 10 of MEMS and integrated circuit when scribing, avoid adopting the expensive dicing methods such as laser, saved cost.
4, owing to adopting the first chip 1 and the second chip 2 bondings and the movable sensitive section 152 of the first chip 1 being formed in seal cavity, can complete to the vacuum seal of the integrated chip 10 of MEMS and integrated circuit or with the integrated chip 10 of MEMS and integrated circuit being enclosed in some specific inert gas when integrated.In addition, can adopt the Plastic Package mode in follow-up encapsulation, but not expensive metal or ceramic package have reduced packaging cost.
5, same, owing to adopting the first chip 1 and the second chip 2 bondings and the movable sensitive section 152 of the first chip 1 being formed in seal cavity, so the integrated chip 10 of this MEMS and integrated circuit can be realized the effect of electromagnetic shielding.
6, in integrated chip 10 preparation methods of above-mentioned MEMS and integrated circuit, due to the first electrical bond chalaza 16 and corresponding germanium material and aluminum or corresponding gold copper-base alloy and the polycrystalline silicon material of adopting of adopting of the second electrical bond chalaza 22, the first packaging ring 17 and the second packaging ring 23, but so the thickness of attenuate the first electrical bond chalaza 16 and the second electrical bond chalaza 22, the first packaging ring 17 and the second packaging ring 23, thereby also reduced the volume of integrated chip 10 integral body of MEMS and integrated circuit.
Although be the example purpose, preferred embodiment of the present utility model is disclosed, but those of ordinary skill in the art will recognize, in the situation that do not break away from by the disclosed scope and spirit of the present utility model of appending claims, various improvement, increase and replacement are possible.
Claims (10)
1. the integrated chip of a MEMS and integrated circuit, comprise the first chip, described the first chip comprises substrate, be arranged on described substrate and have the mems device layer of movable sensitive section, be arranged on the first trace layer of described movable sensitive subordinate side, and be arranged on the first electrical bond chalaza on described mems device layer, it is characterized in that: the integrated chip of described MEMS and integrated circuit also comprises the second chip that is arranged on the first chip and has the IC integrated circuit, and be arranged on electrical connection layer on the first chip, described the second chip comprises the second trace layer, and with the second electrical bond chalaza of described the first electrical bond chalaza bonding, described the second trace layer and the first trace layer are symmetricly set on the both sides of described movable sensitive section, described the first chip also comprises the electric connection part that is electrically connected in order to the first electrical bond chalaza and electrical connection layer.
2. the integrated chip of MEMS according to claim 1 and integrated circuit is characterized in that: described the first chip also comprises the isolation part that is arranged in described substrate and is around in the electric connection part periphery.
3. the integrated chip of MEMS according to claim 2 and integrated circuit is characterized in that: described isolation part comprises the through hole that connects substrate, be positioned at the polysilicon layer of described through hole and be around in the silicon oxide layer of described polysilicon layer periphery.
4. the integrated chip of MEMS according to claim 2 and integrated circuit is characterized in that: described isolation part comprises the through hole that connects substrate and the silica of filling described through hole.
5. the integrated chip of according to claim 3 or 4 described MEMSs and integrated circuit, it is characterized in that: described substrate comprises that described electrical connection layer is arranged on the back side of described substrate towards the front and the relative described positive back side that arranges of described the second chip.
6. the integrated chip of MEMS according to claim 5 and integrated circuit is characterized in that: described isolation part is extended from the back side that just faces described substrate of described substrate and is connected described substrate.
7. the integrated chip of MEMS according to claim 2 and integrated circuit, it is characterized in that: described isolation part ringwise.
8. the integrated chip of MEMS according to claim 1 and integrated circuit is characterized in that: described the second electrical bond chalaza is positioned at the outside of described movable sensitive section.
9. the integrated chip of MEMS according to claim 8 and integrated circuit, it is characterized in that: also comprise the first packaging ring that is arranged on described mems device layer and is positioned at the described first electrical bond chalaza outside on described the first chip, described the second chip also comprises with described the first packaging ring bonding and is positioned at second packaging ring in the described second electrical bond chalaza outside.
10. the integrated chip of MEMS according to claim 9 and integrated circuit, it is characterized in that: described the first electrical bond chalaza and the first packaging ring are formed by germanium material, with described the second electrical bond chalaza and second packaging ring of bonding are formed by aluminum respectively by formed the first electrical bond chalaza of germanium material and the first packaging ring; Perhaps, described the first electrical bond chalaza and the first packaging ring are formed by gold copper-base alloy, with described the second electrical bond chalaza and second packaging ring of bonding are formed by polycrystalline silicon material respectively by formed the first electrical bond chalaza of gold copper-base alloy and the first packaging ring.
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| CN 201320247175 CN203269551U (en) | 2013-05-09 | 2013-05-09 | Integrated chip of MEMS and integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320247175 CN203269551U (en) | 2013-05-09 | 2013-05-09 | Integrated chip of MEMS and integrated circuit |
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| CN203269551U true CN203269551U (en) | 2013-11-06 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103552980A (en) * | 2013-11-15 | 2014-02-05 | 安徽北方芯动联科微系统技术有限公司 | Wafer level packaging method for micro electromechanical system (MEMS) chip and single-chip micro-miniature type MEMS chip |
| CN103979481A (en) * | 2014-05-28 | 2014-08-13 | 杭州士兰集成电路有限公司 | MEMS aluminum and germanium bonding structure and manufacturing method thereof |
| CN104140072A (en) * | 2013-05-09 | 2014-11-12 | 苏州敏芯微电子技术有限公司 | Integrated chip of micro-electro-mechanical system and integrated circuit and manufacturing method of integrated chip |
| CN105980293A (en) * | 2014-02-25 | 2016-09-28 | 诺思罗普·格鲁曼·利特夫有限责任公司 | Method for producing a component, and component |
| CN109205550A (en) * | 2017-06-30 | 2019-01-15 | 台湾积体电路制造股份有限公司 | MEMS device structure and method of forming the same |
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2013
- 2013-05-09 CN CN 201320247175 patent/CN203269551U/en not_active Withdrawn - After Issue
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104140072A (en) * | 2013-05-09 | 2014-11-12 | 苏州敏芯微电子技术有限公司 | Integrated chip of micro-electro-mechanical system and integrated circuit and manufacturing method of integrated chip |
| CN104140072B (en) * | 2013-05-09 | 2016-07-13 | 苏州敏芯微电子技术股份有限公司 | The integrated chip of MEMS and integrated circuit and manufacture method thereof |
| CN103552980A (en) * | 2013-11-15 | 2014-02-05 | 安徽北方芯动联科微系统技术有限公司 | Wafer level packaging method for micro electromechanical system (MEMS) chip and single-chip micro-miniature type MEMS chip |
| CN105980293A (en) * | 2014-02-25 | 2016-09-28 | 诺思罗普·格鲁曼·利特夫有限责任公司 | Method for producing a component, and component |
| CN105980293B (en) * | 2014-02-25 | 2019-01-04 | 诺思罗普·格鲁曼·利特夫有限责任公司 | For manufacturing the method and component of component |
| CN103979481A (en) * | 2014-05-28 | 2014-08-13 | 杭州士兰集成电路有限公司 | MEMS aluminum and germanium bonding structure and manufacturing method thereof |
| CN109205550A (en) * | 2017-06-30 | 2019-01-15 | 台湾积体电路制造股份有限公司 | MEMS device structure and method of forming the same |
| CN109205550B (en) * | 2017-06-30 | 2020-11-24 | 台湾积体电路制造股份有限公司 | MEMS device structure and method of forming the same |
| US10865100B2 (en) | 2017-06-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming micro-electro-mechanical system (MEMS) structure |
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