CN203217560U

CN203217560U - Bus converter

Info

Publication number: CN203217560U
Application number: CN 201320181126
Authority: CN
Inventors: 刘军; 吴勇; 徐阳; 刘月; 刘华涵
Original assignee: Beijing BNC Technologies Co Ltd
Current assignee: Beijing BNC Technologies Co Ltd
Priority date: 2013-04-11
Filing date: 2013-04-11
Publication date: 2013-09-25
Anticipated expiration: 2023-04-11

Abstract

The utility model discloses a bus converter which is connected with an outer ISA device. The bus converter comprises a CPU, a bus converter and a data resolver. The CPU is connected with the bus converter and the data resolver. The bus converter is connected with the CPU, the data resolver and the outer ISA device. The bus converter receives multiple paths of parallel interrupt signals which are transmitted by the outer ISA device, generates a path of serial interrupt signals after coding the parallel interrupt signals and transmits the path of serial interrupt signals to the data resolver. The bus converter is further responsible for data interaction between an ISA bus and a PCI bus. The data resolver receives the serial interrupt signals sent by the bus converter and resolves the serial interrupt signals to generate complete analysis data. The CPU receives the analysis data sent by the data resolver, processes the analysis data, responds correspondingly, generates control data and transmits the control data to the bus converter. The bus converter then transmits the control data to the outer ISA device.

Description

Bus conversion device

Technical Field

The utility model relates to a field that computer bus used relates to a bus conversion equipment.

Background

At present, a Central Processing Unit (CPU) adopted by most of mainboards is an X86CPU or an ARM, key chips are produced in foreign countries, and a back door may be left in the chips by chip production companies, so that potential safety hazards exist. And the key parts of the product are restricted by outsiders, so that the product is inconvenient to be used in key fields such as military and the like.

Nowadays, an ISA bus interface belongs to a rejected bus interface and is only applied to some special fields such as military industry and the like, so that the current solution in the market is insufficient, and the special requirements of some special fields such as military industry and the like on safety and reliability and stability cannot be met.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the technical problem that solves has overcome prior art's shortcoming, utilizes a central processing unit and bus converter that information security and reliability aspects are stronger, carries out the conversion of bus to satisfy the application to the ISA bus.

The utility model provides a bus conversion device connects in outside ISA equipment, bus conversion device includes: a central processing unit, a bus converter and a data parser; the central processing unit is connected with the bus converter and the data analyzer, and the bus converter is connected with the central processing unit, the data analyzer and the external ISA equipment; the bus converter is connected with the external ISA equipment through an ISA bus, the bus converter is connected with the central processing unit through a PCI bus, the bus converter is connected with the data analyzer through a single serial line, and the central processing unit is connected with the data analyzer through the PCI bus; the bus converter receives a plurality of paths of parallel interrupt signals sent by the external ISA equipment, encodes the plurality of paths of parallel interrupt signals to generate a path of serial interrupt signals, and sends the path of serial interrupt signals to the data analyzer; the data analyzer receives the serial interrupt signal sent by the bus converter, analyzes the serial interrupt signal, generates complete analysis data and sends the complete analysis data to the central processing unit; the central processing unit receives the analysis data sent by the data analyzer, processes the analysis data, responds correspondingly, generates control data and sends the control data to the bus converter, and the bus converter sends the control data to the external ISA equipment; the external ISA equipment receives the control data and sends the external ISA equipment data to the bus converter according to the control data; the bus converter also receives the external ISA device data and sends the external ISA device data to the central processing unit.

Further, the central processing unit is a Loongson2F central processing unit.

Further, the bus converter is an IT8888G chip.

Further, the data parser is an FPGA chip or a CPLD chip.

The utility model mainly adopts a Loongson2F central processing unit, which is obviously enhanced in information safety and reliability compared with the scheme of adopting foreign chips; the potential safety hazard caused by using a foreign chip is avoided, the development of a domestic CPU can be promoted, and people are prevented from being restricted in the key technical field. The ISA bus interface utilized in the utility model belongs to the eliminated bus interface, and is only applied in some special fields such as military industry, so that the solution suitable for the current stage on the market is not enough; the scheme can meet the requirement of special fields on the ISA bus, converts the commonly used PCI bus and the ISA bus, and can avoid the problem that some mature ISA devices in the fields cannot be used because of no proper application device.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

fig. 1 is a schematic structural diagram of a bus conversion device according to the present invention.

Fig. 2 is a schematic structural diagram of a bus conversion apparatus according to an embodiment of the present invention.

Fig. 3 is a schematic structural diagram of a bus conversion apparatus according to another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail with reference to the accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.

Fig. 1 is a schematic structural diagram of a bus conversion device according to the present invention. As shown in fig. 1, bus conversion apparatus 10 is externally connected to external ISA device 20, and includes central processing unit 101, bus converter 102 and data parser 103; the central processor 101 is connected to the bus converter 102 and the data parser 103, and the bus converter 102 is connected to the central processor 101, the data parser 103 and the external ISA device 104; bus converter 102 is connected with external ISA device 20 through ISA bus, bus converter 102 is connected with central processor 101 through PCI bus, bus converter 102 is connected with data analyzer 103 through single serial line, and central processor 101 is connected with data analyzer through PCI bus; wherein,

the external ISA device 20 sends out multiple parallel interrupt signals to the bus converter 102 in the bus conversion apparatus 10, and the bus converter 102 receives the multiple parallel interrupt signals, integrates and encodes the multiple parallel interrupt signals to generate one path of serial interrupt signals, and sends the serial interrupt signals to the data parser.

In the present embodiment, the bus converter 102 is an IT8888G chip.

The data analyzer 103 receives the serial interrupt signal sent by the bus converter 102, analyzes the serial interrupt signal to generate complete analysis data which can be read by the central processing unit 101, and sends the analysis data to the central processing unit 101;

in this embodiment, the data parser 103 is an FPGA chip or a CPLD chip.

The central processing unit 101 receives the analysis data sent by the data analyzer 103, processes the analysis data, responds accordingly, generates a control data, and sends the control data to the bus converter 102, and the bus converter 102 sends the control data to the external ISA device 20.

In the present embodiment, the cpu 101 is a Loongson2F cpu. The Loongson2F central processing unit is a domestic general RISC processor that implements the 64-bit MIPS iii instruction set.

The MIPS is a CPU architecture, and is applied to a Loongson2F CPU and a Loongson1A CPU described below.

In this embodiment, after the central processing unit 101 reads the analysis data, it performs data processing to determine what happens on the external ISA device 20, such as data arrival for reading, data transmission, and the like, and the central processing unit 101 responds accordingly, such as starting to transmit instructions such as data of the external ISA device 20, generates control data, and transmits the control data to the external ISA device 20 via the bus converter 102.

After receiving the control data sent by the central processing unit 101, the external ISA device 20 executes corresponding operations, such as transmitting external ISA device data, according to instructions of the central processing unit 101.

The bus converter 102 is responsible for data interaction between the ISA bus and the PCI bus, receiving external ISA device data, and transmitting the data to the central data 101 through the PCI bus.

Fig. 2 is a schematic structural diagram of a bus conversion apparatus according to an embodiment of the present invention. As shown in fig. 2, the central processing unit 301 of Loongson2F is a central processing unit responsible for controlling and operating the whole device. The IT8888G chip 302 is responsible for converting the PCI bus coming out of the central processor 301 in Loongson2F to an ISA bus. Because the number of interrupt lines on the ISA bus is too many (at least 20), and only 4 interrupt lines are provided on the PCI bus, the multiple (at least 20) parallel interrupt signals on the ISA bus cannot be transmitted to the PCI bus in a one-to-one correspondence, nor directly to the Loongson2F cpu 301, because the number of the remaining interrupt pins on the Loongson2F cpu 301 cannot meet the requirement of such many interrupt lines. Therefore, the IT8888G chip 302 integrates and codes signals sent from more than 20 parallel interrupt lines and then transmits the interrupt signals to the FPGA chip 303 through a serial port line, so that the FPGA chip 303 can resolve the serial interrupt signals into complete interrupt information and transmit the complete interrupt information to the Loongson2F central processing unit 301, and after data processing is performed by the Loongson2F central processing unit 301, return a control data to the external ISA device 20 to instruct the external ISA device 20 to operate next.

In this embodiment, because the FPGA chip 303 is also responsible for the CAN function on the device, analyzing the serial interrupt signal only uses a small part of the functions, if the CAN function is not needed, the FPGA chip 303 CAN be replaced by a CPLD chip to realize the function of analyzing the interrupt signal, which CAN reduce the cost.

In this embodiment, the IT8888G chip 302 converts the PCI bus into the ISA bus, and because the ISA interface has more interrupt pins but fewer interrupt pins, the IT8888G chip 302 converts the parallel interrupt signal integration code into the serial interrupt signal, and only needs 1 pin instead of the original 20 pins, thereby reducing the area occupied by the flat cable and reducing the difficulty of the manufacturing process.

Fig. 3 is a schematic structural diagram of a bus conversion apparatus according to another embodiment of the present invention. As shown in fig. 3, compared with the bus conversion apparatus 30 of fig. 2, the bus conversion apparatus 30 of the present embodiment further includes a central processing unit 304 of Loongson 1A; the central processor 304 of longson 1A is connected to the central processor 301 of longson 2F through a PCI bus, and in this embodiment, serves as a south bridge to control some IO devices, such as a network port, a serial port, a parallel port, an IDE interface, an audio interface, and the like.

The utility model discloses the core chip mainly adopts longson 2F central processing unit and longson 1A central processing unit. Compared with the scheme adopting a foreign chip, the information safety and reliability are obviously enhanced; the potential safety hazard caused by using a foreign chip is avoided, the development of a domestic CPU can be promoted, and people are prevented from being restricted in the key technical field. Moreover, the ISA bus interface utilized in the utility model belongs to the eliminated bus interface and is applied only in some special fields such as military industry, so that the solution suitable for the current stage on the market is not enough; the scheme can meet the requirement of special fields on the ISA bus, converts the commonly used PCI bus and the ISA bus, and can avoid the problem that some mature ISA devices in the fields cannot be used because of no proper application device.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above-mentioned embodiments are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A bus conversion apparatus connected to an external ISA device, comprising: a central processing unit, a bus converter and a data parser; the central processing unit is connected with the bus converter and the data analyzer, and the bus converter is connected with the central processing unit, the data analyzer and the external ISA equipment; the bus converter is connected with the external ISA equipment through an ISA bus, the bus converter is connected with the central processing unit through a PCI bus, the bus converter is connected with the data analyzer through a single serial line, and the central processing unit is connected with the data analyzer through the PCI bus; wherein,

the bus converter receives a plurality of paths of parallel interrupt signals sent by the external ISA equipment, encodes the plurality of paths of parallel interrupt signals to generate a path of serial interrupt signals, and sends the path of serial interrupt signals to the data analyzer;

the data analyzer receives the serial interrupt signal sent by the bus converter, analyzes the serial interrupt signal, generates complete analysis data and sends the complete analysis data to the central processing unit;

the central processing unit receives the analysis data sent by the data analyzer, processes the analysis data, responds correspondingly, generates control data and sends the control data to the bus converter, and the bus converter sends the control data to the external ISA equipment;

the external ISA equipment receives the control data and sends the external ISA equipment data to the bus converter according to the control data;

the bus converter also receives the external ISA device data and sends the external ISA device data to the central processing unit.

2. The apparatus of claim 1, wherein the central processor is a Loongson2F central processor.

3. The apparatus of claim 1, wherein the bus converter is an IT8888G chip.

4. The apparatus of claim 1, wherein the data parser is an FPGA chip or a CPLD chip.