CN203178636U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203178636U CN203178636U CN 201320067813 CN201320067813U CN203178636U CN 203178636 U CN203178636 U CN 203178636U CN 201320067813 CN201320067813 CN 201320067813 CN 201320067813 U CN201320067813 U CN 201320067813U CN 203178636 U CN203178636 U CN 203178636U
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Abstract
The utility model discloses an array substrate. The array substrate comprises a substrate body, a drive electrode, a first capacitor, a source electrode, a drain electrode and a first dielectric layer, wherein the first capacitor comprises a first capacitor electrode and a second capacitor electrode, the source electrode, the drain electrode, the drive electrode and the first capacitor electrode are formed on the substrate body and are covered by the first dielectric layer, the first dielectric layer comprises a first area covering the first capacitor electrode and a second area which covers the drive electrode and is thicker than the first area, glass melt glue is formed on the second area, and the second capacitor electrode is formed on the first area. Through the method, a display device adopting the array substrate can achieve a good glue-sealing effect.
Description
Technical field
The utility model relates to field of liquid crystal, particularly relates to a kind of array base palte and display device.
Background technology
Liquid crystal panel generally includes color membrane substrates and array base palte.The production process of liquid crystal panel generally includes array processing procedure, the upright processing procedure of group and module group procedure.The array processing procedure mainly comprises the production run of array base palte.The upright processing procedure of group mainly comprises the process that array base palte and color membrane substrates are fit together.Module group procedure then comprises the process that FPC circuit such as (Flexible Printed Circuit, flexible PCBs) is assembled.
Form TFT (Thin-Film Transistor, thin film transistor (TFT)), electric capacity and the pixel electrode that is arranged in array on the array base palte, and be formed at peripheral drive electrode.The power on/off of drive electrode control TFT, so drive electrode connects TFT and FPC.In the upright processing procedure of group, also be included in the step of the frame place sealing of array base palte and color membrane substrates before the step that array base palte and color membrane substrates are fit together.Specifically, sealing step comprises encapsulating and solidifies two steps.
OLED(Organic Electroluminesence Display, organic electric laser shows) panel is as the future development new trend of liquid crystal panel, and it is very responsive to materials such as steam and oxygen, so its encapsulation condition is harsh.
In the prior art, the packaging technology of oled panel is to adopt the method for laser baking to make the adhesive curing of envelope frame behind the encapsulating.The temperature of laser curing reaches 1000 ℃ even higher.Yet, seal the coating position of frame glue and the position of arranging of drive electrode and partially overlap, if envelope frame glue and drive electrode directly contact the phenomenon that peel off the position of the self-driven electrode of very easily generation envelope frame glue in the solidification process.
The utility model content
The technical matters that the utility model mainly solves provides a kind of array base palte and display device of improving envelope frame effect.
For solving the problems of the technologies described above, the technical scheme that the utility model adopts is: a kind of array base palte is provided, comprise substrate, drive electrode, first electric capacity, source electrode, drain electrode and first dielectric layer, first electric capacity comprises first capacitance electrode and second capacitance electrode, source electrode, drain electrode, drive electrode and first capacitance electrode are formed on the substrate, first dielectric layer covers source electrode, drain electrode, drive electrode and first capacitance electrode, first dielectric layer comprises the first area that covers first capacitance electrode and the second area that covers drive electrode, the thickness of second area is greater than the thickness of first area, second area is used for forming the glass melten gel thereon, and second capacitance electrode is formed on the first area.
Wherein, the thickness of first area is 200 ~ 1000 dusts, and the thickness of second area is 1000 ~ 8000 dusts.
Wherein, array base palte further comprises pixel electrode, organic material layer and escapement, pixel electrode is formed on first dielectric layer and connects source electrode, organic material layer is positioned on first dielectric layer and covers second battery lead plate, pixel electrode exposes organic material layer, and escapement protrudes setting on organic material layer.
Wherein, second capacitance electrode is metal material or transparent conductive material.
Wherein, array base palte further comprises second dielectric layer, semiconductor layer, the 3rd dielectric layer, grid, the 4th dielectric layer and second electric capacity, second electric capacity comprises the 3rd capacitance electrode and the 4th capacitance electrode, second dielectric layer is formed on the substrate, semiconductor layer and the 3rd capacitance electrode are between second dielectric layer and the 3rd dielectric layer, grid and the 4th capacitance electrode are between the 3rd dielectric layer and the 4th dielectric layer, and source electrode all is connected with semiconductor layer with grid.
For solving the problems of the technologies described above, another technical scheme that the utility model adopts is: a kind of display device is provided, and display device comprises array base palte, color membrane substrates and the glue frame that is enclosed by the glass melten gel; The glue frame is between array base palte and color membrane substrates; Array base palte comprises substrate, drive electrode, first electric capacity, source electrode, drain electrode and first dielectric layer, first electric capacity comprises first capacitance electrode and second capacitance electrode, source electrode, drain electrode, drive electrode and first capacitance electrode are formed on the substrate, first dielectric layer covers source electrode, drain electrode, drive electrode and first capacitance electrode, first dielectric layer comprises the first area that covers first capacitance electrode and the second area that covers drive electrode, the thickness of second area is greater than the thickness of first area, second area is used for forming the glass melten gel thereon, and second capacitance electrode is formed on the first area.
Wherein, the thickness of first area is 200 ~ 1000 dusts, and the thickness of second area is 1000 ~ 8000 dusts.
Wherein, array base palte further comprises pixel electrode, organic material layer and escapement, pixel electrode is formed on first dielectric layer and connects source electrode, organic material layer is positioned on first dielectric layer and covers second battery lead plate, pixel electrode exposes organic material layer, and escapement protrudes setting on organic material layer.
Wherein, second capacitance electrode is metal material or transparent conductive material.
Wherein, array base palte further comprises second dielectric layer, semiconductor layer, the 3rd dielectric layer, grid, the 4th dielectric layer and second electric capacity, second electric capacity comprises the 3rd capacitance electrode and the 4th capacitance electrode, second dielectric layer is formed on the substrate, semiconductor layer and the 3rd capacitance electrode are between second dielectric layer and the 3rd dielectric layer, grid and the 4th capacitance electrode are between the 3rd dielectric layer and the 4th dielectric layer, and source electrode all is connected with semiconductor layer with grid.
The beneficial effects of the utility model are: the situation that is different from prior art, first dielectric layer of the utility model array base palte comprises the first area between first capacitance electrode, second capacitance electrode and covers the second area of drive electrode that the thickness of second area is greater than the Thickness Design of first area; Thereby on the basis of the magnitude of the stored charge that ensures first electric capacity, avoid taking place directly contacting the phenomenon that the glass melten gel in the envelope frame technology is peeled off the glass melten gel because of drive electrode, further, the thickness of the second area of drive electrode correspondence is thicker, therefore seals the envelope frame better effects if in the frame technology.
Description of drawings
Fig. 1 is that the part master of the utility model array base palte looks synoptic diagram;
Fig. 2 is that this array base palte shown in Figure 1 is applied to the schematic top plan view in the display device;
Fig. 3 is that the master of the regional A correspondence of display device shown in Figure 2 looks synoptic diagram;
Fig. 4 is the process flow diagram of the manufacture method of the utility model array base palte.
Embodiment
Consult Fig. 1 and Fig. 2, the utility model array base palte comprises substrate 1, drive electrode 2, first electric capacity 3, TFT layer (not indicating), first dielectric layer 51, pixel electrode 6, organic material layer 7 and escapement 8.First electric capacity 3 comprises first capacitance electrode 31 and second capacitance electrode 32.
The TFT layer comprises second dielectric layer 52, semiconductor layer 43, the 3rd dielectric layer 53, grid 44, the 4th dielectric layer 54, source electrode 41, drain electrode 42 and second electric capacity 9.Second electric capacity 9 comprises the 3rd capacitance electrode 91 and the 4th capacitance electrode 92.
Second dielectric layer 52 is formed on the substrate 1.Semiconductor layer 43 and the 3rd capacitance electrode 91 are formed on the side away from substrate 1 of second dielectric layer 52.The 3rd capacitance electrode 91 can be made by different processing procedures successively with semiconductor layer 43, perhaps generates simultaneously in same processing procedure.When the 3rd capacitance electrode 91 and semiconductor layer 43 were formed by same processing procedure, the two was same material, that is, the 3rd capacitance electrode 91 also is semiconductor material.
The 3rd dielectric layer 53 is formed on second dielectric layer 52.The 3rd dielectric layer 53 covers semiconductor layer 43 and the 3rd capacitance electrode 91, makes the 3rd capacitance electrode 91 and semiconductor layer 43 between second dielectric layer 52 and the 3rd dielectric layer 53.
Form second capacitance electrode 32 on the first area 511 of first dielectric layer 51.First capacitance electrode 31, second capacitance electrode 32 and first dielectric layer 51 between the two form first electric capacity 3.Less because of the thickness of first dielectric layer 51 between first capacitance electrode 31 and second capacitance electrode 32, make first electric capacity 3 can access higher magnitude of the stored charge, to satisfy user demand.
Please in the lump with reference to Fig. 2 and Fig. 3, the first area 511 of first dielectric layer 51 covers drive electrode 2, and first area 511 is used for forming glass melten gel 22 thereon, so that array base palte 100 and color membrane substrates 21 are encapsulated.
In the packaging technology of glass melten gel 22, at first, the glass melten gel is poured on the adhesive area (not indicating) of array base palte 100 peripheries, this adhesive area and second area 512 are overlapped; Then, the glass melten gel is solidified the method that adopts the laser baking.In the utility model, between the two, form good transition because thicker first dielectric layer, 51, the first dielectric layers 51 are set between drive electrode 2 and the glass melten gel 22, make glass melten gel 22 obtain good cure package effect.
Further, pixel electrode 6 is formed on first dielectric layer 51.Pixel electrode 6 is connected to source electrode 41.Pixel electrode 6 is formed simultaneously by identical processing procedure with second capacitance electrode 32 or is successively formed by different processing procedures.Preferably, pixel electrode 6 adopts identical processing procedure to form simultaneously with second capacitance electrode 32, and the two all adopts transparent conductive material or silvery journey.When the two adopted different processing procedure, second capacitance electrode 32 also can adopt other conductive material.
Organic material layer 7 is formed on first dielectric layer 51.Organic material layer 7 covers second battery lead plate and pixel electrode 6 is exposed out.Escapement 8 protrudes on organic material layer 7 at interval and arranges, with the color membrane substrates 21 of support with array base palte 100 mutual assemblings.
Organic material layer 7 area is set less than first dielectric layer 51.At least do not lay organic material layer 7 on the frame Jiao Qu of array base palte 100, make 22 perfusions of glass melten gel to first dielectric layer 51 on the top layer that is arranged at frame Jiao Qu.
In the utility model, first dielectric layer 51, second dielectric layer 52, the 3rd dielectric layer 53 and the 4th dielectric layer 54 are silicon nitride or silica material.In the practical application, the material of above-mentioned dielectric layer is not limited by above-mentioned material.And, can adopt identical materials between the adjacent dielectric layer, can also select different materials for use.
Be different from prior art, first dielectric layer 51 of the utility model array base palte 100 comprises the first area 511 between first capacitance electrode 31, second capacitance electrode 32 and covers the second area 512 of drive electrode 2 that the thickness of second area 512 is greater than the Thickness Design of first area 511; Thereby on the basis of the magnitude of the stored charge that ensures first electric capacity 3, avoid taking place directly contacting the phenomenon that the glass melten gel 22 in the envelope frame technologies is peeled off glass melten gel 22 because of drive electrode 2, further, the thickness of the second area 512 of drive electrode 2 correspondences is thicker, therefore, the envelope frame better effects if in the envelope frame technology.
Please refer to Fig. 2, the utility model further provides a kind of display device, and display device comprises the glue frame that array base palte 100, color membrane substrates 21, FPC20 and the glass melten gel 22 described in the previous embodiment enclose.The glue frame is between array base palte 100 and color membrane substrates 21.FPC20 is connected to drive electrode 2.
Please refer to Fig. 4, the utility model further provides a kind of manufacture method of array base palte.This manufacture method comprises:
S10 provides a substrate 1.
Substrate 1 can be the light-passing board of glass substrate or other materials.
S20 forms source electrode 41, drain electrode 42, drive electrode 2 and first capacitance electrode 31 on substrate 1.
S30 forms first dielectric layer 51.First dielectric layer 51 covers source electrode 41, drain electrode 42, drive electrode 2 and first capacitance electrode 31.First dielectric layer 51 comprises the first area 511 that covers first capacitance electrode 31 and the second area 512 that covers drive electrode 2.The thickness of second area 512 is greater than the thickness of first area 511.Second area 512 is used for forming glass melten gel 22 thereon.
S40 forms second capacitance electrode 32 on the first area 511 of first dielectric layer 51.Second capacitance electrode 32, first capacitance electrode 31 and first dielectric layer 51 therebetween form first electric capacity 3.
Specifically, step S20 further comprises: form second dielectric layer 52 on substrate 1.On second dielectric layer 52, form semiconductor layer 43 and the 3rd capacitance electrode 91.Forming the 3rd dielectric layer 53, the three dielectric layers 53 is formed on second dielectric layer 52 and covering semiconductor layer 43 and the 3rd capacitance electrode 91.On the 3rd dielectric layer 53, form grid 44 and the 4th capacitance electrode 92, grid 44 and semiconductor layer 43 over against, the 4th capacitance electrode 92, the 3rd capacitance electrode 91 and the 3rd dielectric layer therebetween form second electric capacity 9.Forming the 4th dielectric layer 54, the four dielectric layers 54 is formed on the 3rd dielectric layer 53 and cover gate 44 and the 4th capacitance electrode 92.Form source electrode 41, drain electrode 42, first capacitance electrode 31 and drive electrode 2 on the 4th dielectric layer 92, source electrode 41 and drain electrode 42 all are connected to semiconductor layer 43.
Among the step S30, preferably, the thickness of first area 511 is 200 ~ 1000 dusts, and the thickness of second area 512 is 1000 ~ 8000 dusts.
This manufacture method further comprises after step S30: form pixel electrode 6 on first dielectric layer 51, pixel electrode 6 is connected to source electrode 41.The step that forms pixel electrode 6 can be finished synchronously with step S40 or successively finish.When pixel electrode 6 and second capacitance electrode 32 selected same processing procedure to form synchronously, the material of the two was identical, namely all selects transparent electrode material or silver.
After pixel electrode 6 is made, on first dielectric layer 51, form organic material layer 7.Organic material layer 7 covers second capacitance electrode 32.Pixel electrode 6 exposes organic material layer 7.At last, on organic material layer 7, protrude some escapements 8 be set, escapement 8 in order to support display device with the fit color membrane substrates 21 of assembling of array base palte 100.
The above only is embodiment of the present utility model; be not so limit claim of the present utility model; every equivalent structure or equivalent flow process conversion that utilizes the utility model instructions and accompanying drawing content to do; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present utility model.
Claims (10)
1. array base palte, it is characterized in that, described array base palte comprises substrate, drive electrode, first electric capacity, source electrode, drain electrode and first dielectric layer, described first electric capacity comprises first capacitance electrode and second capacitance electrode, described source electrode, described drain electrode, described drive electrode and described first capacitance electrode are formed on the described substrate, described first dielectric layer covers described source electrode, described drain electrode, described drive electrode and described first capacitance electrode, described first dielectric layer comprises the first area that covers described first capacitance electrode and the second area that covers described drive electrode, the thickness of described second area is greater than the thickness of described first area, described second area is used for forming the glass melten gel thereon, and described second capacitance electrode is formed on the described first area.
2. array base palte according to claim 1 is characterized in that, the thickness of described first area is 200 ~ 1000 dusts, and the thickness of described second area is 1000 ~ 8000 dusts.
3. array base palte according to claim 1, it is characterized in that, described array base palte further comprises pixel electrode, organic material layer and escapement, described pixel electrode is formed on described first dielectric layer and connects described source electrode, described organic material layer is positioned on described first dielectric layer and covers described second battery lead plate, described pixel electrode exposes described organic material layer, and described escapement protrudes setting on described organic material layer.
4. array base palte according to claim 1 is characterized in that, described second capacitance electrode is metal material or transparent conductive material.
5. array base palte according to claim 4, it is characterized in that, described array base palte further comprises second dielectric layer, semiconductor layer, the 3rd dielectric layer, grid, the 4th dielectric layer and second electric capacity, described second electric capacity comprises the 3rd capacitance electrode and the 4th capacitance electrode, described second dielectric layer is formed on the described substrate, described semiconductor layer and described the 3rd capacitance electrode are between described second dielectric layer and described the 3rd dielectric layer, described grid and described the 4th capacitance electrode are between described the 3rd dielectric layer and described the 4th dielectric layer, and described source electrode all is connected with described semiconductor layer with described grid.
6. a display device is characterized in that, described display device comprises array base palte, color membrane substrates and the glue frame that is enclosed by the glass melten gel; The glue frame is between array base palte and color membrane substrates; Described array base palte comprises substrate, drive electrode, first electric capacity, source electrode, drain electrode and first dielectric layer, described first electric capacity comprises first capacitance electrode and second capacitance electrode, described source electrode, described drain electrode, described drive electrode and described first capacitance electrode are formed on the described substrate, described first dielectric layer covers described source electrode, described drain electrode, described drive electrode and described first capacitance electrode, described first dielectric layer comprises the first area that covers described first capacitance electrode and the second area that covers described drive electrode, the thickness of described second area is greater than the thickness of described first area, described second area is used for forming described glass melten gel thereon, and described second capacitance electrode is formed on the described first area.
7. display device according to claim 6 is characterized in that, the thickness of described first area is 200 ~ 1000 dusts, and the thickness of described second area is 1000 ~ 8000 dusts.
8. display device according to claim 6, it is characterized in that, described array base palte further comprises pixel electrode, organic material layer and escapement, described pixel electrode is formed on described first dielectric layer and connects described source electrode, described organic material layer is positioned on described first dielectric layer and covers described second battery lead plate, described pixel electrode exposes described organic material layer, and described escapement protrudes setting on described organic material layer.
9. display device according to claim 6 is characterized in that, described second capacitance electrode is metal material or transparent conductive material.
10. display device according to claim 9, it is characterized in that, described array base palte further comprises second dielectric layer, semiconductor layer, the 3rd dielectric layer, grid, the 4th dielectric layer and second electric capacity, described second electric capacity comprises the 3rd capacitance electrode and the 4th capacitance electrode, described second dielectric layer is formed on the described substrate, described semiconductor layer and described the 3rd capacitance electrode are between described second dielectric layer and described the 3rd dielectric layer, described grid and described the 4th capacitance electrode are between described the 3rd dielectric layer and described the 4th dielectric layer, and described source electrode all is connected with described semiconductor layer with described grid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320067813 CN203178636U (en) | 2013-02-05 | 2013-02-05 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320067813 CN203178636U (en) | 2013-02-05 | 2013-02-05 | Array substrate and display device |
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| CN203178636U true CN203178636U (en) | 2013-09-04 |
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| CN 201320067813 Withdrawn - After Issue CN203178636U (en) | 2013-02-05 | 2013-02-05 | Array substrate and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137557A (en) * | 2013-02-05 | 2013-06-05 | 深圳市华星光电技术有限公司 | Array substrate and display unit and manufacturing method of array substrate |
| CN109416897A (en) * | 2016-07-29 | 2019-03-01 | 索尼公司 | Display device, display device manufacturing method and electronic equipment |
-
2013
- 2013-02-05 CN CN 201320067813 patent/CN203178636U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137557A (en) * | 2013-02-05 | 2013-06-05 | 深圳市华星光电技术有限公司 | Array substrate and display unit and manufacturing method of array substrate |
| WO2014121525A1 (en) * | 2013-02-05 | 2014-08-14 | 深圳市华星光电技术有限公司 | Array substrate, display device and manufacturing method for array substrate |
| GB2524212A (en) * | 2013-02-05 | 2015-09-16 | Shenzhen China Star Optoelect | Array substrate, display device and manufacturing method for array substrate |
| CN109416897A (en) * | 2016-07-29 | 2019-03-01 | 索尼公司 | Display device, display device manufacturing method and electronic equipment |
| CN109416897B (en) * | 2016-07-29 | 2021-07-02 | 索尼公司 | Display device, display device manufacturing method, and electronic device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20130904 Effective date of abandoning: 20150218 |
|
| RGAV | Abandon patent right to avoid regrant |