CN203133273U - High-frequency surface wave radar data collecting and processing apparatus based on CPCI bus - Google Patents
High-frequency surface wave radar data collecting and processing apparatus based on CPCI bus Download PDFInfo
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Abstract
本实用新型涉及基于CPCI总线的高频地波雷达数据采集和处理装置。该装置采用高分辨率、低抖动ADC实现模数转换，利用大规模FPGA或PDC实现数字下变频，使用大容量DDR2实现数据高速缓存，以DSP作为控制核心，同时利用DSP强大的数字信号处理能力实现脉冲压缩、距离抽样等雷达信号处理，使用CPLD实现FPGAFPP模式程序加载，使用PCI桥接芯片，采用DriverStudio内核驱动编程技术。优点：能将多块板卡同时挂在CPCI总线上便于通道扩展。信号处理能力强，能实现多通道实时信号处理。可重配置性强，能应用于其它算法的实现。具有大容量的DDR2，能实现大量数据缓存。FPGA程序加载灵活。
The utility model relates to a high-frequency ground wave radar data acquisition and processing device based on a CPCI bus. The device uses high-resolution, low-jitter ADC to realize analog-to-digital conversion, uses large-scale FPGA or PDC to realize digital down-conversion, uses large-capacity DDR2 to realize data cache, uses DSP as the control core, and utilizes DSP's powerful digital signal processing capabilities Realize radar signal processing such as pulse compression and distance sampling, use CPLD to realize FPGAFPP mode program loading, use PCI bridge chip, and use DriverStudio kernel driver programming technology. Advantages: multiple boards can be hung on the CPCI bus at the same time to facilitate channel expansion. The signal processing ability is strong, and it can realize multi-channel real-time signal processing. Strong reconfigurability, can be applied to the realization of other algorithms. DDR2 with large capacity can realize a large amount of data cache. FPGA program loading is flexible.
Description
Technical field
The utility model relates to digital radar receiver field, relates in particular to a kind of high-frequency ground wave radar data acquisition and processing (DAP) device based on cpci bus.
Background technology
High-frequency ground wave radar is a kind of ocean remote sensing equipment that can continuous monitoring large tracts of land marine site.The less characteristic of energy attenuation when it utilizes the vertical polarization frequency electromagnetic waves along high conduction seawater surface diffraction propagation, supervision and the location of realizing marine environment state (as drive marine mathematic(al) parameters such as wind, wave, streams), marine low speed are moved hard goal etc.Compare with other hydrospace detection equipment, high-frequency ground wave radar is used for marine environmental monitoring and has remarkable advantages: coverage is big, detection accuracy is high, cost is appropriate, operating cost is cheap, real-time is good, be not subjected to weather and maritime meteorology condition effect, can all weather operations, and can detect marine site outside the sighting distance, be the existing irreplaceable gordian technique of ocean remote sensing equipment, be considered to optimal EEZ monitoring equipment.
A system for high-frequency earth wave radar comprises transmitter, receiver, frequency synthesizer etc.Wherein radar receiver is one of core component of this system, its major function be to the echoed signal that receives amplify, filtering, frequency conversion and other digitized processing, suppress various interference, clutter and internal system noise from the outside simultaneously, obtain target information as much as possible, be used for further signal processing and data and handle.Therefore, the quality of radar receiver performance has directly determined the precision of aims of systems parameter extraction.
Tradition high-frequency ground wave radar receiver great majority adopt the if sampling structure, be that echoed signal that radar antenna receives is carried out once through AFE (analog front end) or once with up-conversion, radiofrequency signal is become intermediate-freuqncy signal, carry out bandpass sampling and digital signal processing at Mid Frequency.Though this structure is less demanding to the ADC sampling rate of digital if receiver, because AFE (analog front end) will be carried out repeatedly frequency conversion, therefore making whole receiver system structure more complicated has increased the internal system noise simultaneously.
Along with the develop rapidly of electronic technology and constantly progressive, the appearance of high-speed wideband ADC, digital down converter and high-performance digital signal processor makes that utilizing software radio to make up a general hardware platform is achieved.With the as close as possible radio-frequency antenna of wideband A/D, so that with the digitizing as far as possible early of the simulating signal that receives, realize the various functions of receiver by software as far as possible, make that receiver is more flexible, anti-interference is stronger, obtain more echo information, improve radar performance.
Summary of the invention
In order to utilize software radio to make up a general hardware platform, the utility model proposes a kind of high-frequency ground wave radar data acquisition and processing (DAP) device based on cpci bus.This device adopts the radio frequency Direct Sampling, realizes that multi-channel data is real-time, handles flexibly.
For achieving the above object, the utility model adopts following technical scheme:
A kind of high-frequency ground wave radar data acquisition and processing (DAP) device based on cpci bus is characterized in that described device comprises: the analog to digital conversion circuit that includes four high resolving power, low jitter ADC module; The Digital Down Convert circuit that includes a large-scale F PGA chip and a programmable digital down converter PDC module; The data caching circuit that includes four DDR2 modules; Include a dsp chip and be used for to realize parameter configuration and the governor circuit of Radar Signal Processing; Include the CPLD configuration module and be used for the configuration circuit that realization FPGA program loads; Include the pci interface circuit of PCI bridging chip; Analog-digital conversion circuit as described, governor circuit, data caching circuit and pci interface circuit all link to each other with the Digital Down Convert circuit, and configuration circuit all links to each other with the pci interface circuit with the Digital Down Convert circuit.
At the above-mentioned high-frequency ground wave radar data acquisition and processing (DAP) device based on cpci bus, described device comprises two groups of analog to digital conversion circuits, Digital Down Convert circuit, data caching circuit and governor circuit; Described two groups of Digital Down Convert circuit and governor circuit all interconnect.
At the above-mentioned high-frequency ground wave radar data acquisition and processing (DAP) device based on cpci bus, two groups of analog to digital conversion circuits comprise eight ADC modules, and the sampling output terminal of eight ADC modules links to each other with digital down converter PDC module with fpga chip simultaneously.
At the above-mentioned high-frequency ground wave radar data acquisition and processing (DAP) device based on cpci bus, two groups of Digital Down Convert circuit comprise two fpga chips and two digital down converter PDC modules, and fpga chip inside comprises AD data latch module, Digital Down Converter Module, ISL5216 interface module, DDR2 interface module, data selection module, dsp interface module, pci interface module; Digital down converter PDC module links to each other with AD data latch module, and every group digital down converter PDC module output terminal links to each other with the fpga chip of this group.
At the above-mentioned high-frequency ground wave radar data acquisition and processing (DAP) device based on cpci bus, two groups of data caching circuits comprise eight DDR2 modules, per four DDR2 modules are formed the 4Gbit data buffer memory of 32 bit data bus, and address, the DCB of four DDR2 modules in every group link to each other with the fpga chip of this group.
At the above-mentioned high-frequency ground wave radar data acquisition and processing (DAP) device based on cpci bus, two groups of governor circuits comprise two dsp chips, the address of every group of dsp chip, data and control signal link to each other with the fpga chip of this group, and the data bus of every group of dsp chip links to each other with the digital down converter PDC module of this group by data buffering simultaneously.
At the above-mentioned high-frequency ground wave radar data acquisition and processing (DAP) device based on cpci bus, described configuration circuit comprises the CPLD configuration module, and this chip comprises the FPP dispensing unit.
At the above-mentioned high-frequency ground wave radar data acquisition and processing (DAP) device based on cpci bus, described pci interface circuit comprises the PCI bridging chip, the PCI port of this PCI bridging chip links to each other with cpci bus, and the LOCAL port of PCI bridging chip all links to each other with the CPLD configuration module with fpga chip.
The utlity model has following advantage and good effect: 1, have the CPCI interface of standard, the polylith integrated circuit board can be hung over simultaneously and be convenient to the passage expansion on the cpci bus; 2, signal handling capacity is strong, can realize the hyperchannel real time signal processing; 3, reconfigurable property is strong, can be applied to the realization of other algorithm; 4, have jumbo DDR2, can realize the mass data buffer memory; 5, the program of fpga chip loads flexibly.
Description of drawings
Fig. 1 is system chart of the present utility model.
Fig. 2 is fpga chip internal data flow diagram of the present utility model.
Fig. 3 is fpga chip internal digital down conversion module work synoptic diagram of the present utility model.
Fig. 4 is the inner pci interface module of fpga chip of the present utility model work synoptic diagram.
Fig. 5 is the inner FPP dispensing unit of CPLD configuration module of the present utility model work synoptic diagram.
Fig. 6 is that the pulse compression of dsp chip of the present utility model realizes theory diagram.
Embodiment
The utility model is described in further detail by reference to the accompanying drawings with specific embodiment below.
Referring to Fig. 1, the utility model comprises the analog to digital conversion circuit based on 8 high resolving power, low jitter ADC module, Digital Down Convert circuit based on 2 large-scale F PGA chips and 2 programmable digital down converter PDC modules, data caching circuit based on 8 DDR2 modules, the governor circuit that is used for realizing parameter configuration and Radar Signal Processing based on 2 dsp chips, based on the configuration circuit that is used for realizing the loading of fpga chip program of CPLD configuration module, based on the pci interface circuit of PCI bridging chip.
In the present embodiment, the ADC module is selected the LTC2217 of LINEAR TECHNOLOGY company for use, and this chip sample frequency can reach 105MSPS, average jitter 85 femtoseconds, and resolution is 16, can be LVDS output or CMOS output.
In the present embodiment, programmable digital down converter PDC module is selected the ISL5216 of INTERSIL company for use, and this chip can receive up to the input of the AD data of 95MSPS, inner integrated four programmable down coversion passages independently.Before ISL5216 effectively works, need dispose it, wherein configuration parameter comprises input format parameter, NCO parameter, CIC parameter and FIR parameter etc., these configuration parameters can generate by the tool software that INTERSIL company provides.The parameter configuration files that DSP import to generate also utilizes external memory interface visit ISL5216 can finish configuration to ISL5216.
In the present embodiment, fpga chip is selected the EP3SL1501152 of Atlera company for use, and fpga chip inside comprises AD data latch module, Digital Down Converter Module, ISL5216 interface module, DDR2 interface module, data selection module, dsp interface module, pci interface module.AD data latch module links to each other with the AD data, is used for latching the AD data; The ISL5216 interface module links to each other with the ISL5216 synchronous serial interface, is used for receiving the data of handling through the ISL5216 Digital Down Convert; The DDR2 interface module links to each other with DDR2 address, DCB, is used for the control of DDR2 read-write sequence; The dsp interface module links to each other with DSP address, DCB, is used for realizing the data buffer memory FIFO of DSP visit FPGA inside; The pci interface module links to each other with PCI9656 LOCAL port, links to each other with DSP address, DCB simultaneously, is used for the sequential control of host access DSP.Two FPGA are used for communication in the plate by the interconnection of IO interface.
In the present embodiment, dsp chip is selected the TS201 of ADI company for use, and this chip dominant frequency has DRAM in the 24Mbit sheet, 64bit data bus, 4 full-duplex link mouths up to 600MHz.Two TS201 interconnect by link port, are used for exchanges data in the plate.TS201 is mainly used in Radar Signal Processing except being used for basic control and data transmission, comprises pulse compression, distance sampling etc.
In the present embodiment, the PCI bridging chip is selected the PCI9656 of PLX company for use, and this chip is supported 66M, 64 pci bus interfaces and 66M, 32 LOCAL bus interface, supports plurality of data transmission modes, comprises holotype, subordinate pattern and DMA pattern.PCI drives programming and adopts the DriverStudio kernel to drive programming technique, drives programming guide based on WDM and finishes, and supports the data transmission of subordinate pattern and DMA pattern.
Fig. 2 is fpga chip internal data flow diagram.The ADC sampled data latchs through AD data latch module, and the data after latching are input to Digital Down Converter Module and carry out The digital quadrature transformation and filtering extraction, and the I/Q data of gained deposit FIFO in; The ADC sampled data also can be handled by its synchronous serial interface output through the ISL5216 Digital Down Convert, and the I/Q data of output deposit FIFO in through the ISL5216 interface module; Data select module to dispose according to DSP, can select the ADC sampled data, or through the data of FPGA Digital Down Convert, or through the data of ISL5216 Digital Down Convert; Data select module output data to be transferred to DSP by the dsp interface module, or are transferred to DDR2 through the DDR2 interface module; DSP can be by the data among DDR2 interface module and the dsp interface module accesses DDR2.
Fig. 3 is fpga chip internal digital down conversion module work synoptic diagram.Be divided into two-way through AD data latched data, one tunnel cosine signal that produces with digital controlled oscillator NCO multiplies each other, and the sinusoidal signal of another road and NCO generation multiplies each other.Data after multiplying each other are through intercepting difference input integral cascade comb filter CIC, and the data behind the filtering extraction are imported the FIR wave filter respectively through intercepting, and the I/Q base band data behind the FIR wave filter shaping filter deposits FIFO in through intercepting.The intercepting figure place has been taken all factors into consideration dynamic range of signals and FPGA resource, has guaranteed that intercepting is high-order.Wherein, NCO, multiplier, CIC, FIR finish by the IP kernel that Atlera company provides, and the CIC extracting multiple is 160, and progression is that cut-off frequecy of passband and the stopband cutoff frequency of 5, FIR wave filter arranges according to sampled signal bandwidth and FPGA resource.
Fig. 4 is the inner pci interface module of fpga chip work synoptic diagram.When main frame is visited DSP by pci bus, PCI9656 LOCAL end produces address signal LA[31..2], data-signal LD[31..0], application visit LOCAL bus signals LHOLD, bus access start signal ADS, read-write LW/R, bus access end signal BLAST, the inner pci interface module of FPGA produces application visit LOCAL bus useful signal LHOLDA according to input and gives PCI9656, host bus request signal HBR gives DSP, DSP receives the HBR signal and produces the pci interface module that host bus grant signal HBG gives FPGA inside, this module produces address signal TS_ADDR[31..0], data-signal TS_D[31..0], read signal TS_RD or write signal TS_WRL give DSP, DSP produces the pci interface module that handshake ACK gives FPGA inside, and this module produces read-write simultaneously and finishes signal READY to PCI9656.
Fig. 5 is the inner FPP dispensing unit of CPLD configuration module work synoptic diagram.When main frame is downloaded the FPGA binary program by pci bus, PCI9656 LOCAL end produces address signal LA[31..2], data-signal LD[31..0], application visit LOCAL bus signals LHOLD, bus access start signal ADS, read-write LW/R, bus access end signal BLAST, the inner FPP dispensing unit of CPLD produces application visit LOCAL bus useful signal LHOLDA according to input and gives PCI9656, produce beginning configuration signal FPGA_CONFIG, configurable clock generator signal FPGA_DCLK, configuration data signals FPGA_DATA[7..0], signal FPAG_CONF_DONE is finished in the status signal FPGA_STATUS and the configuration that receive the FPGA feedback simultaneously, after finishing the configuration of an eight bit data, the output read-write is finished signal READY and is given PCI9656.
Fig. 6 is that the dsp chip pulse compression realizes theory diagram.S (n) is the complex signal of radar return after ADC sampling and Digital Down Convert, and it is counted and is M; H (n) is the radar matched sample, and it is counted and is N, wherein L=M+N-1.Echo data and matched sample all multiply each other behind zero padding FFT, are IFFT again and get final product to such an extent that y (n) is exported in matched filtering.The Visual DSP++ Integrated Development Environment that the DSP exploitation adopts ADI company to provide, this instrument comprises the library file of realizing FFT and IFFT.
Above disclosed only is preferred embodiment of the present utility model, can not limit the interest field of the utility model certainly with this, and therefore the equivalence of doing according to the utility model claim changes, and still belongs to protection domain of the present utility model.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103472438A (en) * | 2013-09-24 | 2013-12-25 | 上海无线电设备研究所 | Multichannel signal pulse pressure time division multiplexing device |
| CN104794091A (en) * | 2014-01-22 | 2015-07-22 | 北京浩正泰吉科技有限公司 | Communication card based on CPCI interface |
| CN107465430A (en) * | 2017-07-03 | 2017-12-12 | 北京无线电测量研究所 | The method and system of FM signal parameter monitoring based on cpci bus |
| CN108181497A (en) * | 2017-12-04 | 2018-06-19 | 北京控制与电子技术研究所 | A kind of measuring method of the multichannel AC voltage effective value based on cpci bus |
| CN110907693A (en) * | 2019-12-10 | 2020-03-24 | 航天新长征大道科技有限公司 | Compact peripheral interconnection bus board card |
| CN112305961A (en) * | 2020-10-19 | 2021-02-02 | 武汉大学 | New Signal Detection and Acquisition Equipment |
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2013
- 2013-03-15 CN CN 201320118589 patent/CN203133273U/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103472438A (en) * | 2013-09-24 | 2013-12-25 | 上海无线电设备研究所 | Multichannel signal pulse pressure time division multiplexing device |
| CN104794091A (en) * | 2014-01-22 | 2015-07-22 | 北京浩正泰吉科技有限公司 | Communication card based on CPCI interface |
| CN104794091B (en) * | 2014-01-22 | 2018-01-12 | 北京浩正泰吉科技有限公司 | A kind of communication card based on CPCI interfaces |
| CN107465430A (en) * | 2017-07-03 | 2017-12-12 | 北京无线电测量研究所 | The method and system of FM signal parameter monitoring based on cpci bus |
| CN107465430B (en) * | 2017-07-03 | 2021-04-02 | 北京无线电测量研究所 | CPCI bus-based frequency modulation signal parameter monitoring method and system |
| CN108181497A (en) * | 2017-12-04 | 2018-06-19 | 北京控制与电子技术研究所 | A kind of measuring method of the multichannel AC voltage effective value based on cpci bus |
| CN110907693A (en) * | 2019-12-10 | 2020-03-24 | 航天新长征大道科技有限公司 | Compact peripheral interconnection bus board card |
| CN110907693B (en) * | 2019-12-10 | 2022-02-01 | 航天新长征大道科技有限公司 | Compact peripheral interconnection bus board card |
| CN112305961A (en) * | 2020-10-19 | 2021-02-02 | 武汉大学 | New Signal Detection and Acquisition Equipment |
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