CN203071910U - Sinusoidal signal simulation device - Google Patents
Sinusoidal signal simulation device Download PDFInfo
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- CN203071910U CN203071910U CN 201220742435 CN201220742435U CN203071910U CN 203071910 U CN203071910 U CN 203071910U CN 201220742435 CN201220742435 CN 201220742435 CN 201220742435 U CN201220742435 U CN 201220742435U CN 203071910 U CN203071910 U CN 203071910U
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Abstract
The utility model discloses a sinusoidal signal simulation device, wherein two ends of the sinusoidal signal simulation device are connected with an upper computer and a test object respectively. The sinusoidal signal simulation device comprises an input module, a clock source, a controller, a digital-to-analog converter and a filter, wherein the controller is connected with the input module, the clock source and the digital-to-analog converter; the filter is connected with the digital-to-analog converter; the input module is used for receiving commands from the upper computer; waveform date is stored inside the controller; the controller analyzes the frequency, the amplitude, the phase and bias parameters of sinusoidal signals according to commands issued by the input module, extracts corresponding data in a circulation manner according to the parameters, and adjusts the extracted data, thereby realizing adjustment on the value of amplitude and the bias. Data outputted by the controller is converted into analog signals by the digital-to-analog converter and filtered by the filter to filter out burrs, and smooth multipath synchronous sinusoidal signals whose frequency, amplitude, phase and bias parameter all can be configured are outputted.
Description
Technical field
The utility model relates to the signal of telecommunication and produces and processing technology field, particularly a kind of sinusoidal signal analogue means.
Background technology
Designing and developing in the process of kinetic control system, for understand system parameter variations the consequence that may cause, often by in the selection hardware-in-loop simulation system control system coherent signal being simulated, carry out a large amount of experiments repeatedly with lower cost, to obtain sufficient amount and data Quality, provide foundation for designing or testing.Specifically, the analog sinus signals that produces with analogue system replaces actual measuring light signal, analog sinus signals is fed back to tested object, thereby whether the response of verification test object meets the requirements.
In analogue system, frequency represents the of ac part of measuring light signal, and amplitude represents the power of light signal, and phase difference represents the time difference of a few bundle light signals, and biasing represents the size of the DC quantity of measuring light signal.For the accurate measuring light signal of analog control system, require sinusoidal signal generator can produce all adjustable sinusoidal signals of channelized frequencies, amplitude, phase place, biasing.For producing accurate sinusoidal signal, (Direct Digital Synthesis is called for short: DDS) to adopt the Direct Digital synthetic technology usually.A variety of DDS chips are arranged on the market, but these chips can only produce single frequency signal usually, what have can produce the two-way orthogonal sine at most, and does not have a kind ofly can produce all adjustable sinusoidal signals of channelized frequencies, phase place, amplitude synchronously.In addition, the DDS chip cost is higher, function singleness, and using value is not high in the hardware-in-loop simulation system.There is a kind of sinusoidal signal generator in the prior art, realized the sinusoidal signal that the multichannel synchronizing frequency is adjustable, phase place is adjustable and but the frequency integral multiple is regulated, but can't realize the adjusting of direct current biasing, and this sinusoidal signal generator needs to write Wave data with a controller to a memory inside, the hardware configuration complexity before each the use.In addition, general signal generator also can't produce all adjustable sinusoidal signals of each characteristic parameter.
Therefore, how to provide a kind of can produce synchronously channelized frequencies, phase place, amplitude all adjustable sinusoidal signal analogue means be the technical problem that those skilled in the art need to be resolved hurrily.
The utility model content
The utility model provides a kind of sinusoidal signal analogue means, can produce all adjustable sinusoidal signals of multichannel synchronizing frequency, phase place, amplitude and biasing.
For solving the problems of the technologies described above, the utility model provides a kind of sinusoidal signal analogue means, the two ends of described sinusoidal signal analogue means link to each other with tested object with host computer respectively, comprise: input module, the clock source, controller, digital/analog converter and filter, described controller respectively with described input module, clock source and digital/analog converter link to each other, described filter links to each other with described digital/analog converter, input module is used for receiving the configuration order of host computer, controller receives the configuration order of input module transmission, and produce corresponding configuration data according to configuration order, the realization configuration data is resolved, the Wave data storage, the extraction of Wave data and the conversion of data, data after the conversion are passed to digital/analog converter and transfer analog signal to, and carry out smothing filtering by filter, output to tested object.
As preferably, described controller comprises: the phase-locked loop that links to each other with described clock source, the interface module of Xiang Lianing, command analysis module, data processing module, data latch synchronization module and digital/analog converter control module successively, and described interface module links to each other with described input module, and described digital/analog converter control module links to each other with described digital/analog converter.
As preferably, described data processing module comprises data adjusting module, data extraction module and waveform data memory, wherein, with described command analysis module, data adjusting module, data latch synchronization module and waveform data memory links to each other, described data adjusting module also latchs synchronization module with described command analysis module with data respectively and links to each other described data extraction module respectively.
As preferably, described configuration data comprises the configuration data of sampling step-length, pulse daley value, amplitude, phase place, biasing, port number.
As preferably, described controller is field programmable gate array.
As preferably, described input module is optical-fibre communications module, USB communication module or RS232 communication module.
As preferably, described clock source is active crystal oscillator.
As preferably, described digital/analog converter is the digital/analog converter of four-way serial input.
As preferably, described filter is the RC filter.
Compared with prior art, the utlity model has following advantage:
1, the utility model can dispose frequency, amplitude, biasing and the phase place of needed sinusoidal signal flexibly according to the needs of test, and can keep between the multiple signals synchronously;
2, because Wave data is stored in the inside of controller, and need not to expand external memory storage, simplified the hardware of described sinusoidal signal analogue means;
3, output signal frequency can obtain by the clock signal frequency division to clock source output, and pulse daley value and sampling step-length are set, and frequency that namely can the flexible configuration sinusoidal signal need not outside DDS chip;
4, the amplitude adjustment of sinusoidal signal can realize by the multiplier in controller inside, can also realize the biasing of direct current by multiplier and adder, need not outside expander amplifier.
Description of drawings
Fig. 1 is the frame diagram of sinusoidal signal analogue means in the utility model one embodiment;
Fig. 2 is the block diagram of the utility model one embodiment middle controller;
Fig. 3 is the workflow diagram of sinusoidal signal analogue means in the utility model one embodiment.
Among the figure: 1-sinusoidal signal analogue means, 2-host computer, 3-tested object, 10-clock source, 20-input module, 30-controller, 301-phase-locked loop, 302-interface module, 303-command analysis module, 304-data processing module, 3041-data adjusting module, 3042-data extraction module, 3043-waveform data memory, 305-data latch synchronization module, 306-digital-to-analog conversion and control module, 40-digital/analog converter, 50-filter.
Embodiment
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, below in conjunction with accompanying drawing embodiment of the present utility model is described in detail.It should be noted that the utility model accompanying drawing all adopts the form of simplification and all uses non-ratio accurately, only in order to convenient, the purpose of aid illustration the utility model embodiment lucidly.
Please refer to Fig. 1, the utility model provides a kind of sinusoidal signal analogue means 1, and its two ends link to each other with tested object 3 with host computer 2 respectively.Preferable, described sinusoidal signal analogue means 1 comprises: input module 20, clock source 10, controller 30, digital/analog converter 40 and filter 50, described controller 30 links to each other with described input module 20, clock source 10 and digital/analog converter 40 respectively, and described filter 50 links to each other with described digital/analog converter 40.Particularly, described clock source 10 provides the stable clock signal for controller 30; Described input module 20 is used for receiving the configuration order of host computer 1, Wave data is stored in controller 30 inside, controller 30 produces the configuration data of corresponding sampling step-length, pulse daley value, amplitude, phase place, biasing and port number according to the configuration order of input module 20.The Wave data of sinusoidal signal is stored in the controller 30, because the symmetry of sinusoidal signal only needs the data of the positive half period of storage to get final product.Controller 30 is according to the order of input module 20, parse the sinusoidal wave frequency, amplitude, phase place and the offset parameter that need output, controller 30 is according to these parameters, circulation extracts corresponding data from Wave data, and the data that extract are regulated, thereby realize the adjusting of amplitude and biasing.Controller 30 is according to phase parameter, by postponing to extract the fixed skew that realizes several signals.The data of controller 30 outputs are converted to analog signal by digital/analog converter 40, pass through the filtering of filter 50 again, the filtering burr, output smoothing, frequency, amplitude, phase place and biasing be configurable multichannel synchronous sinusoidal signal all.
Therefore, the utility model can dispose frequency, amplitude, biasing and the phase place of needed sinusoidal signal flexibly according to the needs of test, and can keep between the multiple signals synchronously.In addition, because Wave data is stored in the inside of described controller 30, and need not to expand external memory storage, simplified the hardware of described sinusoidal signal analogue means 1.Because output signal frequency can obtain by the clock signal frequency division to clock source 10 output, pulse daley value and sampling step-length are set, frequency that namely can the flexible configuration sinusoidal signal need not outside DDS chip.When system clock frequency was 80MHz, the peak frequency of exportable sinusoidal signal was about 32KHz.Sinusoidal signal can realize the amplification of amplitude in controller 30 inside by multiplier, the biasing by multiplier and adder realization direct current need not outside expander amplifier.
Please refer to Fig. 2, in the present embodiment, described controller 30 comprises: the phase-locked loop 301 that links to each other with described clock source 10, the interface module 302 of Xiang Lianing, command analysis module 303, data processing module 304, data latch synchronization module 305 and digital/analog converter control module 306 successively, described interface module 302 links to each other with described input module 20, and described digital/analog converter control module 306 links to each other with described digital/analog converter 40.Preferable, described data processing module 304 comprises data adjusting module 3041, data extraction module 3042 and waveform data memory 3043, wherein, described data extraction module 3042 latchs synchronization module 305 with described command analysis module 303, data adjusting module 3041, data respectively and waveform data memory 3043 links to each other, and described data adjusting module 3041 also latchs synchronization module 305 with described command analysis module 303 and data respectively and links to each other.
Particularly, please refer to Fig. 2, and in conjunction with Fig. 3, phase-locked loop 301 provides clock reference for entire controller 30, interface module 302 receives the instruction that input module 20 sends, send by command analysis module 303 and resolve, command analysis module 303 parses the parameter information that will produce sinusoidal signal, and the beginning of control data extraction module 3042 and stopping.After the order that receives the beginning extracted data that command analysis module 303 sends, data extraction module 3042 is according to the instruction that receives, begin to read Wave data according to certain frequency and extraction step-length from waveform data memory 3043, the data that described data extraction module 3042 will read from data storage 3043 send data adjusting module 3041 earlier to.Data extraction module 3042 extracts Wave data successively and judges the symbol of current data from waveform data memory 3043, namely, the positive half cycle of waveform is for just, and negative half period multiply by amplitude for negative with Wave data, can adjust the amplitude of sinusoidal signal, again according to current data symbol, with the value addition of amplitude or subtract each other, just can adjust direct current biasing, realize the amplitude amplification of sinusoidal signal and the adjustment of direct current biasing, the data after the adjustment send to data and latch in the synchronization module 305.Data latch synchronization module 305 poll current data several times in a transmission cycle, signal according to data extraction module 3042, whether judgment data has renewal, then immediately data is sent to digital-to-analog conversion and control module 306 if any upgrading, and is notified to data extraction module 3042; If there is not Data Update, then skip current data.Digital-to-analog conversion and control module 306 latchs data and the channel information that synchronization module 305 transmission come according to data, data is sent to digital/analog converter 40 passages of appointment.Data latch synchronization module 305 by polling mechanism at a high speed, have both guaranteed that Wave data was in time sent, guarantee again between each passage synchronously.For the phase place of the sinusoidal signal between a plurality of passages, can realize by output delay.In the present embodiment, described digital/analog converter 40 is selected the digital/analog converter of four-way serial input for use, employing+10V reference voltage, and exportable voltage range is-10V ~+10V.Filter 50 is selected simple RC filter for use.
Please continue with reference to Fig. 2, as preferably, described controller 30 is field programmable gate array (FPGA), realizes that Wave data storage, sequencing control control with interface.Waveform signal is stored in FPGA inside, even Wave data can not disappear yet after the described FPGA power down, because Wave data is stored in FPGA inside, has very high reading speed again.Described input module 20 is optical-fibre communications module, USB communication module or RS232 communication module, realizes the isoparametric configuration of sine wave freuqency amplitude.Described clock source 10 is active crystal oscillator, and frequency is 290MHz, and clock signal is connected to the phase-locked loop 301 of controller 30.
In sum, sinusoidal signal analogue means of the present utility model, comprise: input module 20, clock source 10, controller 30, digital/analog converter 40 and filter 50, described controller 30 respectively with described input module 20, clock source 10 and digital/analog converter 40 link to each other, described filter 50 links to each other with described digital/analog converter 40, input module 20 is used for receiving the configuration order of host computer, controller 30 receives the configuration order of input module 20 transmission, and produce corresponding configuration data according to configuration order, the realization configuration data is resolved, the Wave data storage, the extraction of Wave data and the conversion of data, data after the conversion are passed to digital/analog converter 40 and transfer analog signal to, and carry out smothing filtering by filter 50, output to tested object.。The utility model can dispose frequency, amplitude, biasing and the phase place of needed sinusoidal signal flexibly according to the needs of test, and can keep between the multiple signals synchronously.In addition, because Wave data is stored in the inside of described controller 30, and need not to expand external memory storage, simplified the hardware of described sinusoidal signal analogue means 1.Because output signal frequency can obtain by the clock signal frequency division to clock source 10 output, pulse daley value and sampling step-length are set, frequency that namely can the flexible configuration sinusoidal signal need not outside DDS chip.When system clock frequency was 80MHz, the peak frequency of exportable sinusoidal signal was about 32KHz.Sinusoidal signal can realize the amplification of amplitude in controller 30 inside by multiplier, the biasing by multiplier and adder realization direct current need not outside expander amplifier.
Obviously, those skilled in the art can carry out various changes and modification to utility model and not break away from spirit and scope of the present utility model.Like this, if of the present utility model these revise and modification belongs within the scope of the utility model claim and equivalent technologies thereof, then the utility model also is intended to comprise these change and modification.
Claims (9)
1. sinusoidal signal analogue means, the two ends of described sinusoidal signal analogue means link to each other with tested object with host computer respectively, it is characterized in that, comprise: input module, clock source, controller, digital/analog converter and filter, described controller links to each other with described input module, clock source and digital/analog converter respectively, and described filter links to each other with described digital/analog converter;
Input module is used for receiving the configuration order of host computer, controller receives the configuration order of input module transmission, and produce corresponding configuration data according to configuration order, realize configuration data parsing, Wave data storage, the extraction of Wave data and the conversion of data, data after the conversion are passed to digital/analog converter and transfer analog signal to, and carry out smothing filtering by filter, output to tested object.
2. sinusoidal signal analogue means as claimed in claim 1, it is characterized in that, described controller comprises: the phase-locked loop that links to each other with described clock source, the interface module of Xiang Lianing, command analysis module, data processing module, data latch synchronization module and digital/analog converter control module successively, and described interface module links to each other with described input module, and described digital/analog converter control module links to each other with described digital/analog converter.
3. sinusoidal signal analogue means as claimed in claim 2, it is characterized in that, described data processing module comprises data adjusting module, data extraction module and waveform data memory, wherein, with described command analysis module, data adjusting module, data latch synchronization module and waveform data memory links to each other, described data adjusting module also latchs synchronization module with described command analysis module with data respectively and links to each other described data extraction module respectively.
4. as any described sinusoidal signal analogue means among the claim 1-3, it is characterized in that described configuration data comprises the configuration data of sampling step-length, pulse daley value, amplitude, phase place, biasing, port number.
5. sinusoidal signal analogue means as claimed in claim 1 is characterized in that, described controller is field programmable gate array.
6. sinusoidal signal analogue means as claimed in claim 1 is characterized in that, described input module is optical-fibre communications module, USB communication module or RS232 communication module.
7. sinusoidal signal analogue means as claimed in claim 1 is characterized in that, described clock source is active crystal oscillator.
8. sinusoidal signal analogue means as claimed in claim 1 is characterized in that, described digital/analog converter is the digital/analog converter of four-way serial input.
9. sinusoidal signal analogue means as claimed in claim 1 is characterized in that, described filter is the RC filter.
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| CN 201220742435 CN203071910U (en) | 2012-12-28 | 2012-12-28 | Sinusoidal signal simulation device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105116183A (en) * | 2015-08-24 | 2015-12-02 | 中国科学院微电子研究所 | Multi-Channel Waveform Signal Generator |
| CN105634718A (en) * | 2014-11-20 | 2016-06-01 | 计算系统有限公司 | Apparatus and method for signal synchronization |
| CN109426176A (en) * | 2017-08-22 | 2019-03-05 | 中国计量科学研究院 | A kind of isolation of multichannel and the synchronous sine wave generating system and its method of clock |
| CN113541519A (en) * | 2021-07-26 | 2021-10-22 | 深圳市尚科新能源有限公司 | Synchronous phase locking method for power supply and power supply |
| CN114375445A (en) * | 2019-08-29 | 2022-04-19 | 微芯片技术股份有限公司 | Preprocessing data using autonomous memory access and related systems, methods, and devices |
-
2012
- 2012-12-28 CN CN 201220742435 patent/CN203071910U/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634718A (en) * | 2014-11-20 | 2016-06-01 | 计算系统有限公司 | Apparatus and method for signal synchronization |
| CN105634718B (en) * | 2014-11-20 | 2020-01-21 | 计算系统有限公司 | Apparatus and method for signal synchronization |
| CN105116183A (en) * | 2015-08-24 | 2015-12-02 | 中国科学院微电子研究所 | Multi-Channel Waveform Signal Generator |
| CN109426176A (en) * | 2017-08-22 | 2019-03-05 | 中国计量科学研究院 | A kind of isolation of multichannel and the synchronous sine wave generating system and its method of clock |
| CN114375445A (en) * | 2019-08-29 | 2022-04-19 | 微芯片技术股份有限公司 | Preprocessing data using autonomous memory access and related systems, methods, and devices |
| CN114375445B (en) * | 2019-08-29 | 2022-12-27 | 微芯片技术股份有限公司 | Preprocessing data using autonomous memory access and related systems, methods, and apparatus |
| CN113541519A (en) * | 2021-07-26 | 2021-10-22 | 深圳市尚科新能源有限公司 | Synchronous phase locking method for power supply and power supply |
| CN113541519B (en) * | 2021-07-26 | 2023-01-06 | 深圳市尚科新能源有限公司 | Synchronous phase locking method for power supply and power supply |
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Address after: 201203 Pudong New Area East Road, No. 1525, Shanghai Patentee after: SHANGHAI MICRO ELECTRONICS EQUIPMENT (GROUP) Co.,Ltd. Address before: 201203 Pudong New Area East Road, No. 1525, Shanghai Patentee before: SHANGHAI MICRO ELECTRONICS EQUIPMENT Co.,Ltd. |
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Granted publication date: 20130717 |