CN203039666U - Single-end conversion differential circuit and radio frequency power amplifier - Google Patents
Single-end conversion differential circuit and radio frequency power amplifier Download PDFInfo
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- CN203039666U CN203039666U CN 201220631926 CN201220631926U CN203039666U CN 203039666 U CN203039666 U CN 203039666U CN 201220631926 CN201220631926 CN 201220631926 CN 201220631926 U CN201220631926 U CN 201220631926U CN 203039666 U CN203039666 U CN 203039666U
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Abstract
The utility model provides a single-end conversion differential circuit which comprises (2n-1) phase inverters. Single-end period signals are divided into first output signals and second output signals to be output, wherein the first output signals are output as first differential signals through n phase inverters and the second output signals are output as second differential signals through (n-1) phase inverters. Therefore, the first output signals are output as the first differential signals after a phase of the first output signals reverses 180 degrees n times, the second output signals are output as the second differential signals after a phase of the second output signals reverses 180 degrees (n-1) times, and a phase difference between the first differential signals and the second differential signals is 180 degrees. Moreover, the phase inverters are usually composed of power devices and do not has single fixed frequency points, so that the single-end conversion differential circuit of the utility model enables the single-end period signals within a certain frequency scope to be converted into the differential signals so as to be more convenient to apply. The utility model further provides a radio frequency power amplifier.
Description
Technical field
The utility model relates to wireless communication field, especially relates to a kind of single-ended transfer difference circuit and radio-frequency power amplifier.
Background technology
Radio-frequency power amplifier is mainly used in the wireless telecommunication system, is the important component part of various transmitting sets.Radio-frequency power amplifier adopts single ended mode or differential mode to realize usually, the radio-frequency power amplifier that single ended mode is realized has characteristic of simple structure, but it need have good ground connection, therefore is subjected to power supply and the interference of signal on the ground easily, thereby easily produces clutter and concussion.And the radio-frequency power amplifier that differential mode is realized is lower to the requirement of ground connection, is not vulnerable to power supply and the interference of signal on the ground.But because the input signal of radio-frequency power amplifier is single-ended periodic signal, so need a single-ended transfer difference circuit in the radio-frequency power amplifier of differential mode realization, realize single-ended periodic signal is converted to the differential signal of 180 ° of phase phasic differences.
In the prior art, a kind of single-ended transfer difference circuit adopts first order transformer as shown in Figure 1, because the single-ended transfer difference circuit realizes that by chip transformer device structure often area occupied is very big usually, has therefore increased the cost of chip.In order to save cost, the implementation of another kind of single-ended transfer difference also is provided in the prior art, as shown in Figure 2, the single-ended transfer difference circuit is made up of the LC-CL network, this single-ended transfer difference circuit no longer need transformer, so cost is lower.But because the frequency of LC-CL network is fixed, namely the single-ended periodic signal of characteristic frequency can only be changed into differential signal, therefore need design the LC-CL network of different frequent points for the single-ended periodic signal of different frequency, thereby cause the inconvenience of using.
The utility model content
The technical problem that the utility model solves is to provide a kind of single-ended transfer difference circuit and radio-frequency power amplifier, make same single-ended transfer difference circuit can realize the single-ended periodic signal of frequency in the certain limit is changed into differential signal, thus should use more convenient.
For this reason, the technical scheme of the utility model technical solution problem is:
The utility model provides a kind of single-ended transfer difference circuit, and described circuit comprises: (2n-1) individual inverter, wherein n 〉=1;
Single-ended periodic signal is divided into first output signal and second output signal; First output signal is exported as first differential signal through behind n inverter; Described second output signal is exported as second differential signal through behind (n-1) individual inverter.
Preferably, described first output signal through first inverter after as first differential signal output, described second output signal is exported as second differential signal.
Preferably, m inverter in the n of the described first output signal process inverter is for amplifying inverter; M inverter in (n-1) individual inverter of the described second output signal process is for amplifying inverter, and the amplification coefficient of the m of the described first output signal process amplification inverter is identical with the amplification coefficient of m amplification inverter of the described second output signal process; Wherein, (n-1) 〉=m 〉=1.
Preferably, described first output signal successively through behind second inverter and the 3rd inverter as first differential signal output, described second output signal is exported as second differential signal after through the 4th inverter;
Described second inverter and the 4th inverter are the amplification inverter, and described second inverter is identical with the amplification coefficient of the 4th inverter.
Preferably, described amplification inverter comprises the 2nd NMOS pipe, the 2nd PMOS pipe and first resistance, the source ground level of described the 2nd NMOS pipe, the source electrode of described the 2nd PMOS pipe connects supply voltage, the grid of the grid of described the 2nd NMOS pipe and the 2nd PMOS pipe links to each other and as the input of described amplification inverter, the drain electrode of the drain electrode of described the 2nd NMOS pipe and the 2nd PMOS pipe links to each other and as the output of described amplification inverter, series connection first resistance between the input of described amplification inverter and the output.
Preferably, described amplification inverter comprises the 3rd NMOS pipe and second resistance, the source ground level of described the 3rd NMOS pipe, and the drain electrode of described the 3rd NMOS pipe connects supply voltage by second resistance; The grid of described the 3rd NMOS pipe is as the input of described amplification inverter, and the drain electrode of described the 3rd NMOS pipe is as the output of described amplification inverter.
Preferably, amplify inverter and comprise the 4th NMOS pipe and the 5th NMOS pipe, the source ground level of described the 4th NMOS pipe, the drain electrode of described the 4th NMOS pipe connects the source electrode of the 5th NMOS pipe, and the drain and gate of described the 5th NMOS pipe all connects supply voltage; The grid of described the 4th NMOS pipe is as the input of described amplification inverter, and the drain electrode of described the 4th NMOS pipe is as the output of described amplification inverter.
Preferably, described circuit also comprises first amplifying stage and second amplifying stage that amplification coefficient is identical;
Described first output signal through first amplifying stage and n inverter after as the output of first differential signal, described second output signal through second amplifying stage and (n-1) individual inverter export as second differential signal.
Preferably, described inverter comprises NMOS pipe and PMOS pipe, the source ground level of a described NMOS pipe, the source electrode of a described PMOS pipe connects supply voltage, the grid of the grid of a described NMOS pipe and a PMOS pipe links to each other and as the input of inverter, and the drain electrode of the drain electrode of a described NMOS pipe and a PMOS pipe links to each other and as the output of inverter.
Preferably, described circuit also comprises delay circuit;
Export as second differential signal behind described second output signal process (n-1) individual inverter and the delay circuit;
The delay time of described delay circuit equals the poor of delay time that described first output signal passes through (n-1) individual inverter through delay time and described second output signal of n inverter.
The utility model also provides a kind of radio-frequency power amplifier, and described amplifier comprises: AC power, output resistance, driving stage, power stage, transformer, antenna and as any described single-ended transfer difference circuit of claim 1 to 10;
The supply voltage of described AC power output is sent to the single-ended transfer difference circuit through behind the output resistance as single-ended periodic signal;
Through the former limit of the described transformer of series connection after driving stage, the power stage, the secondary of described transformer is connected between antenna and the ground level successively for first differential signal of described single-ended transfer difference circuit output and second differential signal;
Described driving stage is used for amplifying first differential signal and second differential signal, so that first differential signal and second differential signal after amplifying can drive described power stage;
Described power stage is used for providing enough power gains to the signal of described driving stage output.
By technique scheme as can be known, in the single-ended transfer difference circuit in the utility model single-ended periodic signal is divided into first and second output signals, first output signal is through n inverter, be that export as first differential signal 180 ° of n backs of phasing back, second output signal is through n-1 inverter, be that export as second differential signal 180 ° of (n-1) inferior backs of phasing back, as can be seen, first differential signal is the differential signal of 180 ° of phasic differences mutually with second differential signal.And because inverter is made up of power device usually, therefore do not have single fixedly frequency, can carry out the signal of frequency in the certain limit anti-phase, therefore the single-ended transfer difference circuit that provides of the utility model can be realized the single-ended periodic signal of frequency in the certain limit is changed into differential signal, thus should use more convenient.
Description of drawings
Fig. 1 is a kind of structural representation of single-ended transfer difference circuit of the prior art;
Fig. 2 is the structural representation of another kind of single-ended transfer difference circuit of the prior art;
The structural representation of one specific embodiment of the single-ended transfer difference circuit that Fig. 3 provides for the utility model;
The concrete structure figure of the inverter that Fig. 4 provides for the utility model;
The concrete structure figure of another inverter that Fig. 5 provides for the utility model;
The concrete structure figure of another inverter that Fig. 6 provides for the utility model;
The concrete structure figure of another inverter that Fig. 7 provides for the utility model;
The structural representation of another specific embodiment of single-ended transfer difference circuit that Fig. 8 provides for the utility model;
The structural representation of another specific embodiment of single-ended transfer difference circuit that Fig. 9 provides for the utility model;
The structural representation of another specific embodiment of single-ended transfer difference circuit that Figure 10 provides for the utility model;
The structural representation of another specific embodiment of single-ended transfer difference circuit that Figure 11 provides for the utility model;
The concrete structure figure of the delay circuit that Figure 12 provides for the utility model;
The structural representation of the specific embodiment of the power radio-frequency amplifiers that Figure 13 provides for the utility model;
Figure 14 is driving stage in the power radio-frequency amplifiers shown in Figure 13 or the structural representation of power stage.
Embodiment
See also Fig. 3, the utility model provides a kind of specific embodiment of single-ended transfer difference circuit, and described circuit comprises: (2n-1) individual inverter 301 and 302, wherein n 〉=1 that is to say that n is the integer more than or equal to 1.
Single-ended periodic signal is divided into first output signal and the output of second output signal.Here, single-ended periodic signal can be to be divided into first output signal and second output signal.As the output of first differential signal, export as second differential signal through (n-1) individual inverter 302 backs by second output signal through n inverter 301 backs for first output signal.Wherein, single-ended periodic signal can be periodic square-wave signal or periodic sine wave signal.In radio-frequency power amplifier, single-ended periodic signal can be produced by radio-frequency signal source.
By technique scheme as can be known, single-ended periodic signal is divided into first output signal and second output signal in the single-ended transfer difference circuit among this embodiment, first output signal is through n inverter, be that export as first differential signal 180 ° of n backs of phasing back, second output signal is through n-1 inverter, be that export as second differential signal 180 ° of (n-1) inferior backs of phasing back, as can be seen, first differential signal is the differential signal of 180 ° of phasic differences mutually with second differential signal.And because inverter is made up of power device usually, can carry out the signal of frequency in the certain limit anti-phase, therefore the single-ended transfer difference circuit that provides of the utility model can be realized the single-ended periodic signal of frequency in the certain limit is changed into differential signal, thus should use more convenient.
In this embodiment, n inverter 301 and (n-1) the direct order end periodic signal of individual inverter 302.In fact, the single-ended transfer difference circuit that the utility model provides can also comprise power splitter, and namely power divider is divided into first output signal and second output signal by power splitter with single-ended periodic signal.
Inverter is a kind of device of 180 ° of the phasing backs of signal can the be made up of power device usually.Fig. 4 to Fig. 7 provides the composition form of four kinds of inverters.
The inverter that provides among Fig. 4 comprises NMOS pipe N1 and PMOS pipe P1, the source ground level of the one NMOS pipe N1, the source electrode of the one PMOS pipe P1 connects supply voltage, the grid of the grid of the one NMOS pipe N1 and PMOS pipe P1 links to each other and as the input of this inverter, and the drain electrode that the drain electrode of NMOS pipe N1 and a PMOS manage P1 links to each other and as the output of this inverter.When the inverter among Fig. 4 was in running order, when its input signal was low level, then NMOS pipe N1 was in cut-off region, the one PMOS pipe P1 is in linear zone, when its input signal was high level, then NMOS pipe N1 was in linear zone, and PMOS pipe P1 is in cut-off region.
The inverter that provides among Fig. 5 to Fig. 7 is the inverter with enlarging function, namely amplify inverter, amplification inverter among Fig. 5 comprises the 2nd NMOS pipe N2, the 2nd PMOS pipe P2 and first resistance R 1, the source ground level of the 2nd NMOS pipe N2, the source electrode of the 2nd PMOS pipe P2 connects supply voltage, the grid of the grid of the 2nd NMOS pipe N2 and the 2nd PMOS pipe P2 links to each other and as the input of this amplification inverter, the drain electrode of the drain electrode of the 2nd NMOS pipe N2 and the 2nd PMOS pipe P2 links to each other and as the output of this amplifications inverter, first resistance R 1 of connecting between the input of this amplification inverter and the output.Because the existence of first resistance R 1, during the inverter that provides among Fig. 5 work, the 2nd NMOS pipe N2 and the 2nd PMOS pipe P2 all are in the amplification region.
Amplification inverter among Fig. 6 comprises the source ground level of the 3rd NMOS pipe N3 and second resistance R, 2, the three NMOS pipe N3, and the drain electrode of the 3rd NMOS pipe N3 connects supply voltage by second resistance R 2.The grid of the 3rd NMOS pipe N3 amplifies the input of inverter as this, and the drain electrode of the 3rd NMOS pipe N3 is amplified the output of inverter as this.
Amplification inverter among Fig. 7 comprises the 4th NMOS pipe N4 and the 5th NMOS pipe N5, the source ground level of the 4th NMOS pipe N4, and the drain electrode of the 4th NMOS pipe N4 connects the source electrode of the 5th NMOS pipe N5, and the drain and gate of the 5th NMOS pipe N5 all connects supply voltage.The grid of the 4th NMOS pipe N4 amplifies the input of inverter as this, the drain electrode of the 4th NMOS pipe N4, and namely the source electrode of the 5th NMOS pipe N5 amplifies the output of inverter as this.
Except the inverter that Fig. 4 to Fig. 7 provides, the inverter of various ways also is provided in the prior art, all can be used for the embodiment that the utility model provides, give unnecessary details no longer one by one at this.
The single-ended transfer difference circuit of the inverter that employing Fig. 4 provides is described below by an embodiment.
See also Fig. 8, the utility model provides another specific embodiment of single-ended transfer difference circuit, in this embodiment, and n=1.This circuit comprises: first inverter 801.Wherein first inverter 801 is inverter shown in Figure 4.
Single-ended periodic signal is divided into first output signal and the output of second output signal.As the output of first differential signal, directly export as second differential signal by described second output signal through first inverter, 801 backs for first output signal.Wherein, single-ended periodic signal can be periodic square-wave signal or periodic sine wave signal.In radio-frequency power amplifier, single-ended periodic signal can be produced by radio-frequency signal source.
First output signal among this embodiment is through first inverter 801, be to export as first differential signal after 180 ° of the phasing backs 1 time, second output signal is directly exported, be that phase invariant is directly exported as second differential signal, therefore, first differential signal is the differential signal of 180 ° of phasic differences mutually with second differential signal.In fact, first inverter 801 can also adopt the inverter of other arbitrary forms.
In this embodiment, the direct order end periodic signal of the output of first inverter 801 and second differential signal.
In the embodiment that the utility model provides, when single-ended periodic signal hour, first output signal and second output signal are also less, therefore can first output signal and second output signal be amplified by amplification inverter or the amplifying stage that Fig. 5 to Fig. 7 provides.Be illustrated by two embodiment respectively below.
See also Fig. 9, the utility model provides another specific embodiment of single-ended transfer difference circuit, in this embodiment, and n=2.This circuit comprises: second inverter 901, the 3rd inverter 902 and the 4th inverter 903.Wherein second inverter 902 is inverter shown in Figure 4, and second inverter 901 and the 4th inverter 903 are amplification inverter shown in Figure 5.And second inverter 901 is identical with the amplification coefficient of the 4th inverter 903.
Single-ended periodic signal is divided into first output signal and the output of second output signal.First output signal is exported as first differential signal through second inverter 901 and the 3rd inverter 902 backs.Wherein, first output signal can be as shown in Figure 9 successively through second inverter 901 and the 3rd inverter 902, also can be successively through the 3rd inverter 902 and second inverter 901.Second output signal is exported as second differential signal through the 4th inverter 903 backs.Wherein, single-ended periodic signal can be periodic square-wave signal or periodic sine wave signal.In radio-frequency power amplifier, single-ended periodic signal can be produced by radio-frequency signal source.
In this embodiment, the direct order end periodic signal of second inverter 901 and the 4th inverter 903.
First output signal among this embodiment is through second inverter 901 and the 3rd inverter 902, therefore export as first differential signal after 180 ° of the signal phase counter-rotatings of first output 2 times, second output signal is through the 4th inverter 903, therefore export as second differential signal after 180 ° of the signal phase counter-rotatings of second output 1 time, therefore, first differential signal is the differential signal of 180 ° of phasic differences mutually with second differential signal.And because second inverter 901 is identical with the amplification coefficient of the 4th inverter 903, therefore first output signal is identical with the multiple that second output signal is exaggerated.Second inverter 901 among this embodiment and the 4th inverter 903 can also adopt the amplification inverter of arbitrary forms such as Fig. 6 or Fig. 7.
In other embodiments, the amplification coefficient of second inverter and the 4th inverter can be different, and both also can adopt the amplification inverter of different structure.
In fact, in other embodiments, can amplify first output signal and secondary signal with a plurality of amplification inverters.Particularly, in the embodiment shown in fig. 3, m1 inverter in the n of the first output signal process inverter is for amplifying inverter.M2 inverter in (n-1) individual inverter of the second output signal process is for amplifying inverter.Wherein, (n-1) 〉=m1 〉=1, (n-1) 〉=m1 〉=1.And amplify the amplification inverter that inverter can adopt arbitrary form such as Fig. 5 to Fig. 7.Preferably, m1=m2=m, the amplification coefficient of the m of the first output signal process amplification inverter is identical with the amplification coefficient of m amplification inverter of the described second output signal process.
See also Figure 10, the utility model provides another specific embodiment of single-ended transfer difference circuit, in this embodiment, and n=2.This circuit comprises: the 5th inverter 1001, first amplifying stage 1002 and second amplifying stage 1003.First amplifying stage 1002 is identical with the amplification coefficient of second amplifying stage 1003.The 5th inverter 1001 is inverter shown in Figure 4.
Single-ended periodic signal is divided into first output signal and the output of second output signal.First output signal is exported as first differential signal through first amplifying stage 1002 and the 5th inverter 1001 backs.Wherein, first output signal can be as shown in figure 10 successively through first amplifying stage 1002 and the 5th inverter 1001, also can be successively through the 5th inverter 1001 and first amplifying stage 1002.Second output signal is exported as second differential signal through second amplifying stage, 1003 backs.Wherein, single-ended periodic signal can be periodic square-wave signal or periodic sine wave signal.In radio-frequency power amplifier, single-ended periodic signal can be produced by radio-frequency signal source.In fact, the 5th inverter 1001 can also adopt the inverter of other arbitrary forms.
In this embodiment, the direct order end periodic signal of first amplifying stage 1002 and second amplifying stage 1003.
First amplifying stage among this embodiment amplifies the input signal of first amplifying stage, and second amplifying stage amplifies the input signal of second amplifying stage.And first amplifying stage is identical with the amplification coefficient of second amplifying stage, so first output signal is identical with the multiple that second output signal is exaggerated among this embodiment.In other embodiments, the amplification coefficient of first amplifying stage 1002 and second amplifying stage 1003 also can be inequality.
In other embodiments, can adopt a more than inverter.Particularly, first output signal through first amplifying stage and n inverter after as the output of first differential signal, described second output signal through second amplifying stage and (n-1) individual inverter export as second differential signal.Wherein, first output signal is not limited through the concrete order of first amplifying stage and n inverter.Second output signal through second amplifying stage and (n-1) the concrete order of individual inverter do not limited yet.N 〉=1 wherein.
Because inverter can produce certain time-delay, for the single-ended periodic signal of some high frequencies, to the requirement meeting of time-delay than higher.Therefore the time-delay that can cause by the delay circuit compensated inverter is illustrated below by an embodiment.
See also Figure 11, the utility model provides another specific embodiment of single-ended transfer difference circuit, in this embodiment, and n=1.This circuit comprises: hex inverter 1101 and delay circuit 1102.Wherein hex inverter 1101 is inverter shown in Figure 4.
Single-ended periodic signal is divided into first output signal and the output of second output signal.First output signal is exported as first differential signal through hex inverter 1101 backs.Second output signal process delay circuit, 1102 backs are as second differential signal.The delay time of delay circuit 1102 is identical with the delay time of hex inverter 1101.Wherein, single-ended periodic signal can be periodic square-wave signal or periodic sine wave signal.In radio-frequency power amplifier, single-ended periodic signal can be produced by radio-frequency signal source.In fact, hex inverter 1101 can adopt other forms of inverter.
In this embodiment, the direct order end periodic signal of hex inverter 1101 and delay circuit 1102.
1101 pairs of first output signals of hex inverter have caused certain phase place time-delay among this embodiment, and delay circuit 1102 has compensated this time-delay just.Therefore first differential signal and second differential signal of final output are that phase place just in time differs 180 ° differential signal.
In fact, in other embodiments, can comprise (2n-1) individual inverter.Particularly, as the output of first differential signal, export as second differential signal behind second output signal process (n-1) individual inverter and the delay circuit behind n inverter of first output signal process.Wherein, second output signal is not limited through the concrete order of (n-1) individual inverter and delay circuit.And the delay time of delay circuit equals first output signal is passed through (n-1) individual inverter through the delay time of n inverter and second output signal delay time poor.
Delay circuit can be made up of two quick inverters, also can adopt structure as shown in figure 12.Only need to realize that delay function gets final product.
Delay circuit as shown in figure 12 comprises time delay resistance R3 and ground capacity C1, first end of time delay resistance R3 is as the input of delay circuit, second end of time delay resistance R3 is as the output of delay circuit, and second end of time delay resistance R3 is by ground capacity C1 ground connection.
As shown in figure 13, the utility model also provides a kind of specific embodiment of radio-frequency power amplifier.Among this embodiment, described amplifier comprises: the single-ended transfer difference circuit 1302 among radio-frequency signal source 1301, the embodiment as shown in Figure 8, driving stage 1303, power stage 1304, transformer 1305 and antenna 1306.Single-ended transfer difference circuit 1303 comprises first inverter 601.Wherein first inverter 601 is inverter shown in Figure 4.
The single-ended periodic signal of radio-frequency signal source 1301 outputs.
Described single-ended periodic signal is divided into first output signal and the output of second output signal.As the output of first differential signal, directly export as second differential signal by described second output signal through first inverter, 601 backs for first output signal.
First differential signal of single-ended transfer difference circuit 1302 outputs and second differential signal pass through the former limit of driving stage 1303, power stage 1304 back series transformers 1305 successively, and the secondary of transformer 1305 is connected between antenna 1306 and the ground level.
Driving stage 1303 is used for amplifying first differential signal and second differential signal, so that first differential signal and second differential signal after amplifying can driving power levels 1304.
Wherein, single-ended transfer difference circuit 1102 can also adopt any one in the single-ended transfer difference embodiment of circuit in the utility model.
Wherein, driving stage 1303 and power stage 1304 all can adopt structure as shown in figure 14.When driving stage 1303 adopted structure shown in Figure 14, driving stage 1303 comprised: the 6th NMOS pipe N6, the 7th NMOS pipe N7, the 8th NMOS pipe N8, the 9th NMOS pipe N9, first inductance L 1 and second inductance L 2.The grid of the 7th NMOS pipe N7 is the first input end of driving stage 1303, the source ground of the 7th NMOS pipe N7, the drain electrode of the 7th NMOS pipe N7 connects the source electrode of the 6th NMOS pipe N6, the grid of the 6th NMOS pipe N6 is first output, and the drain electrode of the 6th NMOS pipe N6 connects supply voltage by first inductance L 1.The grid of the 9th NMOS pipe N9 is second input of driving stage 1303, the source ground of the 9th NMOS pipe N9, the drain electrode of the 9th NMOS pipe N9 connects the source electrode of the 8th NMOS pipe N8, the grid of the 8th NMOS pipe N8 is second output, and the drain electrode of the 8th NMOS pipe N8 connects supply voltage by second inductance L 2.When the input signal of first input end was first differential signal, the input signal of second input was second differential signal.When the input signal of first input end was second differential signal, the input signal of second input was first differential signal.First output is connected power stage 1304 with second output.
When power stage 1304 adopts structure shown in Figure 14, connected mode when adopting structure shown in Figure 14 with driving stage 1303 is similar, difference no longer is first differential signal and second differential signal for the input signal of the first input end of power stage 1304 and second input only, but the output signal after driving stage 1303 of first differential signal and second differential signal, the former limit of the first input end of power stage 1304 and the second input series transformer 1305.
The above only is preferred implementation of the present utility model; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection range of the present utility model.
Claims (11)
1. a single-ended transfer difference circuit is characterized in that, described circuit comprises: (2n-1) individual inverter, wherein n 〉=1;
Single-ended periodic signal is divided into first output signal and second output signal; First output signal is exported as first differential signal through behind n inverter; Described second output signal is exported as second differential signal through behind (n-1) individual inverter.
2. circuit according to claim 1 is characterized in that, described first output signal through first inverter after as first differential signal output, described second output signal is exported as second differential signal.
3. circuit according to claim 1 is characterized in that, m inverter in the n of the described first output signal process inverter is for amplifying inverter; M inverter in (n-1) individual inverter of the described second output signal process is for amplifying inverter, and the amplification coefficient of the m of the described first output signal process amplification inverter is identical with the amplification coefficient of m amplification inverter of the described second output signal process; Wherein, (n-1) 〉=m 〉=1.
4. circuit according to claim 3, it is characterized in that, described first output signal successively through behind second inverter and the 3rd inverter as first differential signal output, described second output signal is exported as second differential signal after through the 4th inverter;
Described second inverter and the 4th inverter are the amplification inverter, and described second inverter is identical with the amplification coefficient of the 4th inverter.
5. according to claim 3 or 4 described circuit, it is characterized in that, described amplification inverter comprises the 2nd NMOS pipe, the 2nd PMOS pipe and first resistance, the source ground level of described the 2nd NMOS pipe, the source electrode of described the 2nd PMOS pipe connects supply voltage, the grid of the grid of described the 2nd NMOS pipe and the 2nd PMOS pipe links to each other and as the input of described amplification inverter, the drain electrode of the drain electrode of described the 2nd NMOS pipe and the 2nd PMOS pipe links to each other and as the output of described amplification inverter, series connection first resistance between the input of described amplification inverter and the output.
6. according to claim 3 or 4 described circuit, it is characterized in that described amplification inverter comprises the 3rd NMOS pipe and second resistance, the source ground level of described the 3rd NMOS pipe, the drain electrode of described the 3rd NMOS pipe connects supply voltage by second resistance; The grid of described the 3rd NMOS pipe is as the input of described amplification inverter, and the drain electrode of described the 3rd NMOS pipe is as the output of described amplification inverter.
7. according to claim 3 or 4 described circuit, it is characterized in that, amplify inverter and comprise the 4th NMOS pipe and the 5th NMOS pipe, the source ground level of described the 4th NMOS pipe, the drain electrode of described the 4th NMOS pipe connects the source electrode of the 5th NMOS pipe, and the drain and gate of described the 5th NMOS pipe all connects supply voltage; The grid of described the 4th NMOS pipe is as the input of described amplification inverter, and the drain electrode of described the 4th NMOS pipe is as the output of described amplification inverter.
8. circuit according to claim 1 is characterized in that, described circuit also comprises first amplifying stage and second amplifying stage that amplification coefficient is identical;
Described first output signal through first amplifying stage and n inverter after as the output of first differential signal, described second output signal through second amplifying stage and (n-1) individual inverter export as second differential signal.
9. circuit according to claim 1, it is characterized in that, described inverter comprises NMOS pipe and PMOS pipe, the source ground level of a described NMOS pipe, the source electrode of a described PMOS pipe connects supply voltage, the grid of the grid of a described NMOS pipe and a PMOS pipe links to each other and as the input of inverter, and the drain electrode of the drain electrode of a described NMOS pipe and a PMOS pipe links to each other and as the output of inverter.
10. circuit according to claim 1 is characterized in that, described circuit also comprises delay circuit;
Export as second differential signal behind described second output signal process (n-1) individual inverter and the delay circuit;
The delay time of described delay circuit equals the poor of delay time that described first output signal passes through (n-1) individual inverter through delay time and described second output signal of n inverter.
11. a radio-frequency power amplifier is characterized in that, described amplifier comprises: AC power, output resistance, driving stage, power stage, transformer, antenna and as any described single-ended transfer difference circuit of claim 1 to 10;
The supply voltage of described AC power output is sent to the single-ended transfer difference circuit through behind the output resistance as single-ended periodic signal;
Through the former limit of the described transformer of series connection after driving stage, the power stage, the secondary of described transformer is connected between antenna and the ground level successively for first differential signal of described single-ended transfer difference circuit output and second differential signal;
Described driving stage is used for amplifying first differential signal and second differential signal, so that first differential signal and second differential signal after amplifying can drive described power stage;
Described power stage is used for providing enough power gains to the signal of described driving stage output.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220631926 CN203039666U (en) | 2012-11-26 | 2012-11-26 | Single-end conversion differential circuit and radio frequency power amplifier |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220631926 CN203039666U (en) | 2012-11-26 | 2012-11-26 | Single-end conversion differential circuit and radio frequency power amplifier |
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| CN203039666U true CN203039666U (en) | 2013-07-03 |
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| CN 201220631926 Expired - Lifetime CN203039666U (en) | 2012-11-26 | 2012-11-26 | Single-end conversion differential circuit and radio frequency power amplifier |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110061706A (en) * | 2018-01-19 | 2019-07-26 | 硅实验室公司 | Synthesizer-power amplifier interface in radio-circuit |
| CN110896315A (en) * | 2018-09-12 | 2020-03-20 | 宁德时代新能源科技股份有限公司 | Wireless radio frequency communication system |
| CN113556106A (en) * | 2021-07-28 | 2021-10-26 | 东南大学 | Hysteresis comparator with threshold voltage capable of being adjusted in self-adaptive mode |
| CN116505928A (en) * | 2023-06-28 | 2023-07-28 | 牛芯半导体(深圳)有限公司 | Buffer circuit applied to TX clock |
-
2012
- 2012-11-26 CN CN 201220631926 patent/CN203039666U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110061706A (en) * | 2018-01-19 | 2019-07-26 | 硅实验室公司 | Synthesizer-power amplifier interface in radio-circuit |
| CN110896315A (en) * | 2018-09-12 | 2020-03-20 | 宁德时代新能源科技股份有限公司 | Wireless radio frequency communication system |
| US10992327B2 (en) | 2018-09-12 | 2021-04-27 | Contemporary Amperex Technology Co., Limited | Wireless radio frequency communication system |
| CN113556106A (en) * | 2021-07-28 | 2021-10-26 | 东南大学 | Hysteresis comparator with threshold voltage capable of being adjusted in self-adaptive mode |
| CN116505928A (en) * | 2023-06-28 | 2023-07-28 | 牛芯半导体(深圳)有限公司 | Buffer circuit applied to TX clock |
| CN116505928B (en) * | 2023-06-28 | 2023-09-22 | 牛芯半导体(深圳)有限公司 | Buffer circuit applied to TX clock |
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