CN202815170U - Chip test system - Google Patents
Chip test system Download PDFInfo
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- CN202815170U CN202815170U CN 201220084366 CN201220084366U CN202815170U CN 202815170 U CN202815170 U CN 202815170U CN 201220084366 CN201220084366 CN 201220084366 CN 201220084366 U CN201220084366 U CN 201220084366U CN 202815170 U CN202815170 U CN 202815170U
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Abstract
The utility model relates to a chip test system in connection with an external test chip, comprising a host computer, a test plate and an IIC bus. The inner of the host computer is provided with test software and is in connection with the test plate through a USB interface; the host computer is used for generating test data and sends the data to the test plate through the USB interface; the test plate receives the test data to perform conversion between a USB protocol and an IIC protocol and is in connection with the external test chip through an ICC bus. According to the utility mode, data of a register can be visually checked and modified, obtained return values can be visually displayed on a PC terminal, data in Memory and Flash can be read in a batch mode and convenience can be provided for test personnel to have a direct understanding of chip inner data.
Description
Technical field
The utility model relates to the chip testing field, relates in particular to chip test system.
Background technology
Design of Digital Integrated Circuit (IC design) generally has following flow process:
1. system function design stage
Some are set such as function, operating speed, interface specification, environment temperature and consumed power equal-specification in the application scenario of designer's product, with as the foundation of future during circuit design.More further planning software module and hardware module this how to divide.
2. design description and behavioral scaling checking
After system function design is finished, can SOC be divided into some functional modules according to function, and determine the IP kernel that these functions of realization will be used.This stage will connect the framework that affected SOC inside and the signal of each intermodule interaction, and the reliability of future products.After the decision module, can realize with hardware description languages such as VHDL or Verilog the design of each module.Then, utilize the circuit emulator of VHDL or Verilog, functional verification is carried out in design.
3. logic synthesis
After determining that design description is correct, can use logic synthesis tool (synthesizer) to carry out comprehensively.
4. gate leve checking
The gate leve functional verification is the register transfer level verification.Main work is to confirm whether the circuit after comprehensive meets functional requirement, and this work general using gate level verification tool is finished.
5. place and route
The functional module arranged rational that layout refers to design is on chip, and planning is their position well.Wiring then refers to finish the line that interconnects between each module.
6. flow test
Produce designed chip by semiconductor technology, in order to test.
7. scale of mass production.
Summary of the invention
The utility model is applied to the board level test stage after the chip flow success, whether generally need to carry out " trial production " namely flow to it before chip large-scale production, the sample behind the convection rib carries out detection validation, successful in order to detect integrated circuit (IC) design, whether function meets the demands etc.
For achieving the above object, the technical solution adopted in the utility model is: a kind of chip test system, be connected with the external testing chip, and it is characterized in that: comprise host computer, test board, iic bus;
Described host computer is connected with test board by USB interface, is used for generating test data and passes to test board by USB interface;
Described test board receives test data and carries out usb protocol and the IIC protocol conversion, is connected with the external testing chip by the ICC bus.
The first preferred version of the present utility model is that described USB interface is the USB2.0 interface.
The second preferred version of the present utility model is that described usb protocol is the USB2.0 agreement.
The 3rd preferred version of the present utility model is, establishing testing software in described is visualization interface.
The 4th preferred version of the present utility model is that described test board comprises chip Cy68013.
Technical advantage of the present utility model is: can visually check the data of revising register, the rreturn value that obtains can be presented at the PC end intuitively, and reading in batches data among Memory, the Flash, cheap tester has one to get information about to Data within the chip.
Below in conjunction with the drawings and specific embodiments utility model is described further.
Description of drawings
Fig. 1 is the present embodiment structural representation.
Embodiment
With reference to figure 1, chip test system is connected with the external testing chip, comprises host computer, test board, iic bus; Establish testing software in the host computer and be connected with test board by USB interface, be used for generating test data and pass to test board by USB interface; Test board receives test data and carries out usb protocol and the IIC protocol conversion, is connected with the external testing chip by the ICC bus.USB interface is the USB2.0 interface.Usb protocol is the USB2.0 agreement.In to establish testing software be visualization interface.Test board comprises chip Cy68013.
Concrete methods of realizing may further comprise the steps:
(1) operator inputs host computer to data by visualization interface, and the host computer in house software changes into the data of USB2.0 agreement to data layout, then by USB interface data is sent;
(2) data communication device that sends of upper computer software is crossed the USB2.0 interface and is entered into plate level chip Cy68013, finishes USB2.0 to the IIC protocol translation in Cy68013, and last iic bus sends data.
(3) iic bus according to sevtor address data distribution in the interfaces such as each register, Memory.
(4) receive data of each interface, register after the chip functions logical operation, turns back to the PC end by this link again, shows.
Upper computer software:
The host computer in house software comprises read button, write button, dialog box, becomes different page functions according to the Module Division of chip, forgiving corresponding register in the page function, use register ID that it is sorted, each register has two kinds of operations of read-write, click the read button and can read the interior data of register, and turn back on the corresponding forms; Click the write button, can write the data in the respective dialog frame in the register, if read-write normally has corresponding prompting.
In the dialog box that the record operation is arranged bottom.
B) USB is to the IIC protocol conversion
In beta version, carried the Cy68013 chip of Cypress company, chip is connected to the USB interface end of PC can accept the data that PC transmits, integrated 8051 single-chip microcomputers in the Cy68013 chip, use two common I/O mouths of 8051 can simulate the iic bus agreement, data communication device is crossed iic bus and is sent.
C) iic bus is to die terminals
Comprised the sevtor address of each register in the data that iic bus carries, each register finds corresponding data by the sevtor address addressing, and data enter corresponding register and return to iic bus through after the logical operation, send back according to former link is counter.
Claims (2)
1. a chip test system is connected with the external testing chip, it is characterized in that: comprise host computer, test board, iic bus;
Described host computer is connected with test board by USB interface, is used for generating test data and passes to test board by USB interface;
Described test board receives test data and carries out usb protocol and the IIC protocol conversion, is connected with the external testing chip by the ICC bus.
2. chip test system according to claim 1, it is characterized in that: described USB interface is the USB2.0 interface.
3Chip test system according to claim 1 is characterized in that: described test board comprises chip Cy68013.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220084366 CN202815170U (en) | 2012-03-08 | 2012-03-08 | Chip test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220084366 CN202815170U (en) | 2012-03-08 | 2012-03-08 | Chip test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202815170U true CN202815170U (en) | 2013-03-20 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220084366 Expired - Lifetime CN202815170U (en) | 2012-03-08 | 2012-03-08 | Chip test system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202815170U (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102608520A (en) * | 2012-03-08 | 2012-07-25 | 无锡华大国奇科技有限公司 | Chip testing system based on USB-IIC (universal serial bus to inter-integrated circuit) protocol |
| CN103399835A (en) * | 2013-07-31 | 2013-11-20 | 龙迅半导体科技(合肥)有限公司 | Data communication method and system |
| CN106021056A (en) * | 2016-05-31 | 2016-10-12 | 四川九洲空管科技有限责任公司 | Automatic testing system and method for Arinc429 communication chip |
| WO2019056935A1 (en) * | 2017-09-20 | 2019-03-28 | 南京扬贺扬微电子科技有限公司 | Ft4222-based testing system and method for spi flash |
| CN111159720A (en) * | 2020-03-27 | 2020-05-15 | 深圳市芯天下技术有限公司 | System for testing RPMC |
-
2012
- 2012-03-08 CN CN 201220084366 patent/CN202815170U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102608520A (en) * | 2012-03-08 | 2012-07-25 | 无锡华大国奇科技有限公司 | Chip testing system based on USB-IIC (universal serial bus to inter-integrated circuit) protocol |
| CN103399835A (en) * | 2013-07-31 | 2013-11-20 | 龙迅半导体科技(合肥)有限公司 | Data communication method and system |
| CN106021056A (en) * | 2016-05-31 | 2016-10-12 | 四川九洲空管科技有限责任公司 | Automatic testing system and method for Arinc429 communication chip |
| CN106021056B (en) * | 2016-05-31 | 2018-07-13 | 四川九洲空管科技有限责任公司 | A kind of Arinc429 communication chips Auto-Test System and test method |
| WO2019056935A1 (en) * | 2017-09-20 | 2019-03-28 | 南京扬贺扬微电子科技有限公司 | Ft4222-based testing system and method for spi flash |
| CN111159720A (en) * | 2020-03-27 | 2020-05-15 | 深圳市芯天下技术有限公司 | System for testing RPMC |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: IC card chip and module chip testing system Effective date of registration: 20140825 Granted publication date: 20130320 Pledgee: Agricultural Bank of China Limited by Share Ltd Wuxi science and Technology Branch Pledgor: Wuxi Huada Guoqi Technology Co.,Ltd. Registration number: 2014990000698 |
|
| PLDC | Enforcement, change and cancellation of contracts on pledge of patent right or utility model | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20160810 Granted publication date: 20130320 Pledgee: Agricultural Bank of China Limited by Share Ltd Wuxi science and Technology Branch Pledgor: Wuxi Huada Guoqi Technology Co.,Ltd. Registration number: 2014990000698 |
|
| PLDC | Enforcement, change and cancellation of contracts on pledge of patent right or utility model | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130320 |