CN202548496U - Pixel array substrate - Google Patents

Abstract

The utility model discloses a pixel array substrate, which includes a substrate, a plurality of scanning lines, a plurality of data lines, a plurality of shared lines, a plurality of pixel units and a plurality of shielding electrodes. Scan lines, data lines and shared lines are all configured on the substrate. The data lines intersect with the scan lines to divide a plurality of pixel areas on the plane of the substrate. Each pixel unit is configured in one of the pixel areas and includes a pixel electrode. Each pixel electrode has a first side edge, and the first side edge located between two adjacent scan lines faces one of the scan lines. The shielding electrodes are respectively arranged in the pixel areas and located between the pixel electrodes and the substrate. Each shielding electrode protrudes from one of the first side edges and is electrically insulated from the sharing line, the scan line and the data line. When the pixel array substrate of the present invention is in operation, the picture quality can be reduced from being damaged due to the influence of the coupling capacitance.

Description

Pixel Array Substrate

technical field

The utility model relates to a display element, and in particular to a pixel array substrate.

Background technique

At present, some large-size or high-resolution liquid crystal displays (Liquid Crystal Display, LCD) have a large number of scan lines (scan lines), and this type of liquid crystal display will drive multiple adjacent scan lines at a time to turn on Multiple thin-film transistors (Thin-Film Transistor, TFT). This can increase the charging time of the liquid crystal capacitance (liquid crystal capacitance) corresponding to each pixel electrode (pixel electrode), thereby reducing the occurrence of insufficient charging of the liquid crystal capacitance.

In the above-mentioned liquid crystal display, each pixel electrode and its adjacent scanning lines will form a coupling capacitance, and the coupling capacitance will affect the gray scale voltage generated by the pixel electrode. When the liquid crystal display is in operation, some scan lines are driven to make some pixel electrodes generate grayscale voltages to charge the liquid crystal capacitors. However, at this time, there are still other scan lines that are not driven, so the amount of charges stored in the coupling capacitors is inconsistent. This may cause wrong grayscale voltages generated by the pixel electrodes, which may damage the picture quality of the LCD.

Utility model content

In view of this, the main purpose of the present invention is to provide a pixel array substrate that can reduce the influence of the coupling capacitance on the gray scale voltage.

To achieve the above purpose, the present invention proposes a pixel array substrate, which includes a substrate, multiple scanning lines, multiple data lines, multiple sharing lines, multiple pixel units, an insulating layer and multiple shielding electrodes. The substrate has a plane. The scan lines are juxtaposed with each other and arranged on the plane; the data lines are juxtaposed with each other and arranged on the plane; the data lines and the scan lines are interlaced to divide a plurality of pixel regions on the plane. The sharing line is juxtaposed with the scanning line and arranged on a plane. Each pixel unit is arranged in one of the pixel areas, and each pixel unit includes a pixel switch, a pixel electrode and a conductive column. The pixel switch is electrically connected to the scan line and the data line. The conductive column is connected between the pixel switch and the pixel electrode, wherein each pixel electrode has a first side edge, and the first side edge between two adjacent scanning lines faces one of the scanning lines. Wire. The insulation layer is arranged between the pixel electrode and the plane, and covers the scanning line, the data line, the sharing line and the pixel switch. The conductive column is configured in the insulating layer. The shielding electrodes are respectively arranged in the pixel regions and located between the pixel electrodes and the plane. The shielding electrodes partially overlap with the pixel electrodes respectively, wherein each shielding electrode protrudes from one of the first side edges, and the shielding electrodes are electrically connected to the sharing line, the scanning line and the data line. insulation.

In an embodiment of the present invention, the pixel array substrate further includes a protection layer. The protective layer is disposed between the plane and the insulating layer, and covers the scanning line and the sharing line, wherein the shielding electrode is disposed between the protective layer and the insulating layer.

In an embodiment of the present invention, the number of shielding electrodes in each pixel area is one.

In an embodiment of the present invention, the number of shielding electrodes in each pixel area is multiple.

In an embodiment of the present invention, each pixel electrode further has a pair of second side edges opposite to each other, and the first side edge is connected between the two second side edges. One of the shielding electrodes in the same pixel area protrudes from the two second side edges.

In an embodiment of the present invention, the pixel array substrate further includes a plurality of capacitive electrodes. The capacitive electrodes are respectively arranged in the pixel area and connected to the sharing line. The insulating layer further covers the capacitive electrodes, and each capacitive electrode partially overlaps with one of the pixel electrodes.

In an embodiment of the present invention, each pixel electrode further has a pair of second side edges opposite to each other, and the first side edge is connected between the two second side edges. Each capacitor electrode protrudes from one of the second side edges.

In an embodiment of the present invention, there are multiple capacitive electrodes in each pixel area.

In an embodiment of the present invention, each sharing line has two opposite sides, and the capacitor electrode protrudes from one side of the sharing line.

In an embodiment of the present invention, each of the sharing lines has two opposite sides, and the capacitor electrode protrudes from the sides of the sharing line.

In an embodiment of the present invention, the number of shielding electrodes in each pixel area is multiple. In the same pixel area, the capacitive electrodes are located between the shielding electrodes.

In an embodiment of the present invention, each pixel electrode further has a pair of second side edges opposite to each other, and the first side edge is connected between the two second side edges. The shapes of the shielding electrodes are ring-shaped, and each shielding electrode protrudes from the first side edge and the two second side edges of one of the pixel electrodes.

Based on the above, when the pixel array substrate of the present invention is in operation, the shielding electrode can generate an electric field shielding effect, thereby reducing the effect of the coupling capacitance formed by the pixel electrode and the scanning line on the gray scale voltage. In order to reduce the situation that the picture quality is damaged due to the influence of the coupling capacitance.

Description of drawings

FIG. 1A is a schematic top view of a pixel array substrate according to an embodiment of the present invention;

Fig. 1B is a schematic sectional view drawn along the I-I line section in Fig. 1A;

2 is a schematic top view of a pixel array substrate according to another embodiment of the present invention;

FIG. 3 is a schematic top view of a pixel array substrate according to another embodiment of the present invention.

Explanation of reference signs

100, 200, 300 pixel array substrate

110 Substrate

112 plane

120c shared line

120d data cable

120s scan line

130 pixel units

132 pixel switch

134 pixel electrodes

136 conductive column

140 insulation layer

150, 350 shaded electrodes

160 layers of protection

170, 270 Capacitive electrodes

C1 channel layer

D1 drain

E1 first side edge

E2 Second side edge

E3 side

G1 Gate

P1 pixel area

S1 source.

Detailed ways

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific examples are given together with the accompanying drawings and described in detail as follows.

FIG. 1A is a schematic top view of a pixel array substrate according to an embodiment of the present invention, and FIG. 1B is a schematic cross-sectional view drawn along line I-I in FIG. 1A . Please refer to FIG. 1A and FIG. 1B , the pixel array substrate 100 of this embodiment includes a substrate 110 , a plurality of scanning lines 120s, a plurality of data lines 120d and a plurality of sharing lines 120c. The substrate 110 has a plane 112 , and the scan lines 120s , data lines 120d and sharing lines 120c are all disposed on the plane 112 .

The data lines 120d are juxtaposed with each other, and the scan lines 120s are juxtaposed with each other, wherein the data lines 120d and the scan lines 120s are interlaced to divide a plurality of pixel regions P1 on the plane 112 . In detail, the data lines 120d and the scan lines 120s are arranged in a grid, thereby forming a plurality of lattices, wherein the lattices are pixel regions P1, as shown in FIG. 1A .

The sharing line 120c is parallel to the scanning line 120s, and each scanning line 120s may be located between two adjacent sharing lines 120c, so the sharing line 120c may pass through a plurality of pixel regions P1. In addition, both the sharing line 120c and the scanning line 120s may be made of the same film layer. For example, both the sharing line 120c and the scanning line 120s can be formed by the same metal layer after photolithography and etching. Therefore, the materials constituting both the sharing line 120c and the scanning line 120s can be the same.

The pixel array substrate 100 further includes a plurality of pixel units 130 and an insulating layer 140 (as shown in FIG. 1B ). Each pixel unit 130 is disposed in one of the pixel regions P1 and includes a pixel switch 132 , a pixel electrode 134 and a conductive column 136 . The insulating layer 140 is disposed between the pixel electrode 134 and the plane 112, and covers the scanning line 120s, the data line 120d, the sharing line 120c and the pixel switch 132, and the sharing line 120c partially overlaps the pixel electrode 134, as shown in FIG. 1A . The conductive column 136 is disposed in the insulating layer 140 and connected between the pixel switch 132 and the pixel electrode 134 so that the pixel switch 132 is electrically connected to the pixel electrode 134 .

The pixel switch 132 is electrically connected to the scan line 120s and the data line 120d. In detail, each pixel switch 132 may be a field-effect transistor (Field-Effect Transistor, FET), and may include a source S1, a drain D1, a gate G1, and a channel layer C1, wherein the source S1, Both the drain D1 and the channel layer C1 are located above the gate G1 , and the channel layer C1 is located between the gate G1 and the source S1 , and between the gate G1 and the drain D1 . In addition, the channel layer C1 may be a semiconductor layer.

In the same pixel unit 130, the gate G1 is connected to the scan line 120s, and can be integrally formed with the scan line 120s. In detail, both the gate G1 and the scan line 120s can be made of the same film layer, for example, both the gate G1 and the scan line 120s can be formed by the same metal layer after lithography and etching. The source S1 is connected to the data line 120d, and the drain D1 is connected to the conductive pillar 136 .

When the scan lines 120s are driven, the pixel switches 132 electrically connected to the driven scan lines 120s are turned on. At this time, the grayscale signal output by the data line 120d is input to the source S1 of the turned-on pixel switch 132 , and passes through the channel layer C1 , the drain D1 and the conductive column 136 in sequence. Afterwards, the grayscale signal is transmitted to the pixel electrode 134 to generate a grayscale voltage.

The pixel array substrate 100 further includes a plurality of shielding electrodes 150 , wherein the shielding electrodes 150 are respectively disposed in the pixel region P1 and located between the pixel electrodes 134 and the plane 112 (as shown in FIG. 1B ). In addition, in the embodiment shown in FIG. 1A , the number of the shielding electrode 150 in each pixel region P1 may be only one.

The shielding electrodes 150 partially overlap with the pixel electrodes 134 respectively. Each pixel electrode 134 has a first side edge E1 and a pair of second side edges E2 opposite to each other. In each pixel electrode 134 , the first side edge E1 is connected between the second side edges E2 , and each shielding electrode 150 protrudes from one of the first side edges E1 .

The shielding electrodes 150 are electrically insulated from the sharing line 120c, the scanning line 120s and the data line 120d, and the first side edge E1 between two adjacent scanning lines 120s faces therein. One scanning line 120s, so the shielding electrode 150 is disposed between one of the scanning lines 120s and one of the pixel electrodes 134 .

Both the pixel electrode 134 and the scanning line 120s facing the first side edge E1 will form a coupling capacitance that affects the gray scale voltage, but the shielding electrode 150 can generate an electric field shielding effect in the coupling capacitance, thereby reducing the impact of the above coupling capacitance on the gray scale voltage. The influence of the voltage prompts the pixel electrode 134 to generate a suitable grayscale voltage, so as to reduce the situation that the picture quality is damaged due to the influence of the coupling capacitance.

In addition, the pixel array substrate 100 may further include a protection layer 160, as shown in FIG. 1B. The protective layer 160 is disposed between the plane 112 and the insulating layer 140, and covers the scanning line 120s and the sharing line 120c, and the shielding electrode 150 and the source S1 and the drain D1 of the pixel switch 132 can be It is disposed between the protective layer 160 and the insulating layer 140 . The shielding electrode 150, the source S1 and the drain D1 can be made of the same film layer, for example, the same metal layer is formed by lithography and etching, thus forming the shielding electrode 150, the source S1 and the drain D1. The materials of the three drains D1 may be the same.

In this embodiment, the pixel array substrate 100 may further include a plurality of capacitive electrodes 170, wherein the capacitive electrodes 170 are respectively arranged in the pixel region P1, and the number of capacitive electrodes 170 in each pixel region P1 may be as many as indivual. Taking FIG. 1A as an example, there are two capacitive electrodes 170 in each pixel area P1. In addition, each capacitive electrode 170 is located below the pixel electrode 134 and partially overlaps the pixel electrode 134 , wherein each capacitive electrode 170 protrudes from one of the second side edges E2 .

The capacitive electrode 170 may be disposed on the plane 112, and the capacitive electrode 170 and the sharing line 120c may be made of the same film layer. For example, both the capacitive electrode 170 and the sharing line 120c can be formed by the same metal layer after lithography and etching, so the materials constituting the capacitive electrode 170 and the sharing line 120c can be the same, and the insulating layer 140 It further covers the capacitive electrode 170 . In addition, since the scanning line 120s and the sharing line 120c can be made of the same film layer, the capacitive electrode 170 , the scanning line 120s and the sharing line 120c can be made of the same film layer.

The capacitor electrode 170 is connected to the sharing line 120c, so that the capacitor electrode 170 is electrically connected to the sharing line 120c to which it is connected. In the embodiment shown in FIG. 1A, each sharing line 120c has two opposite sides E3, and the capacitor electrode 170 protrudes from one side E3 of the sharing line 120c. In other words, in the same shared line 120c, the plurality of capacitive electrodes 170 are only connected to one side E3, but not to the other side E3.

Since the sharing line 120c and the capacitor electrode 170 overlap the pixel electrode 134, the sharing line 120c, the capacitor electrode 170 and the pixel electrode 134 in the same pixel region P1 can form a storage capacitor (storage) for maintaining the gray scale voltage. capacities, also known as Cst). In addition, the above-mentioned storage capacitor may be a storage capacitor (Cs on common) configured on a shared line.

FIG. 2 is a schematic top view of a pixel array substrate according to another embodiment of the present invention. Please refer to FIG. 2, the pixel array substrate 200 of this embodiment is similar in structure to the pixel array substrate 100, and has the same effect. For example, the pixel array substrate 200 also includes elements such as scanning lines 120s, data lines 120d, sharing lines 120c, and pixel units 130. , and the cross-sectional structures of the pixel array substrates 200 and 100 are very similar. Therefore, the following will mainly introduce the differences between the pixel array substrates 100 and 200 , and only describe in detail with reference to FIG. 2 , and will not repeat the same technical features and functions.

Differences between the pixel array substrates 100 and 200 include the number of shielding electrodes 150 in each pixel region P1 and the connection between the plurality of capacitive electrodes 270 and the plurality of sharing lines 120c included in the pixel array substrate 200 . In detail, in this embodiment, the number of shielding electrodes 150 in each pixel region P1 is multiple, and in the same pixel region P1, one of the shielding electrodes 150 protrudes from the two second sides of the pixel electrode 134 edge E2, and another shielding electrode 150 protrudes from the first side edge E1.

Each capacitive electrode 270 is located below the pixel electrode 134, and both the capacitive electrode 270 and the sharing line 120c can be made of the same film layer. The capacitor electrodes 270 partially overlap the pixel electrodes 134 , wherein each capacitor electrode 270 protrudes from one of the second side edges E2 . In addition, in the same pixel area P1, the capacitive electrode 270 may be located between the shielding electrodes 150, as shown in FIG. 2 .

The connection mode between the capacitor electrode 270 and the sharing line 120c is different from the connection mode between the capacitor electrode 170 and the sharing line 120c in the foregoing embodiments. In detail, in this embodiment, the capacitor electrode 270 protrudes from two sides E3 of the sharing line 120c. That is to say, in the same shared line 120c, some capacitive electrodes 270 are connected to one side E3, while other capacitive electrodes 270 are connected to the other side E3, as shown in FIG. 2 .

FIG. 3 is a schematic top view of a pixel array substrate according to another embodiment of the present invention. Please refer to FIG. 3, the pixel array substrate 300 of this embodiment is similar to the pixel array substrate 100, for example, the pixel array substrate 300 also includes scanning lines 120s, data lines 120d, sharing lines 120c and pixel units 130, and the pixel array substrates 300, 100 The cross-sectional structures of the two are very similar, so the following will mainly introduce the differences between the pixel array substrates 100 and 300, and will not repeat the same technical features and functions of the two, nor will the cross-sectional structure of the pixel array substrate 300 be shown, but A detailed description will be given only in conjunction with FIG. 3 .

In detail, the main difference between the pixel array substrates 300 and 100 is that the plurality of shielding electrodes 350 included in the pixel array substrate 300 are all ring-shaped, and each shielding electrode 350 not only partially overlaps with one of the pixel electrodes 134 , and protrude from the first side edge E1 and the two second side edges E2 of the pixel electrode 134 , as shown in FIG. 3 .

In addition, in the embodiment shown in FIG. 3 , the pixel array substrate 300 may not include any capacitive electrodes 170 , 270 in the foregoing embodiments. However, the sharing line 120c still partially overlaps the pixel electrode 134, so even if the pixel array substrate 300 does not include any capacitive electrodes 170, 270, both the sharing line 120c and the pixel electrode 134 in the same pixel region P1 can still be used to maintain gray. storage capacitor for step voltage.

To sum up, the shielding electrodes included in the pixel array substrate of the present invention can generate an electric field shielding effect in the coupling capacitance formed by the pixel electrodes and the scanning lines. In this way, the utility model can reduce the influence of the coupling capacitor on the gray scale voltage, and promote the pixel electrode to generate a suitable gray scale voltage, so as to reduce the situation that the picture quality is damaged due to the influence of the coupling capacitor.

Although the utility model is disclosed above with the foregoing embodiments, it is not intended to limit the utility model. Any person familiar with the similar technology can make equivalent replacements for changes and modifications without departing from the spirit and scope of the utility model. Still within the scope of patent protection of the utility model.

Claims (12)

1. pixel array substrate is characterized in that it comprises:

One substrate has a plane;

The multi-strip scanning line, arranged side by side each other, and be configured on this plane;

Many data lines, arranged side by side each other, and be configured on this plane, said data line and said sweep trace are staggered, on this plane, mark off a plurality of picture elements zone;

Many common lines, arranged side by side with said sweep trace, and be configured on this plane;

A plurality of picture elements unit; Respectively this picture element configuration of cells is therein in picture element zone; Each picture element unit comprises a picture element switch, a pixel electrode and a conductive pole, and said picture element switch electrically connects said sweep trace and said data line, and said conductive pole is connected between said picture element switch and the said pixel electrode; Wherein respectively this pixel electrode has a first side edge, and the said first side edge between adjacent two sweep traces is all towards sweep trace wherein;

One insulation course is configured between said pixel electrode and this plane, and covers said sweep trace, said data line, said common lines and said picture element switch, and wherein said conductive pole is configured in this insulation course; And

A plurality of shielding electrodes; Be configured in respectively in the said picture element zone; And between said pixel electrode and this plane; Said shielding electrode is overlapped with said pixel electrode respectively, and wherein respectively this shielding electrode protrudes from one of them first side edge, and said shielding electrode all is electrically insulated with said common lines, said sweep trace and said data line.

2. pixel array substrate as claimed in claim 1; It is characterized in that; This pixel array substrate more comprises a protective seam; This protective seam is configured between said plane and the said insulation course, and covers said sweep trace and common lines, and wherein said shielding electrode is configured between this protective seam and the said insulation course.

3. pixel array substrate as claimed in claim 1 is characterized in that, the quantity of the said shielding electrode in each said picture element zone is one.

4. pixel array substrate as claimed in claim 1 is characterized in that, the quantity of the said shielding electrode in each said picture element zone is a plurality of.

5. pixel array substrate as claimed in claim 4; It is characterized in that; Each said pixel electrode has more a pair of second side respect to one another edge; And said first side edge is connected between these two second side edge, and one of them shielding electrode in the same picture element zone protrudes from this two second side edge.

6. pixel array substrate as claimed in claim 1; It is characterized in that; This pixel array substrate more comprises a plurality of capacitance electrodes, and said capacitance electrode is configured in respectively in the said picture element zone, and connects said common lines; Said insulation course more covers said capacitance electrode, and respectively this capacitance electrode and one of them pixel electrode are overlapped.

7. pixel array substrate as claimed in claim 6; It is characterized in that; Each said pixel electrode has more a pair of second side respect to one another edge, and said first side edge is connected between these two second side edge, and each said capacitance electrode protrudes from one of them second side edge.

8. pixel array substrate as claimed in claim 6 is characterized in that, the quantity of the said capacitance electrode in each said picture element zone is a plurality of.

9. pixel array substrate as claimed in claim 6 is characterized in that, each said common lines has relative dual side-edge, and said capacitance electrode protrudes from one of them side of said common lines.

10. pixel array substrate as claimed in claim 6 is characterized in that, each said common lines has relative dual side-edge, and said capacitance electrode protrudes from the said side of said common lines.

11. pixel array substrate as claimed in claim 10 is characterized in that, the quantity of the said shielding electrode in each said picture element zone is a plurality of, and in same picture element zone, said capacitance electrode is between said shielding electrode.

12. pixel array substrate as claimed in claim 1; It is characterized in that; Each said pixel electrode has more a pair of second side respect to one another edge; And said first side edge is connected between these two second side edge, and the shape of said shielding electrode is annular, and each said shielding electrode protrudes from said first side edge and this two second side edge of one of them pixel electrode.

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