CN202535324U - Switch circuit - Google Patents
Switch circuit Download PDFInfo
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- CN202535324U CN202535324U CN2011205782609U CN201120578260U CN202535324U CN 202535324 U CN202535324 U CN 202535324U CN 2011205782609 U CN2011205782609 U CN 2011205782609U CN 201120578260 U CN201120578260 U CN 201120578260U CN 202535324 U CN202535324 U CN 202535324U
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- 238000007599 discharging Methods 0.000 claims description 7
- 230000003247 decreasing effect Effects 0.000 claims description 2
- 238000004088 simulation Methods 0.000 abstract description 6
- 230000007704 transition Effects 0.000 description 24
- 101100102627 Oscarella pearsei VIN1 gene Proteins 0.000 description 5
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- 238000010586 diagram Methods 0.000 description 3
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- 238000006731 degradation reaction Methods 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012958 reprocessing Methods 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
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- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
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Abstract
The utility model discloses a switch circuit, comprising a first input stage, a second input stage and output nodes, wherein the first input stage comprises an input end for receiving a first input signal, an output end, and a power supply terminal for receiving increased simulation electric currents; the second input stage comprises an input end for receiving a second input signal, an output end, and a power supply terminal for receiving reduced simulation electric currents; and the output nodes are coupled to output ends of the first input stage and the second input stage to provide switch output signals. An output stage is coupled between the first and the second input stages and the output nodes. The first and the second input stages are computing amplifiers.
Description
Technical field
The utility model relates to analog switching circuit, and relates more particularly to have the soft ON-OFF control circuit of simulation of accurate current steering generator.
Background technology
The classical execution mode of the switch between two signal V1 and the V2 can be the direct switch with logic control shown in the circuit 100 of Fig. 1.Use two cmos switch S1 and S2, and come it is controlled by reverse logic control signal (CTRL and the anti-phase CTRL through inverter 102).Make signal V1 or V2 through operational amplifier 104, so that VOUT output signal to be provided.If two signals have various signals voltage, then will there be jump (jump) or step (step) at output point 106 places.In some applications, this jump or the step of output signal possibly have problems.For example, in voice applications, if the output signal gets into loud speaker, then jumping to produce the pop noise of not expecting (pop-noise) at the loud speaker place.In this case, the smooth transition between two input signals clearly is preferred.
The conventional digital solution 200 of the smooth transition between the switch input signal is used resistor networks 212 and 214 and switching network 216 and 218 accordingly, and big step is divided into little step, and is as shown in Figure 2.Circuit 200 comprises and is used to second input that receives the input of the first input signal V1 and be used to receive the second input signal V2.Circuit 200 also comprises output operational amplifier or buffer 204, soft switch clock generator 206, switch counter 208 and logic controller 210.Circuit 200 also comprises final reprocessing low pass filter 220 usually.Number and soft switching time through increasing little step, reduced pop noise.In solution shown in Figure 2, resistor and parasitic element will owing to the noise that increases and total harmonic distortion (THD) make performance degradation.For some configuration of step number and soft switching time, generated the audio tones of non-expectation.Need low pass filter to remove the high-frequency digital spike that is associated with circuit 200.Digital circuit 200 shown in Figure 2 has been showed between pop noise and the consideration of other performance and has been difficult to weigh.
Therefore, desired is the simple analog switching circuit that is used to provide two smooth transitions between the input signal, and without any need for reprocessing or filtering, does not perhaps use complicated digital circuit.
The utility model content
According to the utility model, showed signal switching circuit and method based on the analog current transition, it can be used for switching to another signal with transition stably from a signal in many application (for example voice applications).
Switching circuit comprises first input stage of power supply terminal that has input, the output that is used to receive first input signal and be used to receive the analog current of increase; Have input, output that is used to receive second input signal and second input stage of the power supply terminal that is used to receive the analog current that reduces, and be coupled to the output of first input stage and second input stage so that the output node of switch output signal is provided.Output stage is between first and second input stages and output node.In first and second input stages each comprises operational amplifier.
According to the embodiment of the utility model, switching circuit can comprise the current feedback circuit that is used for the receive clock signal and is used to generate charging current and discharging current, be used to receive charging and discharging current and be used to provide control voltage voltage generator, be used to receive control voltage and be used to that the electric current and voltage generator of first analog current and second analog current is provided and be used for the combination of first and second analog signals and be used to provide the amplifier stage of switch output signal.
Current feedback circuit comprise have by clock signal carry out the input of switch first and second integrators, have by clock signal carry out switch output two auxiliary voltage current feedback circuits and have first and second current mirrors that carry out the input of switch by clock signal.
Voltage generator comprises first and second current mirrors, receives two additional clock signals and comprises load capacitor.
The electric current and voltage generator comprises the differential amplifier and first and second current mirrors that are used to receive control voltage, reference voltage and are used to provide first and second analog currents.
Amplifier stage comprises first and second input stages and the output stage that is coupled to the output of first and second input stages.In the level each can comprise operational amplifier or buffer.
According to the utility model, first analog current comprises the analog current that increases to second value from first value, and second analog current comprises the analog current that is decreased to first value from second value.
Description of drawings
Fig. 1 is the sketch map of prior art switching circuit and respective switch waveform;
Fig. 2 is the sketch map of prior art digital switch circuit and respective switch waveform;
Fig. 3 is the sketch map according to the switching circuit of the utility model;
Fig. 4 is the simulation result according to the signal jump transition of the DC input of the utility model;
Fig. 5 is the simulation result according to signal decline (drop) transition of the DC input of the utility model; And
Fig. 6 is the simulation result according to the signal transition of the sine wave input of the utility model.
Embodiment
According to the switching circuit of the utility model and method the smooth transition in the switch that is implemented between the input signal is provided but has not had the novel manner of the shortcoming of being mentioned of traditional prior art solution.According to the utility model, easement curve is very stably and can accurately controls.Related side's block diagram according to the circuit of the utility model has been shown in Fig. 3.
The block diagram of circuit 300 comprises four parts:
The 3rd part is a voltage current adapter 306; And
The 4th part is the amplifier stage 308 that is used to realize the smooth transition of signaling switch.
In the 4th part, control signaling switch from VIN1 to VIN2 by operational amplifier input stage current transition.An input stage electric current I _ N becomes zero from I0, and another input stage electric current I _ P becomes I0 from zero.Therefore, the output signal becomes VIN2 from VIN1 reposefully.The positive input terminal of I_N input stage receives the VIN1 input voltage, and the positive input terminal of I_P input stage receives the VIN2 input voltage.As shown, negative input end is coupling in together, and is coupled to the output of output stage.Output stage buffer switch signal is to provide OUTPUT switching voltage.
In part 1, use clock signal clk controlling two integrators, and the electric current generation of electric current I 1 and I2 is provided with configurable frequency and duty ratio.OPAMP1, switch S 1 and capacitor C1 and C2 comprise first switched capacitor integrator.OPAMP2, switch S 3 and capacitor C3 and C4 comprise second switch capacitor integrator.When switch S 1 during in leftward position, will charge to second voltage VTH with voltage V_int from the first voltage VTL through capacitor C1 and Cint in right positions and switch S 2 with charging current I1.When switch S 1 is transferred to leftward position and switch S 2 when being transferred to right positions, capacitor C1 is coupled to the negative input end of OPAMP1.Be stored in V_int voltage on the capacitor C1 before value will be compared with VTH voltage, and first switched capacitor integrator will adjust to next charging current I1, charged to VTH exactly until V_int voltage.
When switch S 3 is transferred to right positions and switch S 4 when being transferred to leftward position, will through capacitor C3 and Cint voltage V_int be discharged to VTL from VTH with discharging current I2.When switch S 3 is transferred to leftward position and switch S 4 when being transferred to right positions, capacitor C3 is coupled to the negative input end of OPAMP2, be stored on the capacitor C3 before V_int voltage will compare with VTL.Second switch capacitor integrator will be adjusted to next discharging current I2, will be discharged to VTL exactly until V_int.
Therefore the current feedback circuit 302 of part 1 comprises like shown two integrators, two voltage current adapters and two current mirror CURRMIRROR1 and CURRMIRROR2.
Two switched capacitor integrator with from two mutually under the control of non-overlapping clock of CLK; V_int will generate triangular voltage; It fluctuates between VTH and VTL; Its charge will be judged by the CLK frequency, and define its charge ratio by CLK duty ratio D (D=0 to 1).Here, will adjust charging current I1 and discharging current I2 is constant until it.
In part 2, the fixed current benchmark I1 of part 1 will become electric current I 3 and I4 by configurable ratio mirror image for 1/M with I2.Current mirror CURRMIRROR3 and CURRMIRROR4 are used for this purpose.To come voltage Vcon is carried out charge or discharge with I4 by electric current I 3.Load capacitor N*Cint is configurable.
Can select PCLK and NCLK as follows:
I3=I1/M; If PCLK is pulse duration=N*M*D/fCLK, then Vcon will charge to VTH from VTL exactly under PCLK pulse control.
I4=I2/M; If NCLK is pulse duration=N*M* (1-D)/fCLK, then Vcon will be discharged to VTL from VTH exactly under NCLK pulse control.
When the optional ratio with M and N applies PCLK and NCLK, will be in PCLK and NCLK ask regularly be discharged to VTL or charge to VTH and obtain the Vcon voltage-transition from VTL from VTH.
In the 3rd part, transistor M1 and M2 comprise that the source-coupled transistor with source-electrode degradation is to (resistor R 1 and R2 receive bias current Io).Vcon voltage will be applied in the M1 gate input, and it will generate difference current to I_P and I_N.Through current mirror CURRMIRROR5 and CURRMIRROR6 electric current is carried out mirror image.
Judge the current transition time by PCLK and NCLK pulse duration.Define this width by N (number of capacitor Cint), M (the current mirror factor of current mirror CURRMIRROR3 and CURRMIRROR4), the duty ratio of CLK signal and the frequency of CLK signal.Can realize wide timing range by the existence of all these settings.Therefore, transition is regularly irrelevant with technology, the influence that it will not be changed by resistor and capacitor will.
Fig. 4 and Fig. 5 are the timing diagrams that two smooth transitions between the DC input signal are shown.
In Fig. 4; The top of figure illustrates the PCLK signal; The middle part of figure is illustrated in the smooth transition of the Vcon voltage between the first voltage VTL and the second voltage VTH, and the bottom of figure is illustrated in the smooth transition of the output signal between first input voltage VIN 1 and second input voltage VIN 2.Therefore Fig. 4 illustrates and wherein between the DC input voltage signal, has the switch that increases (step up) gradually.
In Fig. 5; The top of figure illustrates the NCLK signal; The middle part of figure is illustrated in the smooth transition of the Vcon voltage between the first voltage VTH and the second voltage VTL, and the bottom of figure is illustrated in the smooth transition of the output signal between first input voltage VIN 2 and second input voltage VIN 1.Therefore Fig. 5 illustrates and wherein between the DC input voltage signal, has the switch that reduces (step down) gradually.
Fig. 6 is illustrated in two smooth transitions between the sinusoidal wave input.
In Fig. 6, first and the top section of figure illustrate NCLK and PCLK signal.The second portion of figure is illustrated in smooth transition between the first voltage VTL and the second voltage VTH and Vcon voltage that turn back to VTL voltage.The third part of figure illustrates sinusoidal wave input voltage VIN 1 and VIN2.The 4th and the base section of figure are illustrated between the first input sine wave voltage VIN1 and the second input sine wave voltage VIN2 and smooth transition that return the output signal that drops to the VIN1 sine voltage subsequently.Therefore Fig. 6 illustrates the steady switch that is input to another sine voltage input and turns back to the input of primary sinusoid voltage from a sine voltage.
Therefore, according to the utility model, the stationary signal switch by operational amplifier analog current transition control is provided.Recently accurately control the reference current transition regularly by clock frequency and duty.Can realize large-scale transit time through N (number of capacitors) and M (the current mirror factor) are set.The circuit of the utility model does not receive the high-frequency digital The noise basically, and need not carry out filtering to output stage voltage.Switch transit time and irrelevant in technology (resistor and capacitor) variation.The circuit of the utility model is realized easily and is had an economic benefit.
Therefore, under the situation of spirit that does not break away from the utility model or scope, can carry out various modifications and change the utility model be tangible for a person skilled in the art.Therefore, if modification of the utility model and change are within the scope of the appended claims, then intention is that the utility model covers this modification and change.
Claims (17)
1. a switching circuit is characterized in that, said switching circuit comprises:
First input stage, it has input, the output that is used to receive first input signal and is used to receive the power supply terminal of the analog current of increase;
Second input stage, it has input, output that is used to receive second input signal and the power supply terminal that is used to receive the analog current that reduces; And
Output node, its said output that is coupled to said first input stage and said second input stage is so that provide switch output signal.
2. switching circuit according to claim 1 is characterized in that, said switching circuit also comprises the output stage between said first and second input stages and said output node.
3. switching circuit according to claim 1 is characterized in that, each in said first and second input stages comprises operational amplifier.
4. a switching circuit is characterized in that, said switching circuit comprises:
Current feedback circuit, it is used for the receive clock signal, and is used to generate charging current and discharging current;
Voltage generator, it is used to receive said charging and discharging current, and is used to provide control voltage;
The electric current and voltage generator, it is used to receive said control voltage, and is used to provide first analog current and second analog current; And
Amplifier stage, it is used for said first and second analog currents combination, and is used to provide switch output signal.
5. switching circuit according to claim 4 is characterized in that said current feedback circuit comprises first and second integrators.
6. switching circuit according to claim 5 is characterized in that, said first and second integrators comprise the input that is carried out switch by said clock signal.
7. switching circuit according to claim 4 is characterized in that, said current feedback circuit comprises two additional electric current and voltage generators.
8. switching circuit according to claim 7 is characterized in that, said additional electric current and voltage generator comprises the output that is carried out switch by said clock signal.
9. switching circuit according to claim 4 is characterized in that said current feedback circuit comprises first and second current mirrors.
10. switching circuit according to claim 9 is characterized in that, said first and second current mirrors comprise the input that is carried out switch by said clock signal.
11. switching circuit according to claim 4 is characterized in that, said voltage generator comprises first and second current mirrors.
12. switching circuit according to claim 4 is characterized in that, said voltage generator receives two additional clock signals.
13. switching circuit according to claim 4 is characterized in that, said voltage generator comprises load capacitor.
14. switching circuit according to claim 4 is characterized in that, said electric current and voltage generator comprises and is used to the differential amplifier that receives said control voltage, reference voltage and be used to provide said first and second analog currents.
15. switching circuit according to claim 4 is characterized in that, said electric current and voltage generator comprises first and second current mirrors.
16. switching circuit according to claim 4 is characterized in that, said amplifier stage comprises first and second input stages and the output stage that is coupled to the output of said first and second input stages.
17. switching circuit according to claim 4 is characterized in that, said first analog current comprises the analog current that increases to second value from first value, and said second analog current comprises the analog current that is decreased to said first value from said second value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205782609U CN202535324U (en) | 2011-12-31 | 2011-12-31 | Switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205782609U CN202535324U (en) | 2011-12-31 | 2011-12-31 | Switch circuit |
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| Publication Number | Publication Date |
|---|---|
| CN202535324U true CN202535324U (en) | 2012-11-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011205782609U Withdrawn - After Issue CN202535324U (en) | 2011-12-31 | 2011-12-31 | Switch circuit |
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| Country | Link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187958A (en) * | 2011-12-31 | 2013-07-03 | 意法半导体研发(深圳)有限公司 | Analog signal soft-switching control circuit with precise current guiding generator |
| CN103187958B (en) * | 2011-12-31 | 2016-12-14 | 意法半导体研发(深圳)有限公司 | There is precision current and guide the analogue signal soft switch control circuit of generator |
-
2011
- 2011-12-31 CN CN2011205782609U patent/CN202535324U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187958A (en) * | 2011-12-31 | 2013-07-03 | 意法半导体研发(深圳)有限公司 | Analog signal soft-switching control circuit with precise current guiding generator |
| CN103187958B (en) * | 2011-12-31 | 2016-12-14 | 意法半导体研发(深圳)有限公司 | There is precision current and guide the analogue signal soft switch control circuit of generator |
| CN106603056A (en) * | 2011-12-31 | 2017-04-26 | 意法半导体研发(深圳)有限公司 | Analog signal soft switching control circuit with precise current steering generator |
| CN106603056B (en) * | 2011-12-31 | 2020-02-28 | 意法半导体研发(深圳)有限公司 | Analog signal soft switch control circuit with accurate current steering generator |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20121114 Effective date of abandoning: 20200228 |