CN202486648U - Reference voltage source starting circuit - Google Patents
Reference voltage source starting circuit Download PDFInfo
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- CN202486648U CN202486648U CN 201220102082 CN201220102082U CN202486648U CN 202486648 U CN202486648 U CN 202486648U CN 201220102082 CN201220102082 CN 201220102082 CN 201220102082 U CN201220102082 U CN 201220102082U CN 202486648 U CN202486648 U CN 202486648U
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Abstract
The application discloses a reference voltage source starting circuit which comprises a first image current source circuit, a starting unit, a third PMOS (P-channel Metal Oxide Semiconductor) tube and a fourth PMOS tube, wherein the first image current source circuit comprises a first NMOS (N-channel Mental-oxide-semiconductor) tube and a second NMOS tube. The first image current source circuit is adopted to obtain a current on a switch tube in the reference voltage source circuit and to control the working state of the starting unit; specifically, when the switch tube in the reference voltage source circuit is closed, which means that the reference voltage source circuit is operating within a dead zone, the current in the image current source circuit is 0, and at the moment the starting unit is started, and the current of the starting unit is acted to separate the switch tube in the reference voltage source current from the dead zone; the circuit is simply structured, and can avoid the problem of failing to be started due to an excessively high threshold of the first NMOS tube, therefore, the reference voltage source starting circuit is applied to the reference voltage source circuit under the combined use of high-low voltage technological devices, along with high reliability.
Description
Technical field
The utility model relates to a kind of reference voltage source start-up circuit, belongs to the Analogous Integrated Electronic Circuits design field.
Background technology
In Analogous Integrated Electronic Circuits and mixed-signal circuit design field, reference voltage source is a very important circuit module, for system provides voltage reference and current reference.Yet; Most of reference voltage source circuits generally have two workspaces when working, and the one, normal operation region, all MOS of reference voltage source main body circuit (metal oxid semiconductor; Metal-oxide semiconductor (MOS)) FET all is operated in the saturation region, exports normal reference voltage; Another is the dead band, and reference voltage source main body circuit part metal-oxide-semiconductor is operated in cut-off region, the reference voltage of output error.So, in design, how to avoid reference voltage source circuit to get into the dead band with regard to becoming the problem that must solve, therefore relate to the design of start-up circuit.
The utility model content
For solving the problems of the technologies described above, the application embodiment provides a kind of reference voltage source start-up circuit, to realize the adopting simple reference voltage source start-up circuit of circuit structure that reference voltage source circuit is broken away from the dead band, gets into the operate as normal district, and technical scheme is following:
The application provides a kind of reference voltage source start-up circuit; Be applied to reference voltage source circuit; Comprise: the first image current source circuit, start unit, PMOS pipe, the 3rd PMOS pipe and the 4th PMOS that are made up of NMOS pipe and the 2nd NMOS pipe manage, wherein:
The control end of said start unit is connected with the drain electrode of NMOS pipe and the drain electrode of PMOS pipe respectively; The output terminal of said start unit connects said reference voltage source circuit; When said reference voltage source circuit gets into the dead band, drive said reference voltage source circuit and break away from the dead band;
The source electrode of the one PMOS pipe is connected with supply voltage, and grid connects earth terminal;
The source electrode of the one NMOS pipe connects earth terminal, and grid is connected with drain electrode with the grid of the 2nd NMOS pipe respectively;
The source electrode of the 2nd NMOS pipe connects earth terminal; Drain electrode is connected with the drain electrode of the 4th PMOS pipe; The source electrode of the 4th PMOS pipe is connected with the drain electrode of the 3rd PMOS pipe; The source electrode of the 3rd PMOS pipe is connected with supply voltage, and the 4th gate pmos utmost point, the 3rd gate pmos utmost point link to each other with reference voltage source circuit respectively, to obtain the main body branch current PTAT electric current in the said reference voltage source.
Preferably, said start unit comprises the 2nd PMOS pipe and phase inverter, wherein:
The input end of said phase inverter is as the control end of said start unit, and the output terminal of said phase inverter is connected with the grid of the 2nd PMOS pipe, and the source electrode of the 2nd PMOS pipe is connected with supply voltage, and drain electrode is as the output terminal of said start unit.
Preferably, said start unit is the 7th a NMOS pipe, and the drain electrode of the 7th NMOS pipe is as the output terminal of said start unit, and source electrode connects earth terminal, and grid is as the control end of said start unit.
The application also provides a kind of reference voltage source start-up circuit; Be applied to reference voltage source circuit; Comprise: the first image current source circuit, start unit, first resistance, the 3rd PMOS pipe and the 4th PMOS that are made up of NMOS pipe and the 2nd NMOS pipe manage, wherein:
The control end of said start unit is connected with the drain electrode of NMOS pipe and an end of first resistance respectively; The output terminal of said start unit connects said reference voltage source circuit; When said reference voltage source circuit gets into the dead band, drive said reference voltage source circuit and break away from the dead band;
The other end of first resistance is connected with supply voltage;
The source electrode of the one NMOS pipe connects earth terminal, and grid is connected with drain electrode with the grid of the 2nd NMOS pipe respectively;
The source electrode of the 2nd NMOS pipe connects earth terminal; Drain electrode is connected with the drain electrode of the 4th PMOS pipe; The source electrode of the 4th PMOS pipe is connected with the drain electrode of the 3rd PMOS pipe; The source electrode of the 3rd PMOS pipe is connected with supply voltage AVDD, and the 4th gate pmos utmost point, the 3rd gate pmos utmost point link to each other with reference voltage source circuit respectively, to obtain the main body branch current PTAT electric current in the said reference voltage source.
Preferably, said start unit comprises the 2nd PMOS pipe and phase inverter, wherein:
The input end of said phase inverter is as the control end of said start unit, and the output terminal of said phase inverter is connected with the grid of the 2nd PMOS pipe, and the source electrode of the 2nd PMOS pipe is connected with supply voltage, and drain electrode is as the output terminal of said start unit.
Preferably, said start unit is the 7th a NMOS pipe, and the drain electrode of the 7th NMOS pipe is as the output terminal of said start unit, and source electrode connects earth terminal, and grid is as the control end of said start unit.
Technical scheme by above the application embodiment provides is visible, and said reference voltage source start-up circuit adopts the image current source circuit to obtain the electric current on the switching tube in the said reference voltage source circuit, and is used to control the duty of said start unit; Concrete, when the switching tube in the said reference voltage source circuit ends, when promptly said reference voltage source circuit is operated in the dead band; Electric current in the said image current source circuit is 0; At this moment, start unit is opened, and the electric current of start unit makes the switching tube in the reference voltage source circuit break away from the dead band; And after reference voltage source circuit broke away from the dead band, the electric current on its internal switch pipe raise, and the electric current in the image current source circuit raises; Start-up circuit is ended; At this moment, do not have electric current to flow in the main circuit of reference voltage source circuit, do not influence the operate as normal of reference voltage source circuit.The negligible amounts of the switching tube that the reference voltage source start-up circuit that the application embodiment provides uses; Circuit structure is simple, and owing to adopt said image current source circuit, the unloading phase of reference voltage source circuit; The too high problem that can't start of threshold value because of NMOS pipe in the first image current source circuit can not take place; Therefore, this reference voltage source start-up circuit is applicable in the reference voltage source circuit that high-low pressure technology device uses with, and reliability is high.
Description of drawings
In order to be illustrated more clearly in the application embodiment or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiment that put down in writing among the application, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the integrated circuit structural representation of a kind of reference voltage source of present embodiment;
Voltage oscillogram when Fig. 2 is existing reference voltage source entering dead band;
Fig. 3 is the oscillogram of each key point of reference voltage source of providing of the application;
Fig. 4 is the integrated circuit structural representation of the another kind of reference voltage source of application embodiment;
Fig. 5 is the integrated circuit structural representation of the another kind of reference voltage source of application embodiment;
Fig. 6 is the integrated circuit structural representation of the another kind of reference voltage source of application embodiment.
Embodiment
In order to make those skilled in the art person understand the technical scheme among the application better; To combine the accompanying drawing among the application embodiment below; Technical scheme among the application embodiment is carried out clear, intactly description; Obviously, described embodiment only is the application's part embodiment, rather than whole embodiment.Based on the embodiment among the application, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all should belong to the scope of the application's protection.
See also Fig. 1, show the integrated circuit structural representation of a kind of reference voltage source of the application embodiment, 100 is the structural representation of a kind of reference voltage source start-up circuit of the application embodiment among the figure, and 200 is the structural representation of reference voltage source circuit.
Reference voltage source circuit 200 comprises: transistor PM5, PM6, PM7, PM8, PM9, PM10, NM3, NM4, NM5, NM6; Triode Q1, Q2, Q3; Resistance R 1, R2, R3, R4, wherein, PM5, PM6, PM7, PM8, PM9, PM10 are the PMOS pipe; NM3, NM4, NM5, NM6 are the NMOS pipe, and triode Q1, Q2, Q3 are the positive-negative-positive triode.
The source electrode of PM5, PM6, PM9 all connects supply voltage AVDD, and the drain electrode of PM5, PM6, PM9 links to each other with the source electrode of PM7, PM8, PM10 respectively; The grid of PM5, PM6, PM9 links to each other, and links to each other with the drain electrode of PM8;
The drain electrode of PM7 links to each other through the drain electrode of resistance R 3 connection NM5, and the drain electrode of PM8 is through the drain electrode of resistance R 4 connection NM6, and the drain electrode of PM10 is through the emitter of resistance R 2 connection Q3, and the common port of PM10 and resistance R 2 is as the output terminal Vref of reference voltage source circuit; The grid of PM7, PM8, PM10 links to each other, and links to each other with the drain electrode of NM6;
The source electrode of NM5, NM6 connects the drain electrode of NM3, NM4 respectively, and the grid of NM5, NM6 links to each other, and links to each other with the drain electrode of PM7;
The source electrode of NM3 connects the emitter of triode Q1, and the source electrode of NM4 is through the emitter of resistance R 1 connection triode Q2, and the grid of NM3, NM4 links to each other, and connects the drain electrode of NM5.
The base stage of triode Q1, Q2, Q3 all is connected earth terminal with collector.
PM5, PM6, PM7, PM8, PM9, PM10 are the P channel MOS tube, and its substrate all connects supply voltage AVDD, and NM3, NM4, NM5, NM6 are the N-channel MOS pipe, and its substrate all connects earth terminal.
Said reference voltage source start-up circuit 100 comprises: the first image current source circuit of being made up of transistor NM1, NM2 102, the start unit of being made up of transistor PM2 and phase inverter INV1 101, and transistor PM1, PM3, PM4.Wherein, transistor PM1, PM2, PM3, PM4 are specially the P channel MOS tube, and transistor NM1, NM2 are the N-channel MOS pipe.
Concrete, the source electrode of transistor PM1, PM2, PM3 all is connected in supply voltage AVDD, and the source electrode of PM4 connects the drain electrode of PM3, and the drain electrode of PM2 is connected to first end and the NM5 of drain electrode, the R3 of the PM7 in the reference voltage source circuit 200, the grid of NM6; PM5 in the grid of PM3 and the reference voltage source circuit 200, the grid of PM6 link to each other; The grid of PM4 with reference voltage source circuit 200 in PM7, the grid of PM8 link to each other, the grid of PM2 connects the output terminal of phase inverter INV1, the grid connection earth terminal of PM1; The input end of phase inverter INV1 connects the drain electrode of PM1.Transistor NM1, NM2 constitute the mirror current source of cascodes; Concrete; The source electrode of transistor NM1, NM2 all connects earth terminal, and the grid of NM1, NM2 links to each other, and the grid of NM2 links to each other with the drain electrode of NM2; The drain electrode of NM2 links to each other with the drain electrode of PM4, and the drain electrode of NM1 links to each other with the input end of the drain electrode of PM1 and phase inverter.
The substrate of transistor PM1, PM2, PM3, PM4 all connects supply voltage AVDD, and the substrate of transistor NM1, NM2 all connects earth terminal.
In above-mentioned the reference voltage source start-up circuit 100 and reference voltage source circuit 200, PM3, PM4, PM5, PM6, PM7, PM8 form mirror current source, and PM3, PM4 are used for mirror image PM5 place branch current and PM6 place branch current; NM1 and NM2 form mirror current source, and NM1 is used for the electric current on the mirror image NM2, because NM2 and PM3 be connected on the branch road, so the electric current on the NM2 is identical with electric current on the PM3.The drain electrode of PM2 acts on the bandgap voltage reference circuit as the output terminal of start-up circuit, makes it break away from the work dead band.The PM1 parameter is for falling breadth length ratio, and promptly the ratio of the grid width of PM1 and grid length is less than 1.
The concrete course of work of above-mentioned circuit is following:
When supply voltage AVDD powers on; Because of reference voltage source is in the dead band; NM3, NM4, NM5, NM6 grid potential in the reference voltage source circuit 200 are all lower; NM3, NM4, NM5, NM6 are in cut-off region, and the electric current of PM5 branch road and PM6 branch road is 0, and branch current also is 0 through two class mirror-image PM1 place.Because of the gate source voltage of PM1 is-AVDD, so along with the supply voltage AVDD PM1 that raises fast is in conducting state, the voltage V1 of the drain electrode of PM1 also increases; Through phase inverter INV1 anti-phase, the voltage V2 of the output terminal of phase inverter INV1 reduces fast, as V2≤AVDD-|Vth (PM2) | the time; PM2 conducting, electric current raise and conducting NM3, NM4, NM5, the NM6 grid voltage in the reference voltage source circuit 200, and the electric current of PM5, PM6 branch road increases; And the electric current of the PM1 branch road that is come by NM1, NM2, PM3, PM4 two class mirror-images is moved voltage V1 to enough low; Make the inner NMOS pipe of phase inverter INV1 by the conducting of PMOS pipe, make the output end voltage V2=AVDD of phase inverter INV1, PM2 ends; There is not electric current to flow into voltage-reference main body circuit; Can not influence its operate as normal, reference voltage source start-up circuit 100 makes reference voltage source voltage 200 disengaging dead bands, gets into the operate as normal district.
See also Fig. 2 and Fig. 3, shown in Figure 2 is the oscillogram of existing reference voltage source supply voltage voltage and output voltage; Fig. 3 is the voltage oscillogram of each key point of integrated circuit of the reference voltage source of the application embodiment.
Among Fig. 2, VDD is the voltage waveform of supply voltage AVDD, and Vref is the waveform of the output voltage of reference voltage source circuit output terminal Vref, and is as shown in Figure 2, and at supply voltage AVDD voltage hour, because reference voltage source circuit is in the dead band, output voltage is less.
Among Fig. 3, VDD is the voltage waveform of supply voltage AVDD, and V3 is the grid voltage of NM1, NM2, and Vref is the waveform of the output voltage of reference voltage source circuit output terminal Vref.
After reference voltage source circuit got into the operate as normal district, current mirror was to the branch road at NM1 place, NM1 conducting on the reference voltage source circuit; The drain voltage V1 of NM1 reduces rapidly, and the output end voltage V2 of phase inverter INV1 raises, and PM2 ends; There is not electric current to flow into reference voltage source circuit 200; Therefore, after reference voltage source circuit started the entering operate as normal district that finishes, the reference voltage source start-up circuit can not influence the operate as normal of reference voltage source circuit.And, reference voltage source circuit 200 the unloading phase, the last electric current of NM1 is obtained by the NM2N2 mirror image, the situation that can't start because the threshold voltage of NM1 is too high can not occur, therefore, the reference voltage source start-up circuit high-low pressure technology of present embodiment all is suitable for.
In addition; After reference voltage source circuit 200 got into the operate as normal district, the electric current of reference voltage source start-up circuit 100 was that electric current and the PM3 on the branch road of NM1 place belongs to the electric current sum on the branch road, wherein; Can be through choosing the switching tube of suitable breadth length ratio; Make NM1 be operated in degree of depth conducting district, electric current will be very little, thereby make the current drain of reference voltage source start-up circuit 100 very low.
See also Fig. 4, show the structural representation of the integrated circuit of another kind of reference voltage source, different is that the 101 usefulness transistor NM7 of start unit among Fig. 1 are replaced with embodiment shown in Figure 1.
Concrete, said transistor NM7 is the NMOS pipe, and the grid of NM7 connects the common port of NM1 and PM1, and the source electrode of NM7 all is connected earth terminal with substrate, and the drain electrode of NM7 connects the grid of PM7, PM8.The concrete course of work is: when supply voltage AVDD powers on; Because of reference voltage source circuit 200 is in the dead band; Transistor NM3, NM4, NM5, NM6 grid potential all are in cut-off region than low, and the PTAT of PM5 branch road and PM6 branch road (Proportional To Absolute Temperature, bandgap voltage reference main body branch current) electric current is 0; Behind NM1, NM2, PM3, PM4 two class mirror-images, the PM1 branch current also is 0.Because of the gate source voltage of PM1 is-AVDD, so along with the AVDD PM1 that raises fast is in the bigger conducting state of overdrive voltage, the drain voltage V1 of PM1 also increases; When V1 >=Vth (NM7); NM7 conducting, the electric current among the NM7 reduce and conducting band-gap reference source circuit PM5, NM6, PM7, PM8 grid voltage, thereby the electric current of PM5, PM6 branch road is increased; And by NM1, NM2, PM3, PM4 two class mirror-images and the PM1 branch current that comes is moved voltage V1 to enough low; The grid that this voltage acts on NM7 makes it to turn-off, and does not have electric current to flow into voltage reference source circuit 200, can not influence its operate as normal; So reference voltage source start-up circuit 100 can make reference voltage source circuit 200 disengaging dead bands, get into the operate as normal district.
See also Fig. 5; Show the integrated circuit principle schematic of another kind of reference voltage source; Be on basis embodiment illustrated in fig. 1, transistor PM1 to be replaced with resistance R 0, the course of work of the start-up circuit of the reference voltage source that this figure is corresponding is identical with Fig. 1, repeats no more here.
See also Fig. 6; Show the integrated circuit principle schematic of another kind of reference voltage source; Be on basis embodiment illustrated in fig. 4, transistor PM1 equivalent replacement to be become resistance R 0, the course of work of the reference voltage source start-up circuit of this moment is identical with Fig. 4, repeats no more here.
The above only is the application's a embodiment; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the application's principle; Can also make some improvement and retouching, these improvement and retouching also should be regarded as the application's protection domain.
Claims (6)
1. reference voltage source start-up circuit; Be applied to reference voltage source circuit; It is characterized in that, comprising: the first image current source circuit, start unit, PMOS pipe, the 3rd PMOS pipe and the 4th PMOS that are made up of NMOS pipe and the 2nd NMOS pipe manage, wherein:
The control end of said start unit is connected with the drain electrode of NMOS pipe and the drain electrode of PMOS pipe respectively; The output terminal of said start unit connects said reference voltage source circuit; When said reference voltage source circuit gets into the dead band, drive said reference voltage source circuit and break away from the dead band;
The source electrode of the one PMOS pipe is connected with supply voltage, and grid connects earth terminal;
The source electrode of the one NMOS pipe connects earth terminal, and grid is connected with drain electrode with the grid of the 2nd NMOS pipe respectively;
The source electrode of the 2nd NMOS pipe connects earth terminal; Drain electrode is connected with the drain electrode of the 4th PMOS pipe; The source electrode of the 4th PMOS pipe is connected with the drain electrode of the 3rd PMOS pipe; The source electrode of the 3rd PMOS pipe is connected with supply voltage, and the 4th gate pmos utmost point, the 3rd gate pmos utmost point link to each other with reference voltage source circuit respectively, to obtain the main body branch current PTAT electric current in the said reference voltage source.
2. reference voltage source start-up circuit according to claim 1 is characterized in that, said start unit comprises the 2nd PMOS pipe and phase inverter, wherein:
The input end of said phase inverter is as the control end of said start unit, and the output terminal of said phase inverter is connected with the grid of the 2nd PMOS pipe, and the source electrode of the 2nd PMOS pipe is connected with supply voltage, and drain electrode is as the output terminal of said start unit.
3. reference voltage source start-up circuit according to claim 1; It is characterized in that said start unit is the 7th a NMOS pipe, the drain electrode of the 7th NMOS pipe is as the output terminal of said start unit; Source electrode connects earth terminal, and grid is as the control end of said start unit.
4. reference voltage source start-up circuit; Be applied to reference voltage source circuit; It is characterized in that, comprising: the first image current source circuit, start unit, first resistance, the 3rd PMOS pipe and the 4th PMOS that are made up of NMOS pipe and the 2nd NMOS pipe manage, wherein:
The control end of said start unit is connected with the drain electrode of NMOS pipe and an end of first resistance respectively; The output terminal of said start unit connects said reference voltage source circuit; When said reference voltage source circuit gets into the dead band, drive said reference voltage source circuit and break away from the dead band;
The other end of first resistance is connected with supply voltage;
The source electrode of the one NMOS pipe connects earth terminal, and grid is connected with drain electrode with the grid of the 2nd NMOS pipe respectively;
The source electrode of the 2nd NMOS pipe connects earth terminal; Drain electrode is connected with the drain electrode of the 4th PMOS pipe; The source electrode of the 4th PMOS pipe is connected with the drain electrode of the 3rd PMOS pipe; The source electrode of the 3rd PMOS pipe is connected with supply voltage AVDD, and the 4th gate pmos utmost point, the 3rd gate pmos utmost point link to each other with reference voltage source circuit respectively, to obtain the main body branch current PTAT electric current in the said reference voltage source.
5. reference voltage source start-up circuit according to claim 4 is characterized in that, said start unit comprises the 2nd PMOS pipe and phase inverter, wherein:
The input end of said phase inverter is as the control end of said start unit, and the output terminal of said phase inverter is connected with the grid of the 2nd PMOS pipe, and the source electrode of the 2nd PMOS pipe is connected with supply voltage, and drain electrode is as the output terminal of said start unit.
6. reference voltage source start-up circuit according to claim 4; It is characterized in that said start unit is the 7th a NMOS pipe, the drain electrode of the 7th NMOS pipe is as the output terminal of said start unit; Source electrode connects earth terminal, and grid is as the control end of said start unit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220102082 CN202486648U (en) | 2012-03-16 | 2012-03-16 | Reference voltage source starting circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220102082 CN202486648U (en) | 2012-03-16 | 2012-03-16 | Reference voltage source starting circuit |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103412595A (en) * | 2013-06-20 | 2013-11-27 | 中国矿业大学 | Low-power-source-dependency band-gap reference voltage circuit design based on PTAT current |
| CN104914917A (en) * | 2015-05-27 | 2015-09-16 | 西安空间无线电技术研究所 | Resistance value adjustment band gap voltage and current reference source circuit |
| CN104977964A (en) * | 2015-07-08 | 2015-10-14 | 北京兆易创新科技股份有限公司 | Free-operational amplifier low-output voltage high power supply rejection ratio band-gap reference source circuit |
| CN104977963A (en) * | 2015-07-08 | 2015-10-14 | 北京兆易创新科技股份有限公司 | Free-operational amplifier low power-consumption high power supply rejection ratio band-gap reference circuit |
| CN108008756A (en) * | 2017-12-28 | 2018-05-08 | 珠海博雅科技有限公司 | Reference voltage source and regulator circuit |
| CN108469870A (en) * | 2018-05-30 | 2018-08-31 | 丹阳恒芯电子有限公司 | A kind of reference circuit applied in Internet of Things |
| CN109343653A (en) * | 2018-09-19 | 2019-02-15 | 安徽矽磊电子科技有限公司 | A kind of start-up circuit of bandgap voltage reference |
| CN109489844A (en) * | 2017-09-13 | 2019-03-19 | 爱思开海力士有限公司 | Temperature sensing circuit |
| CN111625043A (en) * | 2020-06-29 | 2020-09-04 | 启攀微电子（上海）有限公司 | Adjustable ultra-low power consumption full CMOS reference voltage current generation circuit |
| CN113342114A (en) * | 2021-06-25 | 2021-09-03 | 上海料聚微电子有限公司 | Starting circuit |
| CN114489225A (en) * | 2022-03-18 | 2022-05-13 | 湖南国科微电子股份有限公司 | Band-gap reference circuit, band-gap reference chip and power management chip |
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2012
- 2012-03-16 CN CN 201220102082 patent/CN202486648U/en not_active Expired - Lifetime
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103412595A (en) * | 2013-06-20 | 2013-11-27 | 中国矿业大学 | Low-power-source-dependency band-gap reference voltage circuit design based on PTAT current |
| CN104914917A (en) * | 2015-05-27 | 2015-09-16 | 西安空间无线电技术研究所 | Resistance value adjustment band gap voltage and current reference source circuit |
| CN104977964A (en) * | 2015-07-08 | 2015-10-14 | 北京兆易创新科技股份有限公司 | Free-operational amplifier low-output voltage high power supply rejection ratio band-gap reference source circuit |
| CN104977963A (en) * | 2015-07-08 | 2015-10-14 | 北京兆易创新科技股份有限公司 | Free-operational amplifier low power-consumption high power supply rejection ratio band-gap reference circuit |
| CN104977963B (en) * | 2015-07-08 | 2016-08-17 | 北京兆易创新科技股份有限公司 | A kind of band-gap reference circuit of the high PSRR of low-power consumption without amplifier |
| CN109489844A (en) * | 2017-09-13 | 2019-03-19 | 爱思开海力士有限公司 | Temperature sensing circuit |
| CN108008756A (en) * | 2017-12-28 | 2018-05-08 | 珠海博雅科技有限公司 | Reference voltage source and regulator circuit |
| CN108008756B (en) * | 2017-12-28 | 2023-08-29 | 珠海博雅科技股份有限公司 | Reference voltage source and voltage stabilizing circuit |
| CN108469870A (en) * | 2018-05-30 | 2018-08-31 | 丹阳恒芯电子有限公司 | A kind of reference circuit applied in Internet of Things |
| CN109343653B (en) * | 2018-09-19 | 2020-07-24 | 安徽矽磊电子科技有限公司 | Starting circuit of band-gap reference voltage source |
| CN109343653A (en) * | 2018-09-19 | 2019-02-15 | 安徽矽磊电子科技有限公司 | A kind of start-up circuit of bandgap voltage reference |
| CN111625043A (en) * | 2020-06-29 | 2020-09-04 | 启攀微电子（上海）有限公司 | Adjustable ultra-low power consumption full CMOS reference voltage current generation circuit |
| CN111625043B (en) * | 2020-06-29 | 2022-06-24 | 启攀微电子（上海）有限公司 | Adjustable ultra-low power consumption full CMOS reference voltage current generation circuit |
| CN113342114A (en) * | 2021-06-25 | 2021-09-03 | 上海料聚微电子有限公司 | Starting circuit |
| CN114489225A (en) * | 2022-03-18 | 2022-05-13 | 湖南国科微电子股份有限公司 | Band-gap reference circuit, band-gap reference chip and power management chip |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 4 / F, building 1, No.14 Jiuxianqiao Road, Chaoyang District, Beijing 100020 Patentee after: Beijing Jingwei Hirain Technologies Co.,Inc. Address before: 100101 Beijing city Chaoyang District Anxiang Beili 11 B block 8 layer Patentee before: Beijing Jingwei HiRain Technologies Co.,Ltd. |
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| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20121010 |