CN202394963U - Multi-chip wafer-level semiconductor package structure - Google Patents

Abstract

The utility model discloses a multi-chip wafer level semiconductor package structure, it provides a miniaturized system packaging module, contains: a rewiring circuit layer, wherein a first surface is provided with a plurality of first connecting pads, and a second surface is provided with a plurality of second connecting pads; at least one first chip located on the first surface of the rewiring circuit layer; the first packaging adhesive material is positioned on the first surface of the rewiring circuit layer and coats the first chip; at least one second chip located on the second surface of the rewiring circuit layer; the second packaging adhesive material is positioned on the second surface of the rewiring circuit layer, coats the second chip and is provided with a plurality of openings; and a plurality of first external bumps respectively positioned in the openings and electrically connected to the second pads of the rewiring circuit layer.

Description

Multi-chip wafer-level semiconductor package structure

technical field

The utility model relates to a multi-chip wafer-level semiconductor packaging structure, in particular to a wafer-level semiconductor packaging structure capable of providing a miniaturized system packaging module with multiple chips.

Background technique

Nowadays, in order to meet the needs of various high-density packaging, the semiconductor packaging industry has gradually developed various types of packaging structures. Among them, various system package (system in package, SIP) design concepts are often used to build high-density packaging structures. The above-mentioned system package can be further divided into multi-chip module (multi chip module, MCM), package on package (package on package, POP) and package in package (package in package, PIP). In addition, there are also design concepts to reduce the size of the package structure, such as wafer level package structure (wafer level package, WLP), chip size package structure (chip scale package, CSP) and no external lead package structure (quad-flatno -lead package, QFN) etc.

For example, please refer to FIG. 1, which discloses a package-on-package (POP) structure composed of an existing wafer-level packaging structure (WLP), which includes a first wafer-level packaging structure 100 and a second wafer-level packaging structure 200, wherein the first wafer-level packaging structure 100 includes a first chip 11, a first packaging adhesive 12, and a first redistribution layer (re-distributed layer, RDL ) 13, several first bumps 14 and several through molding vias (TMV) 15, the through molding vias 15 run through the first packaging adhesive 12, and the bottom ends of the vias pass through The first redistribution layer 13 is electrically connected to the first bump 14, and its top is electrically connected to several transfer pads 16 on the upper surface of the first encapsulant 12; at the same time, the second die The round level packaging structure 200 includes a second chip 21 , a second packaging adhesive 22 , a second redistribution layer 23 and several second bumps 24 . During assembly, the second WLP structure 200 is stacked on the first encapsulant 12 of the first WLP structure 100, and the second bumps 24 are electrically connected to the Adapter pad 16. Therefore, the second chip 21 can be connected through the second redistribution layer 23, the second bump 24, the transfer pad 16, the adhesive via hole 15, the first redistribution layer 13 and the first bump 14. An input/output electrical connection path is formed to transmit the power and signal of the second WLP structure 200 or to be used for grounding.

However, the problem with the package-on-package structure formed by the above existing wafer-level packaging structure is that although two or more wafer-level packaging structures 100, 200 can be stacked together to form a miniaturized system package ( SIP) structure, but because the first wafer-level packaging structure 100 must be provided with a sufficient number of through-glue via holes 15 in the first packaging adhesive 12 for corresponding connection to the second wafer-level packaging structure 200 of the second bump 24, so the first encapsulant 12 must have a sufficient volume, which results in that the overall volume of the first wafer-level packaging structure 100 cannot be further reduced, which is not conducive to the miniaturization of the system packaging structure. change. Conversely, if the first encapsulant 12 is to be controlled to have a limited volume, then the first encapsulant 12 will not be able to provide too many via holes 15 through glue, which will also make the second die The quantity of the second bumps 24 of the circular level packaging structure 200 is limited, which further affects the chip computing capability that the system packaging structure can provide. Furthermore, limited by the current technical level of manufacturing the through-glue via hole 15 , the manufacturing yield is still relatively low. As a result, it is currently difficult for the packaging industry to further design a miniaturized system package design with a higher circuit layout density than the POP architecture of the existing wafer-level packaging structure within the limited packaging space.

Therefore, it is necessary to provide a multi-chip wafer-level semiconductor packaging structure to solve the problems existing in the prior art.

Utility model content

In view of this, the utility model provides a multi-chip wafer-level semiconductor packaging structure to solve the technical problem existing in the existing wafer-level packaging technology that high circuit layout density and stacking volume miniaturization cannot be taken into account.

The main purpose of the present invention is to provide a multi-chip wafer-level semiconductor packaging structure. During the manufacturing period, the redistribution circuit layer is made first, and then at least one chip is respectively combined on both sides of the redistribution circuit layer, and the packaging is completed. After gluing, set external bumps on the side of the rewiring circuit layer as input/output terminals, and plate a heat dissipation metal layer on the outer surface of the packaging material, so that the first modularization can be completed without using the POP architecture Package, and directly construct a wafer level package (wafer level package, WLP) level miniaturized system package module, so it is beneficial to increase the circuit layout density of the single package structure itself, improve the heat dissipation efficiency of the package structure, and further make the wafer The volume of the level packaging structure can be smoothly realized to be thinner and smaller.

The secondary purpose of this utility model is to provide a multi-chip wafer-level semiconductor packaging structure, which uses the above-mentioned miniaturized system packaging module to further perform a second modular packaging, that is, on both sides of another rewiring circuit layer Combining the miniaturized system package module and at least one chip respectively, it is indeed beneficial to increase the circuit layout density of the single package structure itself, improve the heat dissipation efficiency of the package structure, and improve the efficiency of the package-in-package (PIP) structure of the wafer-level package structure. The feasibility of stacking, and then the volume of the wafer-level packaging structure and its PIP architecture can be successfully realized in light, thin and short.

In order to achieve the aforementioned purpose of the utility model, the utility model provides a multi-chip wafer-level semiconductor packaging structure, wherein the multi-chip wafer-level semiconductor packaging structure is a miniaturized system package module, and the miniaturized system package module Include:

A redistribution circuit layer has a first surface and a second surface, the first surface is provided with a plurality of first pads, and the second surface is provided with a plurality of second pads;

At least one first chip is located on the first surface of the redistribution circuit layer and is provided with a plurality of first pads, and the first pads are electrically connected to the first pads of the redistribution circuit layer;

A first encapsulant, located on the first surface of the redistribution circuit layer, and covering the first chip;

At least one second chip is located on the second surface of the redistribution circuit layer and is provided with a plurality of second pads, and the second pads are electrically connected to the second pads of the redistribution circuit layer;

a second encapsulant, located on the second surface of the redistribution circuit layer, covering the second chip, and having a plurality of openings; and

A plurality of first external bumps are respectively located in the openings and electrically connected to the second pads of the redistribution circuit layer.

In an embodiment of the present utility model, the opening of the second encapsulant further includes several second external protrusions, and the second external protrusions are respectively stacked and combined on the first external protrusions, And the second circumscribed bump is partially protruded out of the opening of the second encapsulation material.

In an embodiment of the present invention, an outer surface of the first encapsulant has a heat dissipation metal layer.

In an embodiment of the present invention, an outer surface of the second packaging adhesive has a heat dissipation metal layer.

In an embodiment of the present invention, the first encapsulation material is photo-resist, epoxy, prepreg or laser activated material.

In an embodiment of the present invention, the second encapsulating adhesive material is photoresist, epoxy resin, bonding sheet or laser activated material.

In an embodiment of the present invention, the first pad of the first chip is electrically connected to the first pad of the redistribution circuit layer through a plurality of first bumps.

In an embodiment of the present invention, the first bumps may be selected from tin bumps, gold bumps, copper pillar bumps or nickel pillar bumps.

In an embodiment of the present invention, the second pad of the second chip is electrically connected to the second pad of the redistribution circuit layer through a plurality of second bumps.

In an embodiment of the present invention, the second bumps may be selected from tin bumps, gold bumps, copper pillar bumps or nickel pillar bumps.

Furthermore, the utility model provides another multi-chip wafer-level semiconductor packaging structure, wherein the multi-chip wafer-level semiconductor packaging structure includes:

A miniaturized system packaging module as described above, comprising: a first redistribution circuit layer, at least one first chip, a first packaging adhesive, a heat dissipation metal layer, at least a second chip, and a second packaging adhesive and several first external bumps;

A second rewiring circuit layer has a first carrying surface and a second carrying surface, the first carrying surface is provided with several first transfer pads, and the second carrying surface is provided with several second transfer pads pad, wherein the miniaturized system package module is located on the first bearing surface, and the first external bump is electrically connected to the first transfer pad;

A third packaging adhesive, located on the first bearing surface of the second redistribution circuit layer, and covering the miniaturized system packaging module;

At least one third chip is located on the second carrying surface of the second redistribution circuit layer, and is provided with several third pads, and the third pads are electrically connected to the second redistribution circuit layer. on the second adapter pad;

A fourth encapsulant, located on the second carrying surface of the second redistribution circuit layer, covering the third chip, and having several transfer openings; and

A plurality of third external bumps are respectively located in the transfer openings and are electrically connected to the second transfer pads of the second redistribution circuit layer.

In an embodiment of the present utility model, the opening of the fourth encapsulant further includes several fourth outer bumps, and the fourth outer bumps are respectively stacked and bonded to the third outer bumps, And the fourth circumscribed bump is partially protruded out of the opening of the fourth encapsulant.

In an embodiment of the present invention, an outer surface of the third packaging adhesive has a heat dissipation metal layer.

In an embodiment of the present invention, an outer surface of the fourth packaging material has a heat dissipation metal layer.

Description of drawings

FIG. 1 is a schematic diagram of a package-on-package (POP) structure composed of a conventional wafer-level packaging (WLP) structure.

2A, 2B, 2C and 2D are schematic flowcharts of each step of the manufacturing method of the multi-chip wafer-level semiconductor packaging structure according to the first embodiment of the present invention.

FIG. 2E is a schematic diagram of a multi-chip wafer-level semiconductor packaging structure according to a second embodiment of the present invention.

Detailed ways

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the preferred embodiments of the present invention are specifically cited below, together with the accompanying drawings, for a detailed description as follows. Furthermore, the directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc. , are for orientation only with reference to the attached drawings. Therefore, the used directional terms are used to illustrate and understand the present invention, but not to limit the present invention.

Please refer to FIGS. 2A to 2D , which disclose the schematic flow chart of each step of the manufacturing method of the multi-chip wafer-level semiconductor packaging structure of the first embodiment of the present invention. The present utility model will be described in detail below using FIGS. 2A to 2D The detailed processing process of each step in the first embodiment, and the detailed structure, assembly relationship and operation principle of each component.

Please refer to FIG. 2A , the manufacturing method of the multi-chip wafer-level semiconductor packaging structure of the first embodiment of the present utility model is firstly: prepare a temporary carrier 30, and place an adhesive layer on the temporary carrier 30 A redistribution circuit layer 31 is manufactured on the 301 according to a build-up process; then, at least one first chip 32 is stacked and bonded on the redistribution circuit layer 31 . In this step, the temporary carrier plate 30 may be a metal plate (such as a stainless steel plate or a copper plate, etc.), a glass plate or a plastic plate with sufficient hardness. The adhesive layer 301 is preferably a copper seed layer (Cu seed layer) or UV tape (UV tape). The redistribution circuit layer 31 refers to a composite stacked layer formed by alternately stacking a plurality of insulating layers and circuit layers, and the number of insulating layers and circuit layers included therein is based on the requirements for the position and spacing of the redistributed pads of the product. to design. After the redistribution circuit layer 31 is manufactured according to the build-up process, the redistribution circuit layer 31 has a first surface (ie, the upper surface) and a second surface (ie, the lower surface). A plurality of first pads 311 are exposed on the surface, and a plurality of second pads 312 are exposed on the second surface.

Furthermore, the at least one first chip 32 is located on the first surface of the redistribution circuit layer 31, and has a downward-facing active surface and an upward-facing back surface, and the active surface is provided with several A welding pad 321 , the first welding pad 321 is bonded to the first pad 311 of the redistribution circuit layer 31 through a plurality of first bumps 322 . The first bumps 322 may be selected from tin bumps, gold bumps, copper stud bumps (Cupillar bumps) or nickel stud bumps, but not limited thereto.

Please refer to FIG. 2B , the manufacturing method of the multi-chip wafer-level semiconductor packaging structure according to the first embodiment of the present invention is as follows: making a first packaging adhesive 33 located on the first surface of the redistribution circuit layer 31 covering and protecting the first chip 32 ; then, plating a heat dissipation metal layer 34 on an outer surface of the first encapsulant 33 . In this step, the first packaging adhesive 33 can be selected from photo-resist, epoxy, prepreg or laser activated material, such as the The first packaging adhesive material 33 can be selected from a pressing sheet, which refers to a semi-cured prepreg material made of epoxy resin and glass fiber, which can be stacked on the redistribution circuit layer after pressing. 31 on the first surface and then properly deformed to fill the gap between the redistribution circuit layer 31 and the first chip 32, and then reheat to cure the bonding sheet to form the first packaging adhesive 33 . If necessary, before making the first encapsulation material 33 , the gap between the redistribution circuit layer 31 and the first chip 32 may also be pre-filled with underfill.

Furthermore, the heat dissipating metal layer 34 is preferably a coating of copper, silver, gold, nickel, palladium or a composite coating thereof, which can be achieved by sputtering, evaporation, electroplating or electroless plating ( Electroless plating) and other processes are plated on an outer surface (such as the upper surface) of the first packaging adhesive 33. If necessary, the upward facing back of the first chip 32 can be directly exposed when the first packaging adhesive 33 is made, or after the first packaging adhesive 33 is made, it can be ground until the first chip 32 is exposed. The back side of the chip 32 faces upward, so that the back side of the first chip 32 can be directly connected to the heat dissipation metal layer 34 , so as to further improve the efficiency of heat dissipation of the first chip 32 .

Please refer to FIG. 2C , the manufacturing method of the multi-chip wafer-level semiconductor packaging structure of the first embodiment of the present invention is as follows: remove the temporary carrier 30 and the adhesive layer 301, and redistribute the circuit layer 31. At least one second chip 35 and several first external bumps 36 are bonded to the second pad 312 at the bottom of the combination of the first chip 32 , the first encapsulant 33 and the heat dissipation metal layer 34 . In this step, when the adhesive layer 301 is a copper seed layer, the temporary carrier 30 is first peeled off by external force, then the adhesive layer 301 is removed by etching, and then the rewiring circuit layer 31 is exposed. The second pads 312 on the second surface are subjected to surface treatment, such as plating on a nickel/gold layer or a nickel/palladium/gold layer, so as to be used for combining the at least one second chip 35 and a plurality of first external bumps 36. The second chip 35 is located on the second surface (i.e. the lower surface) of the redistribution circuit layer 31, and is provided with several second pads 351, and the second pads 351 pass through several second bumps 352. Electrically connected to the second pad 312 of the redistribution circuit layer 31 . The second bumps 352 may be selected from tin bumps, gold bumps, copper stud bumps or nickel stud bumps, but are not limited thereto.

Furthermore, the first external bumps 36 can be arranged at equal or unequal intervals and bonded to other second pads 312 around the second chip 35 . The height of the first external bump 36 may be greater than, equal to or smaller than the total height of the second chip 35 , the second bonding pad 351 and the second bump 352 combined on the second surface of the redistribution circuit layer 31 . high. The first circumscribed bump 36 may also be selected from tin bumps, gold bumps, copper stud bumps or nickel stud bumps, but is not limited thereto.

In addition, in another embodiment of this step, the temporary carrier 30 can be selected from a glass plate and the adhesive layer 301 can be selected from ultraviolet light tape. At this time, the adhesive layer 301 can be irradiated with ultraviolet light to make the It loses its viscosity, so that the combination of the redistribution circuit layer 31 , the first chip 32 , the first encapsulant 33 and the heat dissipation metal layer 34 is smoothly separated from the temporary carrier 30 and the adhesive layer 301 , and then the surface treatment of the second pad 312 and the bonding of the second chip 35 and the first external bump 36 can also be performed.

Please refer to FIG. 2D , the manufacturing method of the multi-chip wafer-level semiconductor packaging structure in the first embodiment of the present invention is as follows: making a second packaging adhesive 37 located on the second surface of the redistribution circuit layer 31 covering and protecting at least the second chip 35 ; then, stacking and bonding a second external bump 38 on each of the first external bumps 36 . In this step, the second packaging adhesive 37 can be selected from photoresist, epoxy resin, bonding sheet or laser activated material, for example, the second packaging adhesive 37 can be selected from bonding sheet, the The pressing sheet refers to a semi-cured prepreg material composited by epoxy resin and glass fiber, which can be properly deformed after being pressed and stacked on the second surface of the redistribution circuit layer 31, and fills the The space between the redistribution circuit layer 31 and the second chip 35 is described, and then heated to solidify the bonding sheet to form the second packaging adhesive 37 . If necessary, before making the second packaging glue 37 , the gap between the redistribution circuit layer 31 and the second chip 35 may also be pre-filled with underfill glue.

Furthermore, after making the second packaging adhesive 37, the second packaging adhesive 37 covers the second chip 35 and the first external bump 36, and at this time, the second packaging adhesive can be further The material 37 is perforated to form a plurality of openings 371 to respectively expose the first circumscribed bumps 36 . Or, if the second encapsulant 37 is selected from an epoxy resin substrate doped with a solid filler, and is produced by transfer molding (transfer molding) technology, then the mold can also be designed to The shape of the mold cavity is such that the opening 371 is directly formed when the second encapsulant 37 is molded. The purpose of the opening 371 is to further stack and combine a second outer protrusion 38 on each of the first outer protrusions 36, and the total height of the first and second outer protrusions 38 is greater than that of the first outer protrusion 38. Due to the thickness of the second encapsulant 37 , the second external bump 38 can partially protrude out of the opening of the second encapsulant 37 . The second circumscribed bumps 38 may be selected from tin bumps, gold bumps, copper stud bumps or nickel stud bumps, but are not limited thereto.

In addition, a heat dissipation metal layer (not shown) can also be selectively plated on an outer surface (the lower surface) of the second encapsulant 37 . The heat dissipation metal layer is also preferably a copper, silver, gold, nickel, palladium coating or a composite coating, which can also be plated on the second packaging adhesive 37 by sputtering, evaporation, electroplating or electroless plating. on the outer surface. If necessary, the back side of the second chip 35 facing downward may also be directly exposed when the second packaging adhesive 37 is made, or after the second packaging adhesive 37 is made, it may be ground until the first chip is exposed. The back side of the second chip 35 faces downward, so that the back side of the second chip 35 can be directly connected with the heat dissipation metal layer, so as to further improve the efficiency of heat dissipation of the second chip 35 .

At the end of this step, the above-mentioned redistribution circuit layer 31, first packaging adhesive material 33, heat dissipation metal layer 34 and second packaging adhesive material 37 can be cut to separate into several miniaturized SIP modules (miniaturized SIP module) 300 , wherein each miniaturized system package module 300 roughly includes: a redistribution circuit layer 31, at least one first chip 32, a first packaging adhesive 33, a heat dissipation metal layer 34, at least one second chip 35, the first Two packaging adhesive materials 37 , several first external bumps 36 and several second external bumps 38 . The redistribution circuit layer 31 has a first surface (ie, the upper surface) and a second surface (ie, the lower surface), the first surface is provided with several first pads 311, and the second surface is provided with several a second pad 312. The at least one first chip 32 is located on the first surface of the redistribution circuit layer 31, and is provided with a plurality of first pads 321, and the first pads 321 are electrically connected to the redistribution circuit layer 31 on the first pad 311. The first packaging adhesive 33 is located on the first surface of the redistribution circuit layer 31 and covers the first chip 32 . The heat dissipation metal layer 34 is coated on an outer surface (such as an upper surface) of the first encapsulant 33 .

Moreover, the at least one second chip 35 is located on the second surface of the rewiring circuit layer 31, and is provided with a plurality of second pads 351, and the second pads 351 are electrically connected to the rewiring circuit layer. on the second pad 312 of the circuit layer 31 . The second packaging adhesive 37 is located on the second surface of the redistribution circuit layer 31 , covers the second chip 35 , and has a plurality of openings 371 . The plurality of first external bumps 36 are respectively located in the openings 371 and electrically connected to other second pads 312 of the redistribution circuit layer 31 . The second outer bumps 38 are respectively stacked and combined on the first outer bumps 36 , and the second outer bumps 38 partially protrude out of the opening 371 of the second packaging adhesive 37 . , as input/output terminals, to transmit power, signal or as grounding purposes.

Please refer to FIG. 2E , the structure of the multi-chip wafer-level semiconductor package of the second embodiment of the present invention is similar to that of the first embodiment of the present invention, and roughly uses the same component names and figure numbers, but the difference of the second embodiment It is characterized in that: the multi-chip wafer-level semiconductor packaging structure 400 of the second embodiment uses the miniaturized system packaging module 300 of the first embodiment above to further perform a second modular packaging process, and the second The steps of modular packaging are similar to those shown in FIGS. 2A to 2D, except that the first chip 32 in FIGS. 2A to 2D is replaced by the miniaturized system in package module 300, and the first chip 32 in FIGS. 2A to 2D is replaced by at least one third chip 44. To the second chip 35 in 2D, the processing principles of the remaining steps are basically similar. After completing the second modular package process, the multi-chip wafer-level semiconductor package structure 400 of the second embodiment includes: a miniaturized system package module 300, a second redistribution circuit layer 41, a third Packaging adhesive 42 , a heat dissipation metal layer 43 , at least one third chip 44 , a fourth packaging adhesive 46 , several third external bumps 45 and several fourth external bumps 47 .

In the second embodiment, the miniaturized system in package module 300 includes the component structures of the first embodiment as described above, that is, a (first) redistribution circuit layer 31, at least one first chip 32, a first A packaging adhesive 33 , a heat dissipation metal layer 34 , at least one second chip 35 , a second packaging adhesive 37 , a plurality of first external bumps 36 and a plurality of second external bumps 38 . The second redistribution circuit layer 41 has a first carrying surface (i.e. the upper surface) and a second carrying surface (i.e. the lower surface), the first carrying surface is provided with several first transfer pads 411, and the The second carrying surface is provided with several second transfer pads 412, wherein the miniaturized system package module 300 is located on the first carrying surface, and the first and second external bumps 36, 38 are electrically connected on the first transfer pad 411 . The third packaging adhesive 42 is located on the first bearing surface of the second redistribution circuit layer 41 and covers the miniaturized system package module 300 . The heat dissipation metal layer 43 is coated on an outer surface (such as an upper surface) of the third encapsulant 42 .

Moreover, the at least one third chip 44 is located on the second carrying surface of the second redistribution circuit layer 41 and is provided with several third pads 441, and the third pads 441 pass through several third pads. The bump 442 is electrically connected to the second transfer pad 412 of the second redistribution circuit layer 41 . The fourth encapsulant 46 is located on the second carrying surface of the second redistribution circuit layer 41 , covers the third chip 44 , and has a plurality of transfer openings 461 . The plurality of third external bumps 45 are respectively located in the transition openings 461 and are electrically connected to other second transition pads 412 of the second redistribution circuit layer 41 . The fourth bumps 38 are respectively stacked and combined on the third outer bumps 45 , and the second outer bumps 38 partially protrude out of the opening 461 of the fourth packaging adhesive 46 , It can be used as an input/output terminal to transmit power, signal or ground.

If necessary, before making the third packaging glue 42 , the gap between the second redistribution circuit layer 41 and the miniaturized system packaging module 300 may also be pre-filled with underfill glue. Before making the fourth packaging glue 46 , the gap between the second redistribution circuit layer 41 and the third chip 44 can also be pre-filled with underfill glue. In addition, a heat dissipation metal layer (not shown) can also be selectively plated on an outer surface (the lower surface) of the fourth encapsulation material 46 . When necessary, the heat dissipation metal layer 34 (or the third chip) of the miniaturized system package module 300 facing upward may also be directly exposed when the third (or fourth) packaging adhesive material 42 (or 46) is made. 44 facing downwards), or after making the third (or fourth) packaging adhesive 42 (or 46) and then grinding until the heat dissipation metal layer 34 facing upwards of the miniaturized system packaging module 300 is exposed (or The back side of the third chip 44 facing downwards), so that the heat dissipation metal layer 34 of the miniaturized system package module 300 (or the back side of the third chip 44 ) can be connected to the outside of the third packaging adhesive 42 The heat dissipation metal layer 43 or the heat dissipation metal layer (not shown) outside the fourth packaging material 46 are directly connected together, so as to further improve the heat dissipation efficiency of the miniaturized system package module 300 or the third chip 44 .

As mentioned above, compared with the technical problems of the existing wafer-level packaging technology that cannot take into account the high circuit layout density and the miniaturization of the stacking volume, the utility model shown in Fig. 2A to 2D is to make the heavy Wiring circuit layer 31, and then respectively bonding the at least one first chip 32 and the at least one second chip 35 on both sides of the rewiring circuit layer 31, and after sealing the glue on the rewiring circuit layer 31 One side (lower side) is provided with the first and second external bumps 36, 38 as input/output terminals, and the outer surfaces of the first and second packaging adhesive materials 33, 37 can be plated with heat dissipation Metal layer 34, so that the first modular packaging can be directly completed without using the POP architecture, and a miniaturized system-in-package module 300 of wafer level package (wafer level package, WLP) level can be directly constructed, so it is beneficial The circuit layout density of the single package structure itself is increased, the heat dissipation efficiency of the package structure is improved, and the volume of the wafer-level package structure can be smoothly realized to be light, thin and compact.

Furthermore, the utility model shown in FIG. 2E utilizes the aforementioned miniaturized system packaging module 300 to further carry out the second modular packaging process, that is, to combine the miniaturized system packaging module 300 on both sides of another redistribution circuit layer 41. and at least one third chip 44, so it is indeed beneficial to increase the circuit layout density of the single package structure itself, improve the heat dissipation efficiency of the package structure, and improve the stacking feasibility of the package-in-package (PIP) structure of the wafer-level package structure, And further, the volume of the wafer-level packaging structure and its PIP structure can be smoothly realized to be light, thin, and small.

The utility model has been described by the above-mentioned relevant embodiments, but the above-mentioned embodiments are only examples for implementing the utility model. It must be pointed out that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the claims are included in the scope of the present invention.

Claims (10)

1. A multi-chip wafer-level semiconductor packaging structure, characterized in that: the multi-chip wafer-level semiconductor packaging structure is a miniaturized system package module, and the miniaturized system package module includes: A redistribution circuit layer has a first surface and a second surface, the first surface is provided with a plurality of first pads, and the second surface is provided with a plurality of second pads; At least one first chip is located on the first surface of the redistribution circuit layer and is provided with a plurality of first pads, and the first pads are electrically connected to the first pads of the redistribution circuit layer; A first encapsulant, located on the first surface of the redistribution circuit layer, and covering the first chip; At least one second chip is located on the second surface of the redistribution circuit layer and is provided with a plurality of second pads, and the second pads are electrically connected to the second pads of the redistribution circuit layer; a second encapsulant, located on the second surface of the redistribution circuit layer, covering the second chip, and having a plurality of openings; and A plurality of first external bumps are respectively located in the openings and electrically connected to the second pads of the redistribution circuit layer. 2. The multi-chip wafer-level semiconductor packaging structure according to claim 1, characterized in that: the opening of the second packaging adhesive further includes several second external bumps, and the second external bumps are respectively The stack is bonded on the first circumscribing bump. 3 . The multi-chip wafer level semiconductor package structure as claimed in claim 2 , wherein the second external bumps partially protrude out of the opening of the second encapsulant. 4 . 4. The multi-chip wafer-level semiconductor package structure as claimed in claim 1, wherein an outer surface of the first encapsulant has a heat dissipation metal layer. 5 . The multi-chip wafer level semiconductor packaging structure as claimed in claim 1 , wherein an outer surface of the second packaging adhesive has a heat dissipation metal layer. 6 . 6. The multi-chip wafer-level semiconductor packaging structure according to claim 1, wherein the first pad of the first chip is electrically connected to the redistribution circuit layer through a plurality of first bumps. on the first pad; and the second pad of the second chip is electrically connected to the second pad of the redistribution circuit layer through a plurality of second bumps. 7. A multi-chip wafer-level semiconductor packaging structure, characterized in that: the multi-chip wafer-level semiconductor packaging structure comprises: A miniaturized system package module as claimed in claim 1, comprising a first redistribution circuit layer, at least one first chip, a first packaging adhesive, a heat dissipation metal layer, at least one second chip, and a second package Adhesive material and several first external bumps; A second rewiring circuit layer has a first carrying surface and a second carrying surface, the first carrying surface is provided with several first transfer pads, and the second carrying surface is provided with several second transfer pads pad, wherein the miniaturized system package module is located on the first bearing surface, and the first external bump is electrically connected to the first transfer pad; A third packaging adhesive, located on the first bearing surface of the second redistribution circuit layer, and covering the miniaturized system packaging module; At least one third chip is located on the second carrying surface of the second redistribution circuit layer, and is provided with several third pads, and the third pads are electrically connected to the second redistribution circuit layer. on the second adapter pad; A fourth encapsulant, located on the second carrying surface of the second redistribution circuit layer, covering the third chip, and having several transfer openings; and A plurality of third external bumps are respectively located in the transfer openings and are electrically connected to the second transfer pads of the second redistribution circuit layer. 8. The multi-chip wafer-level semiconductor packaging structure according to claim 7, characterized in that: the opening of the fourth packaging adhesive further includes several fourth external bumps, and the fourth external bumps are respectively The stack is combined on the third circumscribed bump, and the fourth circumscribed bump partially protrudes out of the opening of the fourth encapsulation material. 9 . The multi-chip wafer level semiconductor packaging structure as claimed in claim 7 , wherein an outer surface of the third packaging material has a heat dissipation metal layer. 10 . The multi-chip wafer level semiconductor packaging structure as claimed in claim 7 , wherein an outer surface of the fourth packaging material has a heat dissipation metal layer. 11 .

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