CN202218240U - A digital branching device with variable speed and variable number of channels - Google Patents

Abstract

The utility model discloses a variable speed rate variable-way digital branching device, which comprises an input data buffer output device, an input control signal analysis module, an input data buffer output control module, a filter coefficient memory, a filter coefficient of the output control module, a fast fourier transformation (FFT) transformation module, a coefficient adjustment module and a multiply accumulation module. Universal design of low-speed variable speed rate variable-way multiple carrier digital branching devices is achieved.

Description

A kind of variable Rate becomes way digital demultiplexing device

Technical field

The utility model discloses a kind of variable Rate and become way digital demultiplexing device.

Background technology

Spaceborne software implementation processing transponder technology can solve Satellite Software in the fixing problem of rail function through the process software injection mode, can expand the flexibility that satellite communication system is used so greatly.In addition, adopt standardization, modular hardware and software design cell, the disposal ability on the star that reaches total that cooperatively interacts of the basic function module through some as basic function module.

FDMA is a kind of very important satellite communication multi-access mode, adopts FDMA can reduce the complexity of satellite communication system, reduces weight, volume and the power consumption at terminal, is fit to very much mobile communication and portable communications.Therefore, the exploitation of FDMA waveform software kit is the important component part of whole spaceborne software implementation processing transponder technology waveform software kit.FDMA software waveform bag in the spaceborne software implementation processing transponder technology mainly comprises digital demultiplexing, multicarrier all-digital demodulation and the multicarrier decoding of multicarrier.Multi-carrier digital is whole FDMA software waveform bag important component part along separate routes, realizes with FPGA usually.

The many real needs according to project of existing digital demultiplexing method, design is corresponding to the implementation structure of the digital demultiplexing of project technical indicator.Such design implementation structure does not often have versatility, needs design again if technical indicator changes to some extent, has reduced design efficiency.Document 1 " A Novel ASIC for all-digital onboard Multicarrier Demodulation of Symbol-Synchronous FDMA " (F.Quaranta for example; Alenia Spazio) provided and a kind ofly carried out the digital demultiplexing implementation structure to 3 kinds of specific speed, adopted the implementation (realization flow figure such as Fig. 2) of ASIC; Document 2 " realizes 2 with TMS320C6x ^mThe whole Demodulation Algorithm Study of road signal total digitalization " (Zhou Desuo, field red heart, Liu Qiang, Yi Kechu; integrated services network National Key Laboratory of Xian Electronics Science and Technology University, Xi'an, electronic letters, vol; 2000 the 1st phases) realize mainly, carried out 32 the tunnel, the digital demultiplexing of every road 4.8Kbps.

Under identical total bandwidth, to different service and terminal type, the speed of the number of carrier wave and each carrier wave is with difference among the FDMA, and therefore corresponding multi-carrier digital exponent number along separate routes and speed are with different.

The utility model content

The technology of the utility model is dealt with problems and is: overcome the deficiency of prior art, provide a kind of variable Rate to become way digital demultiplexing device.Adopt the utility model to realize universal design to the multi-carrier digital derived channel equipment of low speed variable Rate, change way.

The technical solution of the utility model is:

A kind of variable Rate becomes way digital demultiplexing device, comprising: input data buffering follower, input control signal parsing module, input metadata cache output control module, filter coefficient storage, filter coefficient output control module, multiply accumulating module, FFT conversion module and coefficient adjustment module.

The input control signal parsing module receives shunt exponent number control word N, extraction FACTOR CONTROL word M and the prototype filter coefficient length L imported; Output is exponent number control word N, extraction FACTOR CONTROL word M, every group of prototype filter length Q along separate routes, wherein, and L=Q*N;

Input data buffering output control module; According to shunt exponent number control word N, extraction FACTOR CONTROL word M and every group of prototype filter length Q; Produce the address signal of reading of control input data buffering follower; Wherein, M, N, Q control each interval of dateout generation along separate routes, the number of heterogeneous number and the data point of participating in every group of multiphase filtering respectively; And the multiply accumulating output controlled flag signal flag_mac and the FFT transfer interval marking signal flag_ifft that produce outputed to the multiply accumulating module respectively; Wherein, work as Input Data Buffer, every generation Q heterogeneous input data are just exported a flag_mac marking signal; N flag_mac marking signal of every generation just produces a flag_ifft signal;

Input data buffering follower carries out buffer memory with the input sampling data that receives, and outputs to the multiply accumulating module according to the heterogeneous input data of reading after address signal divides into groups sampled data that receive;

The filter coefficient output control module, shunt exponent number control word N and every group of prototype filter length Q according to the input control signal parsing module produces produce the address signal of reading that outputs to filter coefficient storage;

Filter coefficient storage outputs to the multiply accumulating module according to the address signal of reading that is produced by the filter coefficient output control module that receives with the filter coefficient grouping of storing;

The multiply accumulating module utilizes the filter coefficient of filter coefficient storage output and every group of prototype filter length Q, the multiply accumulating output controlled flag signal flag_mac of input the heterogeneous input data of input data buffering output module output to be carried out multiply accumulating handle; And multiply accumulating is handled back IFFT conversion input signal that obtains and the FFT transfer interval marking signal flag_ifft that receives output to variable-order FFT conversion module;

Variable-order FFT conversion module; With the FFT transfer interval marking signal flag_ifft that receives as IFFT conversion opening flag signal; And under shunt number signal controlling; After IFFT conversion input signal from multiply accumulating module input carried out shunt and handle, with the IFFT conversion output signal that obtains with output to the coefficient adjustment module;

The coefficient adjustment module; When receiving IFFT conversion output effective index signal, utilize to receive along separate routes exponent number control word N and extract the IFFT conversion output signal of FACTOR CONTROL word M and carry out after the phase shift with the digital demultiplexing signal output that forms to the input of variable-order FFT conversion module.

The utility model compared with prior art has following advantage:

(1) the utility model is on the basis of general digital demultiplexing principle; Operating characteristic in conjunction with the FPGA device; The characteristics of utilizing FPGA device speed and resource to exchange have been designed a kind of general digital shunt FPGA implementation structure that is suitable for low speed variable bit rate, variable way.For this implementation structure, the user does not need to design again the FPGA program, only needs to change the input Control Parameter and (comprises filter order N, extracts the high workload clock f of factor M, prototype filter length L and system _WorkWith input clock f _MainConcern control word W), just can realize different rates, the digital demultiplexing of different way signals, improves design efficiency at the development time that can practice thrift the user greatly.

(2) the utility model is when carrying out multiphase filtering; The characteristics of utilizing FPGA device speed and resource to exchange; Change the implementation of Traditional use low-speed parallel transversal filter into high speed serialization multiply accumulating implementation; Whole multiphase filtering tightly needs 2 multipliers, the expense of having saved hardware resource greatly.

Description of drawings

Fig. 1 is the utility model structure chart;

Fig. 2 be external certain satellite system based on special speed, the shunt realization flow figure of specific way;

Fig. 3 is an input control signal parsing module sketch map;

Fig. 4 is the Input Data Buffer module diagram;

Fig. 5 is input data buffering output control module sketch map;

Fig. 6 is the filter coefficient storage module diagram;

Fig. 7 is a filter coefficient storage output control module sketch map;

Fig. 8 is the multiply accumulating module diagram;

Fig. 9 is the coefficient adjustment module diagram.

Embodiment

Just combine accompanying drawing that the utility model is done further introduction below.

Following in the digital demultiplexing corresponding to the mathematic(al) representation of every road output signal:

$y_n\left(r\right)=e^{-\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="HSA00000569055100012.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;}\frac{\mathrm{nrM}}{N}}\underset{p=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{\mathrm{<figure-callout\; id="2"\; label="e\; j"\; filenames="HSA00000569055100012.png"\; state="\{\{state\}\}">e</figure-callout>}}^{j}v(r,p)---\left(1\right)$

$v(r,p)\&equiv;\underset{q=0}{\overset{Q-1}{\mathrm{\&Sigma;}}}h(\mathrm{qN}+p)x(\mathrm{rM}-\mathrm{qN}-p)---\left(2\right)$

Wherein: x (n) represents input signal, and N is a way along separate routes, and M is for extracting the factor, and h (n) represents the prototype filter coefficient, and L is the length of filter coefficient, and L=Q*N, Q are the coefficient number of each Filtering Processing group.

According to above-mentioned principle; The utility model mainly is based on the FPGA processor to carry out variable Rate and becomes way digital demultiplexing device design; To the characteristics of input signal low rate multichannel number and the occupation mode of FPGA processor resource and clock rate exchange; Under the prerequisite that minimizes the hardware resource expense, accomplish variable Rate through the cooperation of a plurality of modules and become the operation of way digital demultiplexing.As shown in Figure 1; Be the utility model sketch map, comprise: input data buffering follower, input control signal parsing module, input metadata cache output control module, filter coefficient storage, filter coefficient output control module, multiply accumulating module, FFT conversion module and coefficient adjustment module.

According to the way N of input signal, the sampling rate f of input signal _s, along separate routes export signals sampling speed f _DownAnd prototype filter coefficient length L is confirmed the high workload clock frequency f of system _WorkThe mutual restriction relation of this Several Parameters is following:

f _work＝f _down*N*Q；f _s＝f _down*M；L＝Q*N；

Generally, the sampling rate f of input signal _s, customer requirements shunt output signal sampling speed f _DownFix, the designer can under the prerequisite that satisfies the filtering performance index request, make L minimize through the suitable prototype filter coefficient length L of design, thereby reduces the high workload clock of whole system.

The input control signal parsing module is resolved the Control Parameter of input, produces the inner used control signal of the utility model device according to Control Parameter, and is as shown in Figure 3.

The input signal of input control signal parsing module has: input service clock f _Main(clk_in), the high workload clock f of system _WorkWith input clock f _MainConcern control word W, external reset signal extracts factor M, number N along separate routes, prototype filter length L.The output signal has: clock enable signal clk_en1; Extract factor M, shunt number N, every group of prototype filter length Q; Number weighs load enable signal nfft_we along separate routes; Shunt number signal nfft, FFT conversion and IFFT conversion control signal fwd_inv, FFT conversion and IFFT conversion control enable signal fwd_inv_we.

f _WorkWith f _MainRelation be: f _Main=f _Work* W, generally, the user can be through configuration input service clock f _MainEqual the high workload clock f of system _Work, this moment W=1, the clock enable signal often is 1.

Shunt Input Data Buffer as shown in Figure 4 is controlled exporting buffering through input data buffering output control module shown in Figure 5.Input data buffering output control module is through the control to Input Data Buffer dual port RAM OPADD; Produce the heterogeneous input data that to carry out multiphase filtering; Control each interval of dateout generation along separate routes by M; Control heterogeneous number by N, participate in the number of the point of every group of multiphase filtering by Q control.

Because the utility model is when being realized by whole FPGA, with a unified high clock processing, the rate-matched for the inputoutput data that makes the Input Data Buffer dual port RAM has adopted and has read the variation that the address enable control signal is controlled OPADD.

The input signal of input data buffering output control module has: input service clock f _Main(clk_in), clock enable signal clk_en1_in, external reset signal rest_in extracts factor M, shunt number N, every group of prototype filter length Q.

The output signal of input data buffering output control module has: read address addr_read, read address enable en_read, multiply accumulating output controlled flag signal flag_mac, IFFT transfer interval marking signal flag_ifft.

Wherein, read the relation of the signal of address signal and input and confirm by the x (rM-qN-p) in the above-mentioned formula (2) part, q=1 wherein ..., Q.

Shunt filter filtering coefficient memory shown in Figure 6 through filter coefficient storage output control module shown in Figure 7 to controlling.Filter coefficient storage is through the control to filter coefficient storage ROM OPADD; Produce the multiphase filter coefficient data that need carry out multiphase filtering; Control heterogeneous number by N, control the number of the filter of participating in every group of multiphase filtering by Q.This module adopts the address enable signal to come the variation of control filters coefficient memory ROM OPADD equally.

The input signal of filter coefficient storage output control module has: input service clock f _Main, clock enable signal clk_en1_in, external reset signal rest_in, shunt number N, every group of prototype filter length Q.

The input signal of filter coefficient storage output control module has the filter coefficient storage of outputing to: read address addr_read_filter_rom, read address enable en_read_filter_rom.

Confirm by the part of the h (qN+p) in the above-mentioned formula (2) for the relation of reading address addr_read_filter_rom and input signal of filter coefficient storage, q=1 wherein ..., Q.

Multiply accumulating module shown in Figure 8 is carried out the multiply accumulating operation to the heterogeneous sampled data and the multiphase filter coefficient data of input.In the multiply accumulating module, every Q computing carried out a zero clearing to accumulator, thereby accomplishes the calculating of a multiphase filtering point.In order to guarantee the relative fixed of dateout amplitude under the different ways, the sampled data points and the filter coefficient of input are carried out the position expansion and the multiply accumulating result is carried out an intercept operation simultaneously through parameter Q.The utility model whole multiply accumulating module when concrete the realization only needs a multiplier, has saved multiplier resources.

The input signal of multiply accumulating module has: input service clock f _MainThe clock enable signal, external reset signal, Input Data Buffer dateout data_out_i; Filter coefficient storage dateout data_out_filter_rom; Every group of prototype filter length Q, multiply accumulating output controlled flag signal flag_mac, IFFT transfer interval marking signal flag_ifft.

The output signal of multiply accumulating module has: IFFT conversion input signal ifft_data_in_i, IFFT conversion clock enable signal ifft_clk_en, IFFT conversion opening flag signal ifft_start_flag.

IFFT conversion opening flag signal is identical with IFFT transfer interval marking signal, just in the multiply accumulating module, has carried out the time delay of corresponding clock cycle.

Formula (2) has provided the operation relation between multiply accumulating module and input data and the filter coefficient in detail.

When realizing, whole digital demultiplexing device needs 2 multiply accumulating modules, the real part and the imaginary part of corresponding respectively input data.

Accomplish the digital demultiplexing of different way signals through variable-order FFT conversion module.Variable-order FFT conversion module is that whole variable Rate becomes the nucleus module in the processing of way digital demultiplexing, the ripe IP kernel FFT transformation kernel V3.2 of this module invokes XILINX company.Through being accomplished, the configuration of FFT exponent number becomes way FFT map function.

Variable-order FFT conversion module input signal has: work clock, work clock enable signal, external reset signal; The real part of IFFT conversion input signal ifft_data_in_i, the imaginary part of IFFT conversion input signal ifft_data_in_i, IFFT conversion opening flag signal ifft_clk_en; Number weighs load enable signal nfft_we along separate routes; Shunt number signal N, FFT conversion and IFFT conversion control signal fwd_inv, FFT conversion and IFFT conversion control enable signal fwd_inv_we.

Variable-order FFT conversion module output signal has: the real part ifft_data_out_i of IFFT conversion output signal; The imaginary part ifft_data_out_q of IFFT conversion output signal; IFFT conversion serial output road index signal xk_index_in, IFFT conversion output effective index signal rdf_in.

Accomplish the phase place of each road signal through the coefficient adjustment module and rotate, as shown in Figure 9.IFFT conversion output signal demand take advantage of a twiddle factor

wherein r represent the point of time domain, be the concrete road of frequency domain number and n represents.M/N=2 generally, 1,1/2,1/4.The coefficient adjustment module is carried out the phase place rotation to the FFT value of variable-order FFT conversion module output, obtains final digital demultiplexing signal, and this module needs a complex multiplier.Before carrying out the phase place rotation, to carrying out the cut position operation, guarantee the consistency of shunting sign amplitude under different shunt way situation of final output from the data of variable-order FFT conversion module output according to N.For the ease of the further processing of user to follow-up signal, utilize Q to produce the clock enable signal of dateout, its frequency is the 1/Q of work clock.

Coefficient adjustment module input signal has: work clock, work clock enable signal, external reset signal; IFFT conversion output signal real part ifft_data_out_i, IFFT conversion output signal imaginary part ifft_data_out_q, IFFT conversion serial output road index signal xk_index_in; IFFT conversion output effective index signal rdf_in; Extract factor M, shunt number N, every group of prototype filter length Q.

The coefficient adjustment module output signal has: work clock enable signal clk_en2_out; The postrotational shunt dateout of phase place solid part signal data_out_i; The postrotational shunt dateout of phase place imaginary signals data_out_q, serial output road index signal xk_index_out.

The unspecified part of the utility model belongs to general knowledge as well known to those skilled in the art.

Claims (3)

1. a variable Rate becomes way digital demultiplexing device, it is characterized in that comprising: input data buffering follower, input control signal parsing module, input metadata cache output control module, filter coefficient storage, filter coefficient output control module, multiply accumulating module, FFT conversion module and coefficient adjustment module.

The input control signal parsing module receives shunt exponent number control word N, extraction FACTOR CONTROL word M and the prototype filter coefficient length L imported; Output is exponent number control word N, extraction FACTOR CONTROL word M, every group of prototype filter length Q along separate routes, wherein, and L=Q*N;

Input data buffering output control module; According to shunt exponent number control word N, extraction FACTOR CONTROL word M and every group of prototype filter length Q; Produce the address signal of reading of control input data buffering follower; Wherein, M, N, Q control each interval of dateout generation along separate routes, the number of heterogeneous number and the data point of participating in every group of multiphase filtering respectively; And the multiply accumulating output controlled flag signal flag_mac and the FFT transfer interval marking signal flag_ifft that produce outputed to the multiply accumulating module respectively; Wherein, work as Input Data Buffer, every generation Q heterogeneous input data are just exported a flag_mac marking signal; N flag_mac marking signal of every generation just produces a flag_ifft signal;

Input data buffering follower carries out buffer memory with the input sampling data that receives, and outputs to the multiply accumulating module according to the heterogeneous input data of reading after address signal divides into groups sampled data that receive;

The filter coefficient output control module, shunt exponent number control word N and every group of prototype filter length Q according to the input control signal parsing module produces produce the address signal of reading that outputs to filter coefficient storage;

Filter coefficient storage outputs to the multiply accumulating module according to the address signal of reading that is produced by the filter coefficient output control module that receives with the filter coefficient grouping of storing;

The multiply accumulating module utilizes the filter coefficient of filter coefficient storage output and every group of prototype filter length Q, the multiply accumulating output controlled flag signal flag_mac of input the heterogeneous input data of input data buffering output module output to be carried out multiply accumulating handle; And multiply accumulating is handled back IFFT conversion input signal that obtains and the FFT transfer interval marking signal flag_ifft that receives output to variable-order FFT conversion module;

Variable-order FFT conversion module; With the FFT transfer interval marking signal flag_ifft that receives as IFFT conversion opening flag signal; And under shunt number signal controlling; After IFFT conversion input signal from multiply accumulating module input carried out shunt and handle, with the IFFT conversion output signal that obtains with output to the coefficient adjustment module;

The coefficient adjustment module; When receiving IFFT conversion output effective index signal, utilize to receive along separate routes exponent number control word N and extract the IFFT conversion output signal of FACTOR CONTROL word M and carry out after the phase shift with the digital demultiplexing signal output that forms to the input of variable-order FFT conversion module.

2. a kind of variable Rate according to claim 1 becomes way digital demultiplexing device, it is characterized in that: the address signal of reading of the filter coefficient storage of reading address signal and the generation of said filter coefficient output control module of the data buffering follower that said input data buffering output control module produces is confirmed according to following formula

$v(r,p)\&equiv;\underset{q=0}{\overset{Q-1}{\mathrm{\&Sigma;}}}h(\mathrm{qN}+p)x(\mathrm{rM}-\mathrm{qN}-p);$

Wherein: x (rM-qN-p) representative and data buffering follower read the corresponding input data of address signal; H (qN+p) representative and filter coefficient storage read address signal corresponding be stored in the prototype filter coefficient in the filter coefficient storage; L is the length of filter coefficient; L=Q*N, (r p) is the output signal of multiply accumulating module to v.

3. a kind of variable Rate according to claim 1 becomes way digital demultiplexing device, it is characterized in that: said coefficient adjustment module is exported signal according to following formula to the serial i FFT conversion of input and is carried out serial phase shift processing

$y_n\left(r\right)=e^{-j2\mathrm{\&pi;}\frac{\mathrm{nrM}}{N}}\underset{p=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}^{j2\mathrm{\&pi;}\frac{\mathrm{np}}{N}}v(r,p).$

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