CN202049955U - Polycrystalline package structure for increasing the amount of current using a constant voltage power supply - Google Patents
Polycrystalline package structure for increasing the amount of current using a constant voltage power supply Download PDFInfo
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- CN202049955U CN202049955U CN 201020642948 CN201020642948U CN202049955U CN 202049955 U CN202049955 U CN 202049955U CN 201020642948 CN201020642948 CN 201020642948 CN 201020642948 U CN201020642948 U CN 201020642948U CN 202049955 U CN202049955 U CN 202049955U
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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Abstract
Description
技术领域 technical field
本实用新型涉及一种多晶封装结构,尤指一种使用定电压电源供应器且用于增加电流量的多晶封装结构。The utility model relates to a polycrystalline packaging structure, in particular to a polycrystalline packaging structure which uses a constant voltage power supply and is used to increase the amount of current.
背景技术 Background technique
电灯的创造可以说是彻底地改变了全人类的生活方式,倘若我们的生活没有电灯,夜晚或天气状况不佳的时候,一切的工作都将要停止;倘若受限于照明,极有可能使房屋建筑方式或人类生活方式都彻底改变,全人类都将因此而无法进步,继续停留在较落后的年代。因此,今日市面上所使用的照明设备,例如:日光灯、钨丝灯、甚至到现在较广为大众所接受的节能灯,皆已普遍应用于日常生活当中。然而,此类电灯大多具有光衰减快、高耗电量、容易产生高热、寿命短、易碎或不易回收等缺点。因此,使用发光二极管的封装结构因应而生。The creation of electric lights can be said to have completely changed the way of life of all human beings. If we live without electric lights, all work will stop at night or when the weather is bad; The way of construction or the way of life of human beings will be completely changed, and all human beings will not be able to progress because of this, and will continue to stay in a relatively backward age. Therefore, the lighting equipment used in the market today, such as fluorescent lamps, tungsten filament lamps, and even the energy-saving lamps that are widely accepted by the public, have been widely used in daily life. However, most of these lamps have disadvantages such as fast light decay, high power consumption, high heat generation, short life, fragile or difficult to recycle. Therefore, a packaging structure using light emitting diodes emerges accordingly.
实用新型内容 Utility model content
本实用新型所要解决的技术问题,在于提供一种多晶封装结构,其可使用定电压电源供应器作为供电的源头且可依据不同数量的发光二极管芯片以增加电流量供应。为了解决上述技术问题,本实用新型提供一种使用定电压电源供应器且用于增加电流量的多晶封装结构,其包括:一基板单元,其具有一基板本体、一位于该基板本体上表面的第一置晶区域、及一位于该基板本体上表面的第二置晶区域;一发光单元,其具有多个电性设置于该第一置晶区域上的发光二极管芯片;一限流单元,其具有多个电性设置于该第二置晶区域上的限流芯片,多个限流芯片电性连接于该发光单元;一边框单元,其具有一环绕地成形于该基板本体上表面的第一环绕式边框胶体及一环绕地成形于该基板本体上表面的第二环绕式边框胶体,该第一环绕式边框胶体围绕上述多个发光二极管芯片,以形成一对应于该第一置晶区域的第一胶体限位空间,且该第二环绕式边框胶体围绕多个限流芯片,以形成一对应于该第二置晶区域的第二胶体限位空间;一封装单元,其具有一填充于该第一胶体限位空间内以覆盖上述多个发光二极管芯片的第一封装胶体及一填充于该第二胶体限位空间内以覆盖多个限流芯片的第二封装胶体。The technical problem to be solved by the utility model is to provide a polycrystalline packaging structure, which can use a constant voltage power supply as a source of power supply and can increase the current supply according to different numbers of LED chips. In order to solve the above technical problems, the utility model provides a polycrystalline packaging structure using a constant voltage power supply and for increasing the amount of current, which includes: a substrate unit, which has a substrate body, a The first crystal mounting area, and a second crystal mounting area located on the upper surface of the substrate body; a light-emitting unit, which has a plurality of light-emitting diode chips electrically arranged on the first crystal mounting area; a current limiting unit It has a plurality of current limiting chips electrically arranged on the second crystal mounting area, and the plurality of current limiting chips are electrically connected to the light emitting unit; a frame unit has a surrounding shape formed on the upper surface of the substrate body The first surrounding frame colloid and a second surrounding frame colloid formed around the upper surface of the substrate body, the first surrounding frame colloid surrounds the above-mentioned plurality of light emitting diode chips to form a corresponding to the first placement The first colloid limiting space in the crystal area, and the second surrounding frame colloid surrounds a plurality of current limiting chips to form a second colloid limiting space corresponding to the second crystal placement area; a packaging unit, which has A first packaging colloid filled in the first colloid limiting space to cover the plurality of LED chips and a second packaging colloid filled in the second colloid limiting space to cover the plurality of current limiting chips.
本实用新型还提供一种使用定电压电源供应器且用于增加电流量的多晶封装结构,其包括:一基板单元,其具有一基板本体、两个位于该基板本体上表面的第一置晶区域、及一位于该基板本体上表面的第二置晶区域;一发光单元,其具有至少一用于产生第一种色温的第一发光模块及至少一用于产生第二种色温的第二发光模块,上述至少一第一发光模块具有多个电性设置于其中一第一置晶区域上的第一发光二极管芯片,且上述至少一第二发光模块具有多个电性设置于另外一第一置晶区域上的第二发光二极管芯片;一限流单元,其具有多个电性设置于该第二置晶区域上的限流芯片,多个限流芯片电性连接于该发光单元;一边框单元,其具有两个环绕地成形于该基板本体上表面的第一环绕式边框胶体及一环绕地成形于该基板本体上表面的第二环绕式边框胶体,上述两个第一环绕式边框胶体分别围绕上述至少一第一发光模块及上述至少一第二发光模块,以分别形成两个相对应上述两个第一置晶区域的第一胶体限位空间,且该第二环绕式边框胶体围绕多个限流芯片,以形成一对应于该第二置晶区域的第二胶体限位空间;以及一封装单元,其具有两个分别填充于上述两个第一胶体限位空间内以分别覆盖上述至少一第一发光模块及上述至少一第二发光模块的第一封装胶体及一填充于该第二胶体限位空间内以覆盖多个限流芯片的第二封装胶体。The utility model also provides a polycrystalline packaging structure using a constant voltage power supply and used to increase the amount of current, which includes: a substrate unit, which has a substrate body, two first placed crystal area, and a second crystal mounting area located on the upper surface of the substrate body; a light emitting unit, which has at least one first light emitting module for generating a first color temperature and at least one first light emitting module for generating a second color temperature Two light-emitting modules, the above-mentioned at least one first light-emitting module has a plurality of first light-emitting diode chips electrically arranged on one of the first chip mounting regions, and the above-mentioned at least one second light-emitting module has a plurality of electrically arranged on the other The second light-emitting diode chip on the first crystal mounting area; a current limiting unit, which has a plurality of current limiting chips electrically arranged on the second crystal mounting area, and the multiple current limiting chips are electrically connected to the light emitting unit ; a frame unit, which has two first encircling frame colloids formed on the upper surface of the substrate body and a second encircling frame colloid formed on the upper surface of the substrate body, the two first encircling Type frame colloid surrounds the above-mentioned at least one first light-emitting module and the above-mentioned at least one second light-emitting module respectively to form two first colloid-limiting spaces corresponding to the above-mentioned two first crystal placement regions, and the second surrounding type The frame colloid surrounds a plurality of current limiting chips to form a second colloid limiting space corresponding to the second crystal placement area; The first encapsulant covering the at least one first light-emitting module and the at least one second light-emitting module respectively, and the second encapsulant filled in the second encapsulant space to cover a plurality of current limiting chips.
本实用新型再提供一种使用定电压电源供应器且用于增加电流量的多晶封装结构,其包括:一基板单元,其具有一基板本体、两个位于该基板本体上表面的第一置晶区域、及一位于该基板本体上表面的第二置晶区域;一发光单元,其具有至少一用于产生第一种色温的第一发光模块及至少一用于产生第二种色温的第二发光模块,其中上述至少一第一发光模块具有多个电性设置于其中一第一置晶区域上的第一发光二极管芯片,且上述至少一第二发光模块具有多个电性设置于另外一第一置晶区域上的第二发光二极管芯片;一限流单元,其具有多个电性设置于该第二置晶区域上的限流芯片,多个限流芯片电性连接于该发光单元;一边框单元,其具有两个环绕地成形于该基板本体上表面的第一环绕式边框胶体及一环绕地成形于该基板本体上表面的第二环绕式边框胶体,且其中一个第一环绕式边框胶体围绕另外一个第一环绕式边框胶体,上述两个第一环绕式边框胶体分别围绕上述至少一第一发光模块及上述至少一第二发光模块,以分别形成两个相对应上述两个第一置晶区域的第一胶体限位空间,上述至少一第二发光模块位于上述两个第一环绕式边框胶体之间,且该第二环绕式边框胶体围绕多个限流芯片,以形成一对应于该第二置晶区域的第二胶体限位空间;以及一封装单元,其具有两个分别填充于上述两个第一胶体限位空间内以分别覆盖上述至少一第一发光模块及上述至少一第二发光模块的第一封装胶体及一填充于该第二胶体限位空间内以覆盖多个限流芯片的第二封装胶体。The utility model further provides a polycrystalline packaging structure using a constant voltage power supply and used to increase the amount of current, which includes: a substrate unit, which has a substrate body, two first placed on the upper surface of the substrate body crystal area, and a second crystal mounting area located on the upper surface of the substrate body; a light emitting unit, which has at least one first light emitting module for generating a first color temperature and at least one first light emitting module for generating a second color temperature Two light-emitting modules, wherein the above-mentioned at least one first light-emitting module has a plurality of first light-emitting diode chips electrically disposed on one of the first chip mounting regions, and the above-mentioned at least one second light-emitting module has a plurality of electrically disposed on another A second light-emitting diode chip on the first crystal mounting area; a current limiting unit, which has a plurality of current limiting chips electrically arranged on the second crystal mounting area, and the multiple current limiting chips are electrically connected to the light emitting diode chip. Unit; a frame unit, which has two first surrounding frame colloids formed around the upper surface of the substrate body and a second surrounding frame colloid formed around the upper surface of the substrate body, and one of the first The surrounding frame colloid surrounds another first surrounding frame colloid, and the above two first surrounding frame colloids respectively surround the above-mentioned at least one first light-emitting module and the above-mentioned at least one second light-emitting module, so as to form two corresponding to the above-mentioned two The first colloid limiting space of the first crystal placement area, the above-mentioned at least one second light-emitting module is located between the above-mentioned two first surrounding frame colloids, and the second surrounding frame colloids surround a plurality of current limiting chips, so as to forming a second colloidal limiting space corresponding to the second chip placement area; and a packaging unit, which has two fillings in the two first colloidal limiting spaces to cover the at least one first light-emitting module respectively. And the first encapsulation compound of the at least one second light-emitting module and a second encapsulation compound filled in the second colloid limiting space to cover a plurality of current limiting chips.
因此,本实用新型的有益效果在于:除了可通过“将多个发光二极管芯片与多个限流芯片电性连接于同一基板单元上”的设计,以使得本实用新型的多晶封装结构可使用定电压电源供应器作为供电的源头,而且也可达到依据使用不同数量的发光二极管芯片以提供不同电流量供应的目的。Therefore, the beneficial effect of the utility model is that: in addition to the design of "electrically connecting multiple light-emitting diode chips and multiple current limiting chips on the same substrate unit", the polycrystalline packaging structure of the utility model can be used The constant voltage power supply is used as the source of power supply, and it can also achieve the purpose of supplying different currents according to the number of LED chips used.
为使能更进一步了解本实用新型的特征及技术内容,请参阅以下有关本实用新型的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本实用新型加以限制。In order to further understand the features and technical contents of the present utility model, please refer to the following detailed description and accompanying drawings of the present utility model. However, the accompanying drawings are only for reference and illustration, and are not intended to limit the present utility model.
附图说明 Description of drawings
图1A为本实用新型实施例一的立体示意图;Fig. 1A is a three-dimensional schematic diagram of
图1B为本实用新型实施例一的侧视剖面示意图;Fig. 1B is a schematic side view sectional view of
图1C为本实用新实施例一的俯视示意图;Fig. 1C is a schematic top view of
图1D为本实用新型实施例一的功能方块图;Fig. 1D is a functional block diagram of
图1E为本实用新型实施例一选用一颗350mA的限流芯片的电路示意图;FIG. 1E is a schematic circuit diagram of a 350mA current-limiting chip selected in
图1F为本实用新型实施例一选用两颗350mA的限流芯片的电路示意图;Fig. 1F is a schematic circuit diagram of selecting two 350mA current limiting chips in
图1G为本实用新型实施例一选用三颗350mA的限流芯片的电路示意图;Fig. 1G is a schematic circuit diagram of selecting three 350mA current-limiting chips in
图2A为本实用新型实施例二的俯视示意图;Fig. 2A is a schematic top view of
图2B为本实用新型实施例二的侧视剖面示意图;Fig. 2B is a schematic side view sectional view of the second embodiment of the utility model;
图3为本实用新型实施例三的俯视示意图;Fig. 3 is a schematic top view of a third embodiment of the utility model;
图4A为本实用新型实施例四的俯视示意图;Fig. 4A is a schematic top view of
图4B为本实用新型实施例四的侧视剖面示意图;Fig. 4B is a side view cross-sectional schematic diagram of
图5A为本实用新型实施例五的俯视示意图;Fig. 5A is a schematic top view of Embodiment 5 of the present utility model;
图5B为本实用新型实施例五的侧视剖面示意图;Fig. 5B is a side view cross-sectional schematic diagram of the fifth embodiment of the utility model;
图6A为本实用新型实施例六的俯视示意图;Fig. 6A is a schematic top view of Embodiment 6 of the present utility model;
图6B为本实用新型实施例六的侧视剖面示意图;Fig. 6B is a schematic side view sectional view of Embodiment 6 of the present utility model;
图7A为本实用新型实施例七的俯视示意图;Fig. 7A is a schematic top view of Embodiment 7 of the present utility model;
图7B为本实用新型实施例七的侧视剖面示意图;Fig. 7B is a schematic side view sectional view of Embodiment 7 of the present utility model;
图8为本实用新型实施例八的俯视示意图;Fig. 8 is a schematic top view of the eighth embodiment of the utility model;
图9A为本实用新型实施例九的俯视示意图;Fig. 9A is a schematic top view of Embodiment 9 of the present utility model;
图9B为本实用新型实施例九的侧视剖面示意图;Fig. 9B is a schematic side view sectional view of Embodiment 9 of the present utility model;
图10为本实用新型实施例十的侧视剖面示意图;Fig. 10 is a schematic side view sectional view of
图11为本实用新型使用多个备用焊垫的局部俯视示意图。FIG. 11 is a schematic partial top view of the utility model using a plurality of spare welding pads.
【主要元件附图标记说明】[Description of reference signs of main components]
定电压电源供应器SConstant voltage power supply S
多晶封装结构 ZPolycrystalline package structure Z
基板单元 1 基板本体 10
电路基板 100
散热层 101
导电焊垫 102
正极焊垫 PPositive pad P
负极焊垫 NNegative pad N
绝缘层 103
第一置晶区域 11
第二置晶区域 12Two
隔热狭缝 13
发光单元 2 发光二极管芯片 20Light-emitting
正极 201
负极 202Negative electrode 202
第一发光模块 2a 第一发光二极管芯片 20aThe first light-emitting
第二发光模块 2b 第一发光二极管芯片 20bThe second light-emitting
限流单元 C 限流芯片 C1Current limiting unit C Current limiting chip C1
边框单元 3 第一环绕式边框胶体 30
第一环绕式边框胶体 30aThe first surround border colloid 30A
第一环绕式边框胶体 30b
圆弧切线 TT
角度 θ
高度 HHeight Height H
宽度 DWidth D
第一胶体限位空间 300
第二环绕式边框胶体 31Second -wiring
第二胶体限位空间 310
封装单元 4 第一封装胶体 40
第一封装胶体 40aThe
第一封装胶体 40bThe
第二封装胶体 41The
导线单元 W 导线 W1Wire unit W Wire wire W1
第一组发光结构 N1The first group of light-emitting structures N1
第二组发光结构 N2The second group of light-emitting structures N2
蓝色光束 L1Blue Beam L1
白色光束 L2White Beam L2
具体实施方式 Detailed ways
实施例一Embodiment one
如图1A至图1D所示,本实用新型实施例一提供一种使用定电压电源供应器S且用于增加电流量的多晶封装结构Z,其包括:一基板单元1、一发光单元2、一限流单元C、一边框单元3及一封装单元4。As shown in FIG. 1A to FIG. 1D ,
基板单元1具有一基板本体10、一位于基板本体10上表面的第一置晶区域11、及一位于基板本体10上表面的第二置晶区域12。举例来说,基板本体10可具有一电路基板100、一设置于电路基板100底部的散热层101、多个设置于电路基板100上表面的导电焊垫102、及一设置于电路基板100上表面并用于露出多个导电焊垫102的绝缘层103。The
发光单元2具有多个电性设置于第一置晶区域11上的发光二极管芯片20(未封装的LED裸晶)。举例来说,每一个发光二极管芯片20可为一蓝色发光二极管芯片,且每一个发光二极管芯片20可通过打线(wire-bonding)的方式,以电性地设置于基板单元1的第一置晶区域11上。The
限流单元C具有多个电性设置于第二置晶区域12上的限流芯片C1(本实用新型的附图中只揭示一颗限流芯片作代表)。多个限流芯片C1电性连接于发光单元2,以提供一特定的电流给发光单元2使用。举例来说,多个限流芯片C1可通过打线的方式,以电性设置于基板单元1的第二置晶区域12上且电性连接于定电压源供应器S与发光单元2之间(如图1D所示)。另外,因为多个限流芯片C1可作为定电压源供应器S与发光单元2之间的桥梁,以使得发光单元2能够从定电压源供应器S得到稳定的电流供应。The current limiting unit C has a plurality of current limiting chips C1 electrically disposed on the second chip mounting area 12 (only one current limiting chip is disclosed in the drawings of the present utility model as a representative). A plurality of current limiting chips C1 are electrically connected to the
边框单元3具有一可通过涂布的方式而环绕地成形于基板本体10上表面的第一环绕式边框胶体30及一可通过涂布的方式而环绕地成形于基板本体10上表面的第二环绕式边框胶体31。第一环绕式边框胶体30围绕多个发光二极管芯片20,以形成一对应于第一置晶区域11的第一胶体限位空间300,且第二环绕式边框胶体31围绕多个限流芯片C1,以形成一对应于第二置晶区域12的第二胶体限位空间310。此外,第一环绕式边框胶体30与第二环绕式边框胶体31彼此分离一特定距离。The
举例来说,第一环绕式边框胶体30(或第二环绕式边框胶体31)的制作方法,至少包括下列几个步骤:(1)首先,环绕地涂布液态胶材(图未示)于基板本体10上表面。液态胶材可被随意地围绕成一预定的形状(例如圆形、方形、长方形等等),并且环绕地涂布液态胶材于基板本体10上表面的起始点与终止点为大约相同的位置,因此起始点与终止点会有一胶体细微凸出的外观;(2)然后,再固化液态胶材以形成第一环绕式边框胶体30。因此,第一环绕式边框胶体30的上表面可呈现一圆弧形,第一环绕式边框胶体30相对于基板本体10上表面的圆弧切线T的角度θ可介于40至50度之间,第一环绕式边框胶体30的顶面相对于基板本体10上表面的高度H可介于0.3至0.7mm之间,第一环绕式边框胶体30底部的宽度D可介于1.5至3mm之间,第一环绕式边框胶体30的触变指数可介于4至6之间,且第一环绕式边框胶体30可为一混有无机添加剂的白色热硬化边框胶体。For example, the manufacturing method of the first surrounding frame glue 30 (or the second surrounding frame glue 31) includes at least the following steps: (1) First, apply liquid glue material (not shown) around the The upper surface of the
封装单元4具有一填充于第一胶体限位空间300内以覆盖多个发光二极管芯片20的第一封装胶体40及一填充于第二胶体限位空间310内以覆盖多个限流芯片C1的第二封装胶体41。第一封装胶体40与第二封装胶体41彼此分离一特定距离,且第一环绕式边框胶体30与第二封装胶体41彼此分离一特定距离。举例来说,由于第一封装胶体40可为一透光胶体(例如荧光胶体或透明胶体),因此多个发光二极管芯片20(例如多个蓝色发光二极管芯片)所投射出来的蓝色光束L1可穿过第一封装胶体40(例如荧光胶体),以产生类似日光灯源的白色光束L2。另外,第二封装胶体41可为一不透光胶体,其用于覆盖多个限流芯片C1,以避免多个限流芯片C1受到白色光束L2的照射而产生损坏的情况。The
基板单元1更进一步包括有:至少一贯穿基板本体10的隔热狭缝13,且隔热狭缝13可位于发光单元2与限流单元C之间或位于第一环绕式边框胶体30与第二环绕式边框胶体31之间。因此,通过隔热狭缝13的使用,可大大减少限流单元C与发光单元2之间的热传路径,进而使得本实用新型可有效减缓由限流单元C的一或多个限流芯片C1所产生的热量传导至发光单元2的速度。The
如图1E至图1G所示,举例来说,当多个串联在一起的发光二极管芯片20需要350mA的电流供应时,设计者可选用一颗350mA的限流芯片C1来达到;当两组多个串联在一起的发光二极管芯片20需要700mA的电流供应时,设计者可选用两颗350mA的限流芯片C1,以并联的方式来分别达到每一组多个串联在一起的发光二极管芯片20所需要的电流量;当三组多个串联在一起的发光二极管芯片20需要1050mA的电流供应时,设计者可选用三颗350mA的限流芯片C1,以并联的方式来分别达到每一组多个串联在一起的发光二极管芯片20所需要的电流量。依此类推,即可达到依据使用不同组数及不同数量的发光二极管芯片20,以达到提供不同电流量供应的目的。换句话说,本实用新型不仅可以直接使用定电压电源供应器S来得到所需电力,而且本实用新型也可通过上述多个并联在一起的限流芯片C1来增加发光单元2所需的电流量。As shown in Figure 1E to Figure 1G, for example, when a plurality of light-emitting
实施例二Embodiment two
由图2A与图1A(或图2B与图1B)的比较,与实施例一的不同在于:实施例二的基板单元1可省略隔热狭缝13的制作。举例来说,当限流单元C不会产生过多的热量时,则可考虑使用本实用新型实施例二的方案。From the comparison of FIG. 2A and FIG. 1A (or FIG. 2B and FIG. 1B ), the difference from the first embodiment is that the
实施例三Embodiment three
由图3与图1C的比较,与实施例一的不同在于:在实施例三中,限流单元C位于第一环绕式边框胶体30与第二环绕式边框胶体31之间,第二环绕式边框胶体31围绕第一环绕式边框胶体30,第二封装胶体41围绕第一封装胶体40,且第一环绕式边框胶体30与第二封装胶体41彼此相连。换句话说,第一环绕式边框胶体30只围绕多个发光二极管芯片20,而第二环绕式边框胶体31同时围绕多个发光二极管芯片20、第一环绕式边框胶体30及多个限流芯片C1,因此第一环绕式边框胶体30与第二环绕式边框胶体31排列成一类似同心圆的图案。From the comparison of Fig. 3 and Fig. 1C, the difference from
实施例四Embodiment four
如图4A与图4B所示,本实用新型实施例四提供一种使用定电压电源供应器(图未示)的多晶封装结构Z,其包括:一基板单元1、一发光单元2、一限流单元C、一边框单元3及一封装单元4。As shown in Figure 4A and Figure 4B,
基板单元1具有一基板本体10、两个位于基板本体10上表面的第一置晶区域11、及一位于基板本体10上表面的第二置晶区域12。举例来说,基板本体10可具有一电路基板100、一设置于电路基板100底部的散热层101、多个设置于电路基板100上表面的导电焊垫102、及一设置于电路基板100上表面并用于露出多个导电焊垫102的绝缘层103。The
发光单元2具有至少一用于产生第一种色温的第一发光模块2a及至少一用于产生第二种色温的第二发光模块2b。第一发光模块2a具有多个电性设置于其中一第一置晶区域11上的第一发光二极管芯片20a,且第二发光模块2b具有多个电性设置于另外一第一置晶区域11上的第二发光二极管芯片20b。The
限流单元C具有多个电性设置于第二置晶区域12上的限流芯片C1。多个限流芯片C1电性连接于发光单元2,以提供一特定且稳定的电流分别给第一发光模块2a与第二发光模块2b使用。The current limiting unit C has a plurality of current limiting chips C1 electrically disposed on the second
边框单元3具有两个环绕地成形于基板本体10上表面的第一环绕式边框胶体30及一环绕地成形于基板本体10上表面的第二环绕式边框胶体31。两个第一环绕式边框胶体30分别围绕第一发光模块2a及第二发光模块2b,以分别形成两个相对应两个第一置晶区域11的第一胶体限位空间300,且第二环绕式边框胶体31围绕多个限流芯片C1,以形成一对应于第二置晶区域12的第二胶体限位空间310。此外,两个第一环绕式边框胶体30彼此分离一预定距离,且两个第一环绕式边框胶体30彼此并联地排列在基板本体10上,另外每一个第一环绕式边框胶体30与第二环绕式边框胶体31彼此分离一特定距离。The
封装单元4具有两个分别填充于两个第一胶体限位空间300内以分别覆盖第一发光模块2a及第二发光模块2b的第一封装胶体(40a、40b)及一填充于第二胶体限位空间310内以覆盖多个限流芯片C1的第二封装胶体41。每一个第一封装胶体(40a、40b)与第二封装胶体41彼此分离一特定距离,且每一个第一环绕式边框胶体30与第二封装胶体41彼此分离一特定距离。举例来说,其中一第一封装胶体40a可为一具有一第一颜色的荧光胶体,另外一第一封装胶体40b可为一具有一第二颜色的荧光胶体,且第二封装胶体41可为一具有遮光效果的不透光胶体。The
基板单元1更进一步包括有:至少一贯穿基板本体10的隔热狭缝13,且隔热狭缝13可位于发光单元2与限流单元C之间或位于其中一第一环绕式边框胶体30与第二环绕式边框胶体31之间,其中隔热狭缝13的功用与实施例一相同。The
第一组发光结构N1可包括:基板本体10、多个第一发光二极管芯片20a、其中一第一环绕式边框胶体30及其中一第一封装胶体40a。第二组发光结构N2可包括:基板本体10、多个第二发光二极管芯片20b、另外一第一环绕式边框胶体30及另外一第一封装胶体40b。The first group of light-emitting structures N1 may include: a
实施例五Embodiment five
由图5A与图4A(或图5B与图4B)的比较,与实施例四的不同在于:实施例五的边框单元3的两个第一环绕式边框胶体30可彼此并联排列且连接在一起。From the comparison between Fig. 5A and Fig. 4A (or Fig. 5B and Fig. 4B), the difference from
实施例六Embodiment six
由图6A与图5A(或图6B与图5B)的比较,与实施例五的不同在于:在实施例六中,每一个第一环绕式边框胶体30可为荧光胶体。换句话说,本实用新型可随着不同的需求而选择性地添加荧光粉于每一个第一环绕式边框胶体30内,进而有效降低发生于封装单元4的两个第一封装胶体(40a、40b)之间的暗带情况。From the comparison of FIG. 6A and FIG. 5A (or FIG. 6B and FIG. 5B ), the difference from the fifth embodiment is that in the sixth embodiment, each first surrounding frame colloid 30 can be a fluorescent colloid. In other words, the present invention can selectively add fluorescent powder in each first encircling frame colloid 30 according to different needs, thereby effectively reducing the occurrence of the two first encapsulation colloids (40a, 40a, 40b) The case of dark bands between.
实施例七Embodiment seven
如图7A与图7B所示,本实用新型实施例七提供一种使用定电压电源供应器(图未示)且用于增加电流量的多晶封装结构Z,其包括:一基板单元1、一发光单元2、一限流单元C、一边框单元3及一封装单元4。As shown in FIG. 7A and FIG. 7B , Embodiment 7 of the present utility model provides a polycrystalline packaging structure Z that uses a constant voltage power supply (not shown) and is used to increase the amount of current, which includes: a
基板单元1具有一基板本体10、两个位于基板本体10上表面的第一置晶区域11、及一位于基板本体10上表面的第二置晶区域12。发光单元2具有至少一用于产生第一种色温的第一发光模块2a及至少一用于产生第二种色温的第二发光模块2b。第一发光模块2a具有多个电性设置于其中一第一置晶区域11上的第一发光二极管芯片20a,且第二发光模块2b具有多个电性设置于另外一第一置晶区域11上的第二发光二极管芯片20b。限流单元C具有多个电性设置于第二置晶区域12上的限流芯片C1。多个限流芯片C1电性连接于发光单元2。The
边框单元3具有两个环绕地成形于基板本体10上表面的第一环绕式边框胶体(30a、30b)及一环绕地成形于基板本体10上表面的第二环绕式边框胶体31,且其中一个第一环绕式边框胶体30b围绕另外一个第一环绕式边框胶体30a,因此两个第一环绕式边框胶体(30a、30b)排列成一类似同心圆的图案。两个第一环绕式边框胶体(30a、30b)分别围绕第一发光模块2a及第二发光模块2b,以分别形成两个相对应两个第一置晶区域11的第一胶体限位空间300,第二发光模块2b位于两个第一环绕式边框胶体(30a、30b)之间,且第二环绕式边框胶体31围绕多个限流芯片C1,以形成一对应于第二置晶区域12的第二胶体限位空间310。The
封装单元4具有两个分别填充于两个第一胶体限位空间300内以分别覆盖第一发光模块2a及第二发光模块2b的第一封装胶体(40a、40b)及一填充于第二胶体限位空间310内以覆盖多个限流芯片C1的第二封装胶体41。The
第一组发光结构N1可包括:基板本体10、多个第一发光二极管芯片20a、其中一第一环绕式边框胶体30a及其中一第一封装胶体40a。第二组发光结构N2可包括:基板本体10、多个第二发光二极管芯片20b、另外一第一环绕式边框胶体30b及另外一第一封装胶体40b。具有较低色温的第一组发光结构N1被设置于内圈,而具有较高色温的第二组发光结构N2则设置于外圈。实施例八The first group of light emitting structures N1 may include: a
由图8与图7A的比较,与实施例七的不同在于:在实施例八中,第一组发光结构N1与第二组发光结构N2的位置相互颠倒,因此具有较低色温的第一组发光结构N1被设置于外圈,而具有较高色温的第二组发光结构N2则设置于内圈。From the comparison between Fig. 8 and Fig. 7A, the difference from Embodiment 7 is that in Embodiment 8, the positions of the first group of light-emitting structures N1 and the second group of light-emitting structures N2 are reversed, so the first group with a lower color temperature The light emitting structure N1 is disposed on the outer circle, and the second group of light emitting structures N2 with higher color temperature is disposed on the inner circle.
实施例九Embodiment nine
由图9A与图7A(或图9B与图7B)的比较,与实施例七的不同在于:在实施例九中,两个第一环绕式边框胶体(30a、30b)都可为荧光胶体。换句话说,本实用新型可随着不同的需求而选择性地添加荧光粉于两个第一环绕式边框胶体(30a、30b)内,以使得光源(如图9B中向上的箭头所示)能够被导引至两个第一封装胶体(40a、40b)之间,进而降低发生于两个第一封装胶体(40a、40b)之间的暗带情况。From the comparison of FIG. 9A and FIG. 7A (or FIG. 9B and FIG. 7B ), the difference from the seventh embodiment is that in the ninth embodiment, both the first surrounding frame colloids (30a, 30b) can be fluorescent colloids. In other words, the present invention can selectively add fluorescent powder in the two first surrounding frame colloids (30a, 30b) according to different needs, so that the light source (as shown by the upward arrow in Figure 9B) It can be guided between the two first packaging colloids (40a, 40b), thereby reducing the occurrence of dark bands between the two first packaging colloids (40a, 40b).
实施例十Embodiment ten
由图10与图7B的比较,与实施例七的不同在于:在实施例十中,内圈的第一环绕式边框胶体30a可为荧光胶体,而外圈的第一环绕式边框胶体30b可为反光胶体。换句话说,本实用新型可随着不同的需求而选择性地添加荧光粉于内圈的第一环绕式边框胶体30a内,以使得光源(如图10中向上的箭头所示)能够被导引至两个第一封装胶体(40a、40b)之间,进而降低发生于两个第一封装胶体(40a、40b)之间的暗带情况。此外,通过”外圈的第一环绕式边框胶体30b为反光胶体”的设计,以使得本实用新型所投出的光源能得到较佳的聚光效果。From the comparison between Fig. 10 and Fig. 7B, the difference from the seventh embodiment is that in the tenth embodiment, the first
另外,如图11所示,在实施例一至实施例十中,基板单元1具有多个设置于基板本体10上表面的正极焊垫P及多个设置于基板本体10上表面的负极焊垫N,每一个发光二极管芯片20具有一正极201及一负极202,每一个发光二极管芯片20的正极201相对应多个正极焊垫P中的至少两个,且每一个发光二极管芯片20的负极202相对应多个负极焊垫N中的至少两个。另外,导线单元W,其具有多条导线W1。每两条导线W1分别电性连接于每一个发光二极管芯片20的正极201与至少两个正极焊垫P中的其中一个之间及电性连接于每一个发光二极管芯片20的负极202与至少两个负极焊垫N中的其中一个之间。In addition, as shown in FIG. 11 , in
因为每一个发光二极管芯片的正极201与负极202分别具有至少一个备用正极焊垫P及至少一个备用负极焊垫N,所以当导线W1的一末端打在(焊接在)其中一个正极焊垫P或负极焊垫N上而失败时(造成浮焊,即导线W1与“正极焊垫P或负极焊垫N”之间没有产生电性连接),制造者不需清除因为打线失败而形成于正极焊垫P表面上的焊渣(或负极焊垫N表面上的焊渣),导线W1的一末端即可打在另外一个正极焊垫P(或另外一个负极焊垫N)上,以节省打线的时间(提升打线的效率)并增加打线的良率。Because the
综上所述,本实用新型除了可通过“将多个发光二极管芯片与多个限流芯片电性连接于同一基板单元上”的设计,以使得本实用新型的多晶封装结构可使用定电压电源供应器作为供电的源头,而且也可达到依据使用不同数量的发光二极管芯片以提供不同电流量供应的目的。To sum up, in addition to the design of "electrically connecting multiple light-emitting diode chips and multiple current-limiting chips to the same substrate unit", the utility model enables the polycrystalline packaging structure of the utility model to use constant voltage The power supply is used as the source of power supply, and can also achieve the purpose of supplying different amounts of current according to the number of LED chips used.
以上所述仅为本实用新型的较佳可行实施例,非因此局限本实用新型的保护范围,故凡运用本实用新型的说明书及附图内容所做的等效技术变化,均包含于本实用新型的保护范围内。The above descriptions are only preferred feasible embodiments of the present utility model, and are not intended to limit the protection scope of the present utility model. Therefore, all equivalent technical changes made by using the description and accompanying drawings of the present utility model are included in this utility model. new type of protection.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103165589A (en) * | 2011-12-08 | 2013-06-19 | 东莞柏泽光电科技有限公司 | Mixed light type polycrystal packaging structure |
CN103247749A (en) * | 2012-02-06 | 2013-08-14 | 东莞柏泽光电科技有限公司 | Multi-chip packaging structure and manufacturing method thereof |
EP2797128A4 (en) * | 2011-12-20 | 2015-08-12 | Citizen Holdings Co Ltd | LED MODULE |
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2010
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103165589A (en) * | 2011-12-08 | 2013-06-19 | 东莞柏泽光电科技有限公司 | Mixed light type polycrystal packaging structure |
EP2797128A4 (en) * | 2011-12-20 | 2015-08-12 | Citizen Holdings Co Ltd | LED MODULE |
US9508910B2 (en) | 2011-12-20 | 2016-11-29 | Citizen Holdings Co., Ltd. | LED module |
EP3220427A1 (en) | 2011-12-20 | 2017-09-20 | Citizen Watch Co., Ltd. | Led module |
US9887185B2 (en) | 2011-12-20 | 2018-02-06 | Citizen Watch Co., Ltd. | Packaging of LED chips and driver circuit on the same substrate |
CN103247749A (en) * | 2012-02-06 | 2013-08-14 | 东莞柏泽光电科技有限公司 | Multi-chip packaging structure and manufacturing method thereof |
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