CN201812417U - Mechanical and electronic signal detection and processing EDA comprehensive experiment box - Google Patents

Abstract

The utility model discloses a mechanical electronic signal detection processing EDA (Electronic Design Automation) comprehensive experiment box, which at least comprises an FPGA/CPLD (Field Programmable Gate Array/Complex Programmable Logic Devices) core module, a DAC (Data Acquisition Chassis) module, a DI/DO (Data Input/Data Output) module, an Encoder module and a bottom plate, wherein the modules are independent respectively; the bottom plate comprises the slot interfaces, the DSP (Digital Signal Processor) and ARM (Advanced RISC Machines) bus expansion interfaces and the KB/LED (KiloByte/Light-Emitting Diode) interfaces of the modules; and the modules are mutually connected with a signal wire through slots on the bottom plate. The utility model is suitable for the EDA comprehensive teaching experiments of mechanical electronics, can be connected with sensor signals on a mechanical platform through signal interfaces on the experiment box to detect and process various mechanical electronic signals and can also be connected with DSP and ARM teaching experiment boxes through the bus expansion interfaces to conduct the motion control comprehensive experiment of an integrated experiment platform. The utility model facilitates mechanical electronics major students to master the EDA technology and expands the application of the EDA technology in the mechanical field.

Description

Mechanical and electronic signal detection and processing EDA comprehensive experiment box

technical field

The utility model relates to a hardware experiment platform for the detection and processing of mechanical and electronic signals, in particular to a modular EDA comprehensive experiment box for the detection and processing of mechanical and electronic signals, which is used for domestic colleges and universities and vocational colleges to use the EDA comprehensive experiment box for mechanical Teaching experiment of electronic signal detection and processing.

Background technique

EDA is the abbreviation of Electronic Design Automation (Electronic Design Automation). EDA technology is to use the computer as a tool to complete the design of logic circuits on the EDA software platform with the hardware description language HDL. EDA is applied in various fields such as machinery, electronics, communications, aerospace, chemical industry, mining, biology, medicine, and military affairs.

At present, the existing EDA experiment box is mainly used for teaching experiments of electronic circuit design, PCB design and IC design in the fields of electronic engineering, computer, microelectronics and communication in colleges and universities. So far, there is no EDA teaching experiment box that can be used for the detection and processing of mechanical and electronic electronic signals, which is convenient for students majoring in mechanical and electronic to master EDA technology as soon as possible and expand the application of EDA technology in the mechanical field.

Contents of the invention

The proposal of the utility model aims to realize a kind of EDA teaching experiment box for the detection and processing of mechanical and electronic electronic signals, for various mechanical and electronic signals, such as sensors (encoder signals, grating ruler signals, position switch signal, etc.), to collect, detect and process, or to control the motor operation of the mechanical platform. The experiment box adopts a modular design scheme, has a variety of bus expansion interfaces, and has rich experimental content: in addition to completing the basic experiments of the existing EDA experiment box, it can mainly connect with peripherals through signal interfaces to realize various mechanical and electronic signals. Detection and processing experiments; in addition, the DSP bus expansion interface and the ARM bus expansion interface of the EDA comprehensive experiment box can be connected with the DSP teaching experiment box and the ARM embedded teaching experiment box respectively to form a comprehensive, advanced and high-tech movement Controlled comprehensive teaching experiment.

The technical scheme of the utility model is summarized as follows:

A mechanical electronic signal detection and processing EDA comprehensive experiment box is characterized in that: it at least comprises FPGA/CPLD core module, DAC module, DI/DO module, Encoder module and base plate; Described base plate comprises FPGA/CPLD core module slot interface , DAC module slot interface, DI/DO module slot interface, Encoder module slot interface, DSP bus expansion interface, ARM bus expansion interface, KB/LED interface; the FPGA/CPLD core module, DAC module, DI/DO The module and the Encoder module are independent, and are built on the backplane through the slot interface; the modules are connected through the backplane slots and the signal lines of the modules on the backplane; the FPGA/CPLD core module is at least composed of the first FPGA/CPLD module and the second FPGA/CPLD module, the first FPGA/CPLD module and the second FPGA/CPLD module are connected through IO pins; the output of the second FPGA/CPLD module is connected to the input of the DAC module; the The DI/DO module is connected to the second FPGA/CPLD module; the Encoder module is connected to the second FPGA/CPLD module; one end of the ARM bus expansion interface is connected to the first FPGA/CPLD module, and the other end can be connected to the peripheral ARM Embedded teaching experiment box connection; one end of the DSP bus extension interface is connected to the first FPGA/CPLD module, and the other end can be connected to the peripheral DSP teaching experiment box; one end of the KB/LED interface is connected to the first FPGA/CPLD Module connection, the other end can be connected with the peripheral keyboard/LED; the DAC module, DI/DO module, and Encoder module are connected with the peripheral device through the bus interface on the various modules.

The FPGA/CPLD core module is at least made up of a first FPGA/CPLD module and a second FPGA/CPLD module; each FPGA/CPLD module has an FPGA/CPLD chip, an independent power supply chip, an independent crystal oscillator, and a reset circuit , JTAG/AS download port; independent power chip, independent crystal oscillator, reset circuit, JTAG/AS download port are all connected to FPGA/CPLD chip.

The DAC module is at least composed of a first DAC module and a second DAC module; each DAC module is mainly composed of a digital-to-analog conversion circuit composed of a 16bit high-speed digital-to-analog conversion chip, a current signal to voltage signal circuit, a gain adjustment circuit, a single-ended Composed of a differential conversion circuit, an output limiting circuit and an output interface circuit; the digital-to-analog conversion circuit is connected to the current signal to voltage signal circuit, the current signal to voltage signal circuit is connected to the gain adjustment circuit, and the gain adjustment circuit is connected to the single-ended differential conversion circuit connected, the single-ended differential conversion circuit is connected with the output limiting circuit, and the output limiting circuit is connected with the output interface circuit.

The Encoder module is composed of a signal interface circuit connected to the encoder signal line, a differential single-ended signal conversion circuit, a high-speed optocoupler isolation circuit, a reverse Schmitt trigger and a signal interface circuit connected with the second FPGA/CPLD module Composition; the signal interface circuit connected to the encoder signal line is connected to the differential single-ended signal conversion circuit; the differential single-ended signal conversion circuit is connected to the high-speed optocoupler isolation circuit; the high-speed optocoupler isolation circuit and the reverse Schmitt trigger Connection; the reverse Schmitt trigger is connected with the signal interface circuit connected with the second FPGA/CPLD module.

The beneficial effects of the utility model are:

The utility model adopts the idea of modular design, which at least includes FPGA/CPLD core module, DAC module, DI/DO module, Encoder module and base plate, and each module is independent of each other; each module is connected through slot interface and signal line on the base plate ; The modules can be combined according to the experimental requirements and built on the bottom plate; the experiment box is suitable for EDA comprehensive teaching experiments for students majoring in mechatronics. Electronic signal detection and processing; in addition, through the DSP bus expansion interface and ARM bus expansion interface of the experiment box, it is connected with the DSP teaching experiment box and the ARM embedded teaching experiment box to form a comprehensive and innovative motion control in the mechatronics experiment platform teaching experiment.

Description of drawings

Figure 1 is a schematic diagram of the structure of the EDA comprehensive experiment box for mechanical and electronic signal detection and processing;

Figure 2 is an example diagram of the bottom plate layout of the EDA comprehensive experiment box.

Detailed ways

Below in conjunction with accompanying drawing, the utility model is further described.

The utility model mechanical electronic signal detection processing EDA comprehensive experiment box structure, as shown in Figure 1, this EDA comprehensive experiment box, at least comprises FPGA/CPLD core module, DAC module, DI/DO module, Encoder module, and base plate; Said The FPGA/CPLD core module is at least made up of a first FPGA/CPLD module and a second FPGA/CPLD module, the first FPGA/CPLD module and the second FPGA/CPLD module are connected by IO pins; the second FPGA/CPLD The module output terminal is connected with the DAC module input terminal; the DI/DO module is connected with the second FPGA/CPLD module; the Encoder module is connected with the second FPGA/CPLD module;

As shown in the layout of the backplane in Figure 2, the backplane includes two slot interfaces for FPGA/CPLD modules, two slot interfaces for DAC modules, slot interfaces for DI/DO modules, slot interfaces for Encoder modules, and DSP bus expansion interfaces , ARM bus expansion interface, KB/LED interface; the FPGA/CPLD core module, DAC module, DI/DO module, and Encoder module are independent of each other, and are built on the backplane through the slot interface; the modules are connected through the backplane slot Connect with the signal lines of each module on the base plate; one end of the ARM bus extension interface is connected with the first FPGA/CPLD module, and the other end is connected with the ARM embedded teaching experiment box; the DSP bus extension interface is connected with the first FPGA/CPLD module at one end. The CPLD module is connected, and the other end is connected with the DSP teaching experiment box; the KB/LED interface is connected with the first FPGA/CPLD module, and the other end is connected with the peripheral keyboard/LED; the DAC module, DI/DO module, Encoder module Connect with peripherals through bus interface.

The FPGA/CPLD core module is at least composed of a first FPGA/CPLD module and a second FPGA/CPLD module; each FPGA/CPLD module has an FPGA/CPLD chip, an independent power chip, an independent crystal oscillator, a reset circuit, and a JTAG /AS download port. Independent power supply chip, independent crystal oscillator, reset circuit, JTAG/AS download port are all connected with FPGA/CPLD chip.

The DAC module is at least composed of a first DAC module and a second DAC module; each DAC module is mainly composed of a digital-to-analog conversion circuit composed of a 16bit high-speed digital-to-analog conversion chip, a current signal to voltage signal circuit, a gain adjustment circuit, and a single-ended differential conversion. circuit, output limiting circuit and output interface circuit; the input of the digital-to-analog conversion circuit is connected to the output of the second FPGA/CPLD module; the output of the digital-to-analog conversion circuit is connected to the current signal to voltage signal circuit, and the current signal to voltage signal circuit It is connected with the gain adjustment circuit, the gain adjustment circuit is connected with the single-end differential conversion circuit, the single-end differential conversion circuit is connected with the output limiting circuit, the output limiting circuit is connected with the output interface circuit, and the output interface is connected with the peripheral.

The Encoder module is composed of a signal interface circuit connected to the encoder signal line, a differential single-ended signal conversion circuit, a high-speed optocoupler isolation circuit, a reverse Schmitt trigger and a signal interface circuit connected to the second FPGA/CPLD module; The signal interface circuit connected with the encoder signal line is connected with the differential single-ended signal conversion circuit; the differential single-ended signal conversion circuit is connected with the high-speed optocoupler isolation circuit; the high-speed optocoupler isolation circuit is connected with the reverse Schmitt trigger; The Schmitt trigger is connected with the signal interface circuit connected with the second FPGA/CPLD module, and the signal processing is completed by the FPGA/CPLD.

The limit switch and proximity switch in the mechanical platform are respectively connected to the DI/DO module in the EDA comprehensive teaching experiment box; the encoder signal and grating ruler signal in the mechanical platform are connected to the Encoder module in the EDA comprehensive experiment box; The control signal of the motor can be connected with the DAC module and DI/DO module in the EDA comprehensive experiment box; the program written in the hardware description language can be downloaded to the FPGA/CPLD chip through the JTAG/AS download interface on the second FPGA/CPLD module, so as to realize the The collection, processing and control of the sensor signals of the mechanical platform are combined to form a comprehensive teaching experiment of mechatronics.

As shown in Figure 1, the DSP teaching experiment box and the ARM embedded teaching experiment box are respectively connected to the first FPGA/CPLD module in the EDA comprehensive experiment box through the DSP bus expansion interface and the ARM bus expansion interface on the bottom plate of the EDA comprehensive experiment box. The first FPGA/CPLD module realizes the dual-port RAM function through hardware description language programming, so that the DSP teaching experiment box, ARM embedded teaching experiment box, and EDA comprehensive experiment box constitute a comprehensive and innovative teaching experiment of a high-performance motion controller .

In this description, it should be pointed out that the above embodiments are only representative examples of the present invention. Obviously, the utility model is not limited to the above-mentioned specific embodiments, and various modifications, transformations and deformations can also be made. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive. Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention shall be deemed to belong to the protection scope of the present invention.

Claims (4)

1. a mechanical electronic signal detection processing EDA comprehensive experiment box is characterized in that: it at least comprises FPGA/CPLD core module, DAC module, DI/DO module, Encoder module and base plate; Described base plate comprises FPGA/CPLD core module plug Slot interface, DAC module slot interface, DI/DO module slot interface, Encoder module slot interface, DSP bus expansion interface, ARM bus expansion interface, KB/LED interface; the FPGA/CPLD core module, DAC module, DI The /DO module and the Encoder module are independent of each other, and are built on the backplane through the slot interface; the modules are connected through the backplane slot and the signal lines of each module on the backplane; the FPGA/CPLD core module is at least composed of the first FPGA /CPLD module and the second FPGA/CPLD module, the first FPGA/CPLD module and the second FPGA/CPLD module are connected through IO pins; the output end of the second FPGA/CPLD module is connected to the input end of the DAC module; The DI/DO module is connected with the second FPGA/CPLD module; the Encoder module is connected with the second FPGA/CPLD module; one end of the ARM bus expansion interface is connected with the first FPGA/CPLD module, and the other end can be connected with an external Establish the connection of ARM embedded teaching experiment box; one end of the DSP bus extension interface is connected with the first FPGA/CPLD module, and the other end can be connected with the peripheral DSP teaching experiment box; one end of the KB/LED interface is connected with the first FPGA /CPLD module connection, and the other end can be connected with the peripheral keyboard/LED; the DAC module, DI/DO module, and Encoder module are connected with the peripherals through the bus interfaces on various modules. 2. the EDA comprehensive experiment box of mechanical electronic signal detection process according to claim 1 is characterized in that: described FPGA/CPLD core module is at least made up of the first FPGA/CPLD module and the second FPGA/CPLD module; Each FPGA/CPLD module has an FPGA/CPLD chip, an independent power chip, an independent crystal oscillator, a reset circuit, and a JTAG/AS download port; an independent power chip, an independent crystal oscillator, a reset circuit, and a JTAG/AS download port are all connected FPGA/CPLD chip connection. 3. the EDA comprehensive experiment box of mechanical electronic signal detection processing according to claim 1, is characterized in that: described DAC module, at least is made up of the first DAC module and the second DAC module; Each DAC module mainly consists of 16bit high-speed A digital-to-analog conversion circuit composed of a digital-to-analog conversion chip, a current signal to voltage signal circuit, a gain adjustment circuit, a single-ended differential conversion circuit, an output limiting circuit and an output interface circuit; the digital to analog conversion circuit and the current signal to voltage signal The circuit is connected, the current signal to voltage signal circuit is connected to the gain adjustment circuit, the gain adjustment circuit is connected to the single-end differential conversion circuit, the single-end differential conversion circuit is connected to the output limiting circuit, and the output limiting circuit is connected to the output interface circuit. 4. the EDA comprehensive experiment box of mechanical electronic signal detection processing according to claim 1, is characterized in that: described Encoder module, by the signal interface circuit that is connected with encoder signal line, differential single-ended signal conversion circuit, high-speed optical Composed of a coupling isolation circuit, a reverse Schmitt trigger and a signal interface circuit connected to the second FPGA/CPLD module; the signal interface circuit connected to the encoder signal line is connected to a differential single-ended signal conversion circuit; a differential single-ended The signal conversion circuit is connected with the high-speed optocoupler isolation circuit; the high-speed optocoupler isolation circuit is connected with the reverse Schmitt trigger; the reverse Schmitt trigger is connected with the signal interface circuit connected with the second FPGA/CPLD module.

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