CN201752139U - Fractional-dedicated physical channel processing device - Google Patents

Abstract

The utility model relates to a WCDMA terminal, in particular to a partial dedicated physical channel processing device. The device disclosed in the utility model includes an F-DPCH receiving and processing module, a CER statistics module, an inner loop power control module and an outer loop power control module, and the outer loop power control module includes a SIR adjustment step calculation unit, a SIR target value calculation unit and a comparison The unit, the SIR adjustment step calculation unit, calculates the adjustment step of the SIR target value according to the estimated CER value, the TPC instruction accuracy target value and the power control step; the SIR target value calculation unit, according to the calculated SIR target value The adjustment step Calculate the SIR target value; the comparison unit compares the calculated SIR target value with the maximum and minimum values in the SIR setting value, and determines the SIR target value of the outer loop power control module according to the comparison result, and sends it to the inner loop power control module. The technical scheme of the utility model improves the precision of the SIR estimation algorithm.

Description

A kind of fractional dedicated physical channel processing unit

Technical field

The present invention relates to WCDMA (Wideband Code Division Multiple Access, Wideband Code Division Multiple Access (WCDMA) inserts) terminal, particularly a kind of fractional dedicated physical channel processing unit.

Background technology

At HSDPA (High Speed Downlink Packet Access, the expression high speed downlink packet access technology) in, each user is dispensed on the dedicated channel DPCH (Dedicated Physical Channel, DPCH) in the both direction (uplink and downlink link) so that exchange high-level signaling information between subscriber equipment (UE) and radio network controller (RNC).In order to reduce in the sub-district owing to there being a large amount of HSDPA users and to OVSF (Orthogonal Variable SpresdingFactor, Orthogonal Variable Spreading Factor OVSF) Ma waste, the WCDMA R6 stage has been introduced fractional dedicated physical channel (F-DPCH), the power control commands bit that is used to carry up channel carries out the inner and outer ring power control, and the functions such as synchronous/asynchronous judgement that are used for descending reception.The frame structure of F-DPCH is characterized in only ordering at second symbol transmission TPC (through-put power control) of each time slot as shown in Figure 1, and other symbols send DTX (Discontinuous Transmission, discontinuous transmission).

At present, patent WO2006122779 provides a kind of communication channel error rate method of estimation and device, be primarily aimed in F-DPCH and handle, wherein mentioned and directly utilized the TPC symbol to carry out SIR (Signal toInterference Ratio, signal-to-jamming ratio) estimation, but there is the limited problem of SIR estimation precision in this method; Adopt target CER (TPC command error rate, TPC instruction errors rate) mapping SIR to determine the method for sir target value in addition, be subjected to the influence that CER and SIR mapping table are made precision; Carry out external circule power control method for another based on CER, compare by CER and the target CER that estimates, the sir target value is raised or downward modulation, this method is difficult to make CER to converge on the CER desired value.

The utility model content

Technical problem to be solved in the utility model is to provide a kind of fractional dedicated physical channel (F-DPCH) processing unit, to improve the quality of power control.

In order to address the above problem, the utility model discloses a kind of fractional dedicated physical channel (F-DPCH) processing unit, comprise F-DPCH receiving processing module, through-put power control (TPC) instruction errors rate (CER) statistical module, inner-loop power control module and external circule power control module, described external circule power control module comprises signal-to-jamming ratio (SIR) adjustment step size computation unit, sir target value computing unit and comparing unit, wherein:

Described SIR adjusts the step size computation unit, is used for measuring the adjustment step-length that CER value, TPC instruction accuracy desired value and the power control step-size estimated calculate the sir target value according to described CER statistical module;

Described sir target value computing unit is used for adjusting according to described SIR the adjustment step size computation sir target value of the sir target value of being calculated the step size computation unit;

Described comparing unit, be used for the sir target value of described sir target value computing unit calculating and the maximum and the minimum value of the SIR value of setting are compared respectively, determine the sir target value of external circule power control module according to comparative result, and send to described inner-loop power control module.

Further, in the said apparatus, described SIR adjusts the step size computation unit and comprises adder, divider and multiplier, wherein:

Described adder is used for that described CER statistical module is measured CER value and the negate of target CER value estimated and handles, and the data after will handling inputs to described divider;

Described divider be used for the data and the TPC instruction accuracy desired value of described adder input are handled, and the data after will handling is input to described multiplier;

Described multiplier is used for the data and the power control step-length of the input of described divider are handled, and obtains the adjustment step-length of sir target value, and the adjustment step-length of described sir target value is input to described sir target value computing unit.

Further, in the said apparatus, sir target value computing unit comprises adder, delayer and sir target value calculator, wherein:

Described delayer is used for feeding back to described adder the adjustment step-length of last sir target value;

Described adder, the adjustment step-length that is used for the SIR that described SIR adjusts the input of step size computation unit is adjusted the last sir target value of step-length and described delayer feedback is carried out addition process, and the data after will handling are input to described sir target value calculator;

Described sir target value calculator according to the adjustment step-length of the sir target value after the described adder processing, calculates current sir target value, and is input in the described comparing unit.

Further, in the said apparatus, described comparing unit comprises first comparator and second comparator, wherein:

Described first comparator, be used for the sir target value of described sir target value computing unit input and the maximum of the SIR value of setting are compared, if the sir target value of described sir target value computing unit input is greater than the maximum in the SIR value of setting, then the maximum in the SIR value of setting is inputed to described inner-loop power control module as the sir target value of external circule power control, if the sir target value of described sir target value computing unit input is less than the maximum in the SIR value of setting, then the sir target value with described sir target value computing unit input inputs to described second comparator;

Described second comparator, be used for the sir target value of described sir target value computing unit input and the minimum value of the SIR value of setting are compared, if the sir target value of described sir target value computing unit input is greater than the minimum value in the SIR value of setting, then the sir target value that sir target value computing unit is imported inputs to described inner-loop power control module as the sir target value of external circule power control, if the sir target value of sir target value computing unit input is less than the minimum value in the SIR value of setting, then the minimum value in the SIR value of setting is inputed to described inner-loop power control module as the sir target value of external circule power control.

Wherein, described inner-loop power control module comprises N SIR estimation unit, SIR merge cells and uplink power control instruction generation unit, data after described N SIR estimation unit will be handled all input to described SIR merge cells and handle, and the data after described SIR merge cells will be handled input to described uplink power control instruction generation unit.

Each SIR estimation unit further comprises first power calculator, second power calculator, the 3rd power calculator, the first cumulative mean device, the second cumulative mean device, adder, SIR calculator and filter, wherein:

Common Pilot Channel (CPICH) symbol after described first power calculator is handled described F-DPCH receiving processing module is handled, and result inputed to the described first cumulative mean device, after handling input information, the described first cumulative mean device inputs to described adder;

CPICH symbol after the described second cumulative mean device is handled described F-DPCH receiving processing module is handled, and result inputed to described second power calculator, described second power calculator inputs to described adder after input information is handled;

Described adder is input to described filter after the information negate of the information of described first cumulative mean device input and the input of described second power calculator handled and handles, and the result after described filter will be handled inputs to described SIR calculator;

F-DPCH symbol after described the 3rd power calculator is handled described F-DPCH receiving processing module is handled, and result is inputed to described SIR calculator;

Described SIR calculator is according to received information calculations SIR estimated value, and the SIR estimated value is inputed to described SIR merge cells.

Each SIR estimation unit further comprises power calculator, adder, squarer, cumulative mean device, SIR calculator and filter, wherein:

Described adder, the real part and the imaginary part negate of the CPICH symbol after the described F-DPCH receiving processing module processing are handled, result after handling is inputed to described squarer to be handled, result after described squarer will be handled inputs to described cumulative mean device and handles, result after described filter is handled described cumulative mean device carries out Filtering Processing, and the result after handling is inputed to described SIR calculator;

F-DPCH symbol after described power calculator is handled described F-DPCH receiving processing module is handled, and result is inputed to described SIR calculator;

Described SIR calculator is according to received information calculations SIR estimated value, and the SIR estimated value is inputed to described SIR merge cells.

Described CER statistical module comprises comparing unit, initial BER statistic unit and BER and CER map unit, wherein:

The TPC real part and the TPC imaginary part of the F-DPCH symbol after described comparing unit is handled described F-DPCH receiving processing module compare, comparative result is input to described initial BER statistic unit, described initial BER statistic unit is handled according to the comparative result and the statistical window length of described comparing unit, result after handling is inputed to described BER and the CER map unit is handled, the result after described BER and CER map unit will be handled inputs to described external circule power control module.

Described F-DPCH receiving processing module comprises N channel bank, and the symbol combiner that all links to each other with N channel bank.

Described each channel bank further comprises first descrambler, first despreader, second descrambler, second despreader, channel estimator and channel compensator, wherein:

The single drive signal that described first descrambler and first despreader are received by CPICH descrambling information and despreading information butt joint is handled, the single drive signal that described second descrambler and second despreader are received by F-DPCH descrambling information and despreading information butt joint is handled, based on the CPICH symbol behind the descrambling and de-spreading, channel estimator is finished channel estimating, CPICH symbol behind the descrambling and de-spreading, F-DPCH symbol and channel estimation value are exported to described symbol combiner after handling by channel compensator.

Technical solution of the present invention has improved the precision of SIR algorithm for estimating, the inaccurate shortcoming of sum of errors interference power estimation of having avoided channel estimating to introduce, and the CER value well converges on the CER desired value in the external circule power control.In addition, technical solution of the present invention can abundant multiplexing WCDMA DPCH processing hardware resource.

Description of drawings

Fig. 1 is the F-DPCH wireless frame structure;

Fig. 2 is the structural representation of F-DPCH processing unit provided by the invention;

Fig. 3 is the concrete structure figure of F-DPCH processing unit provided by the invention;

Fig. 4 is first kind of structure chart of F-DPCH SIR estimation unit in the inner-loop power control module provided by the invention;

Fig. 5 is second kind of structure chart of F-DPCH SIR estimation unit in the inner-loop power control module provided by the invention;

Fig. 6 is the structural representation of CER statistical module provided by the invention;

Fig. 7 is the structural representation of inner and outer ring power control module provided by the invention;

Fig. 8 is that external circule power control module shown in Figure 7 is carried out the flow chart that F-DPCH sir target value is adjusted.

Embodiment

Below in conjunction with drawings and the specific embodiments being described in further detail to technical solution of the present invention.

A kind of F-DPCH processing unit as shown in Figure 2, comprises F-DPCH receiving processing module, CER statistical module, inner-loop power control module, external circule power control module and synchronous/asynchronous discrimination module.Wherein, the CER statistical module all links to each other with the F-DPCH receiving processing module with the inner-loop power control module, the CER statistical module links to each other with the inner-loop power control module by the external circule power control module, and synchronous/step-out discrimination module can link to each other with the CER statistical module, perhaps synchronously/and step-out discrimination module and inner-loop power control module.Introduce the function of each module below.

The F-DPCH receiving processing module mainly uses the Rake receiver that the F-DPCH channel data is handled, and the result after handling is inputed to CER statistical module and inner-loop power control module;

The F-DPCH receiving processing module specifically can comprise N processing unit, and the F-DPCH symbol that all links to each other with N processing unit merges module, wherein, each channel bank further comprises first descrambler, first despreader, second descrambler, second despreader, channel estimator and channel compensator and symbol combiner, as shown in Figure 3:

Wherein, the F-DPCH receiving processing module can realize that the N of a F-DPCH receiving processing module processing unit is the multipath processing unit of Rake receiver by the Rake receiver, and the value of N equals the footpath number of Rake receiver.

First descrambler and first despreader are by CPICH (CommonPilotChannel, Common Pilot Channel) single drive signal of descrambling information and despreading information butt joint receipts is handled, the single drive signal that second descrambler and second despreader are received by F-DPCH descrambling information and despreading information butt joint is handled, based on the CPICH symbol behind the descrambling and de-spreading, channel estimator is finished channel estimating, CPICH symbol behind the descrambling and de-spreading, after F-DPCH symbol and channel estimation value are handled by channel compensator, export to the inner-loop power control module, the F-DPCH that while symbol combiner obtains after multipath is compensated carries out the TPC symbol and merges.Herein, by disposing different parameter (for example diversity mode, obtain parameters such as TPC character position), the F-DPCH receiving processing module can complete multiplexing WCDMA in the DPCH hardware resource, do not need to increase extra resource, the F-DPCH receiving processing module is handled the single drive signal that receives, and the F-DPCH symbol after will handling carries out the TPC merging;

Particularly, the TPC symbol that obtains through channel compensation in the F-DPCH receiving processing module can be by the TPC symbol R behind the descrambling and de-spreading _TPCObtain according to following formula:

$\mathrm{TPC}=R_{\mathrm{TPC}}{({\hat{h}}_1+{\hat{h}}_2)}^{*}$

In implementation procedure, receive the hardware resource of handling in order not increase extra F-DPCH, can multiplexing DPCH processing hardware resource.Yet F-DPCH there are differences on processing and the DPCH under the STTD pattern.Though there is the STTD pattern in F-DPCH, the TPC symbol does not carry out the STTD coding, but F-DPCH and DPCH handle the certain relation of but existence, and during promptly DPCH handled, under closed loop transmit diversity modes, its channel estimating was as follows:

${\hat{h}}_1^{\′}=w_1\·{\hat{h}}_1+w_2\·{\hat{h}}_2$

${\hat{h}}_2^{\′}=0$

W wherein ₁, w ₂Weight factor for antenna 1,2.By relatively obtaining, if adopt w ₁=w ₂=1 configuration just can support F-DPCH to handle easily, and hardware flexibility obtains bigger performance.

Inner-loop power control module, this module are mainly used in finishes the SIR estimation, by comparing with the sir target value, produces uplink transmission power control TPC;

In the present embodiment, for fear of the error that channel estimating is introduced, can adopt single footpath SIR estimation process; Wherein, because the TPC symbol is very few, the interference power estimation may be inaccurate, so need to adopt the CPICH channel to carry out Interference Estimation.The SIR that obtains Dan Jing thus estimates, according to the sub-district indication information of Multipath searching module output, the multipath SIR of Serving cell merged, and obtains total SIR.This partial function also can be supported by DPCH SIR estimation unit fully;

Particularly, the inner-loop power control module includes N SIR estimation unit (it is corresponding with each processing unit in the F-DPCH receiving processing module), SIR merge cells and uplink power control instruction generation unit, wherein, data after N SIR estimation unit will be handled all input to described SIR merge cells and handle, data after described SIR merge cells will be handled input to described uplink power control instruction generation unit, wherein, the structure of each SIR estimation unit can adopt any in following two kinds of schemes:

First kind of scheme, as shown in Figure 4: each SIR estimation unit further comprises first power calculator, second power calculator, the 3rd power calculator, the first cumulative mean device, the second cumulative mean device, adder, SIR calculator and filter, wherein: the CPICH symbol after first power calculator is handled described F-DPCH receiving processing module is handled, and result inputed to the described first cumulative mean device, after handling input information, the described first cumulative mean device inputs to described adder; CPICH symbol after the described second cumulative mean device is handled described F-DPCH receiving processing module is handled, and result inputed to described second power calculator, described second power calculator inputs to described adder after input information is handled; Described adder is input to described filter after the information negate of the information of described first cumulative mean device input and the input of described second power calculator handled and handles, and the result after described filter will be handled inputs to described SIR calculator; F-DPCH symbol after described the 3rd power calculator is handled described F-DPCH receiving processing module is handled, and result is inputed to described SIR calculator; Described SIR calculator is according to received information calculations SIR estimated value, and the SIR estimated value is inputed to described SIR merge cells;

In first kind of scheme, concrete SIR computational methods are as follows:

$I=\frac{1}{10}\underset{k=0}{\overset{9}{\mathrm{\Σ}}}{P}_k^2-{\left(\frac{1}{10}\underset{k=0}{\overset{9}{\mathrm{\Σ}}}{P}_k\right)}^2$

Wherein, P is the CPICH symbol behind the channel compensation, and the interference power that calculates is carried out smoothing processing by filter, and filter adopts the first order IIR filtering device, and filtering parameter can select 1/8,1/16 etc.In order to improve the power estimated value, the signal power estimated value gets interference power after need deducting filtering.Just can try to achieve the sir value of Dan Jing like this based on signal power and interference power, by the Finger indication of Multipath searching configuration, the SIR estimated value of same sub-district be carried out addition then, then obtain the total SIR estimated value in this sub-district.

Second kind of scheme, as shown in Figure 5, each SIR estimation unit further comprises power calculator, adder, squarer, the cumulative mean device, SIR calculator and filter, wherein: described adder, the real part and the imaginary part negate of the CPICH symbol after the described F-DPCH receiving processing module processing are handled, result after handling is inputed to described squarer to be handled, result after described squarer will be handled inputs to described cumulative mean device and handles, result after described filter is handled described cumulative mean device carries out Filtering Processing, and the result after handling is inputed to described SIR calculator; F-DPCH symbol after described power calculator is handled described F-DPCH receiving processing module is handled, and result is inputed to described SIR calculator; Described SIR calculator is according to received information calculations SIR estimated value, and the SIR estimated value is inputed to described SIR merge cells.

In second kind of scheme, concrete SIR computational methods are as follows:

$I=\frac{1}{10}\underset{k=0}{\overset{9}{\mathrm{\Σ}}}{(P_{k,r}-P_{k,i})}^2$

Wherein, P _{K, r}, P _{K, i}Represent CPICH symbol real part and imaginary part behind the channel compensation respectively.

The CER statistical module, because F-DPCH external circule power control module is to handle based on the CER of TPC, so this module is mainly carried out the CER statistics with the TPC symbol after the merging of F-DPCH receiving processing module;

In the present embodiment, the CER statistical module carries out BER according to a preliminary estimate earlier to the merging TPC symbol of F-DPCH receiving processing module output, in order to reduce deviation true and actual estimation, can make the mapping table between a true CER and the estimation BER, finish actual BER to the conversion between the CER, particularly, the CER statistical module further comprises the symbol judgement unit, BER statistic unit and BER and CER map unit, as shown in Figure 6, wherein, the TPC symbol real part and the TPC imaginary part of symbol symbol of the F-DPCH symbol after comparing unit is handled described F-DPCH receiving processing module compare, it is opposite symbol polarity to occur, then think the mistake that a bit occurs, comparative result is input to described initial BER statistic unit, described initial BER statistic unit is handled according to the comparative result and the statistical window length of described comparing unit, result after handling is inputed to described BER and the CER map unit is handled, the result after described BER and CER map unit will be handled inputs to described external circule power control module.

Particularly, separate in supposition TPC real part and imaginary part, and under the real part situation identical with imaginary part BER, can be similar to and obtain real CER and the unified relational expression of initially estimating between the BER.Here can adopt the mapping table of making between a true CER and the initial estimation BER.Mapping can be adopted under the multiple channel circumstance, and the mean value of emulation carries out.The real CER value that conversion by mapping table just can obtain estimating.This part can be realized by hardware, reaches operation efficiently.

The external circule power control module, mainly act as and dynamically adjust target SIR, thereby keep the predeterminated target quality that network issues, this module can be by the CER of utilization estimation and the CER desired value of network settings, adjust formula by the sir target value, finish the sir target value and calculate, the sir target value conduct that obtains is inner-loop power control desired value relatively next, and this algorithm can guarantee that CER converges on the CER desired value.

Particularly, the external circule power control module can comprise that SIR adjusts step size computation unit, sir target value computing unit and comparing unit, wherein:

SIR adjusts the step size computation unit, is used for measuring the side-play amount that CER value, TPC instruction accuracy desired value and the power control step-size estimated calculate the sir target value according to described CER statistical module;

In the present embodiment, SIR adjusts the step size computation unit as shown in Figure 7, comprise adder,, divider, multiplier, described adder, be used for that the CER statistical module is measured CER value and the negate of target CER value estimated and handle, and the data after will handling input to divider; Divider be used for the data and the TPC instruction accuracy desired value of adder input are handled, and the data after will handling is input to multiplier; Multiplier is used for the data and the power control step-length of described divider input are handled, and obtains the adjustment step-length of sir target value, and the adjustment step-length of sir target value is input to sir target value computing unit;

Sir target value computing unit, the side-play amount that is used for adjusting according to described SIR the sir target value of being calculated the step size computation unit is calculated the sir target value;

In the present embodiment, sir target value computing unit comprises adder, delayer and sir target value calculator as shown in Figure 7; Adder, the adjustment step-length that is used for SIR is adjusted the last sir target value of the adjustment step-length of sir target value of step size computation unit input and delayer feedback is carried out addition process, and the data after will handling are input to sir target value calculator; Sir target value calculator according to the adjustment step-length (side-play amount that also can be called the sir target value) of the sir target value after the adder processing, calculates current sir target value.Comparing unit is used for the sir target value of sir target value computing unit calculating and the maximum and the minimum value of the DL SIR value of setting are compared respectively, determines the sir target value of external circule power control module according to comparative result, and sends to the inner-loop power control module;

In the present embodiment, comparing unit comprises first comparator and second comparator as shown in Figure 7, wherein: described first comparator, be used for the sir target value of described sir target value computing unit input and the maximum of the DL SIR value of setting are compared, if the sir target value of described sir target value computing unit input is greater than the maximum in the DL SIR value of setting, then the maximum in the DL SIR value of setting is inputed to described inner-loop power control module as the sir target value of external circule power control, if the sir target value of described sir target value computing unit input is less than the maximum in the DL SIR value of setting, then the sir target value with described sir target value computing unit input inputs to described second comparator; Described second comparator, be used for the sir target value of described sir target value computing unit input and the minimum value of the DL SIR value of setting are compared, if the sir target value of described sir target value computing unit input is greater than the minimum value in the DL SIR value of setting, then the sir target value that sir target value computing unit is imported inputs to described inner-loop power control module as the sir target value of external circule power control, if the sir target value of sir target value computing unit input is less than the minimum value in the DL SIR value of setting, then the minimum value in the DL SIR value of setting is inputed to described inner-loop power control module as the sir target value of external circule power control;

Particularly, the computational process that the external circule power control module is carried out external circule power control sir target value as shown in Figure 8, the external circule power control module receives the CER of statistics and TPC that network issues order error rate desired value, just carries out the calculating of external circule power control sir target value, and computing formula is as follows:

${\mathrm{SIR}}_{k+1}={\mathrm{SIR}}_k+\frac{S}{1-{\mathrm{CER}}_t}({\mathrm{CER}}_{\mathrm{est}}-{\mathrm{CER}}_t)$

Wherein, S is the power control step-length that sets in advance, as 1dB, and CER _iBe TPC order error rate desired value, its scope is [0.01,0.1], and adjusting step-length is 0.01, CER _EstBe the order of the TPC in current statistical window error rate estimated value, it is through the correction of initial estimate.The length of statistical window is unit with the frame, can also can be the number frame for a frame.In fact, rise of sir target value or downward modulation step-length (being the adjustment step-length of sir target value) are in the following formula:

${\mathrm{\Δ}}_k=\frac{S}{1-{\mathrm{CER}}_t}({\mathrm{CER}}_{\mathrm{est}}-{\mathrm{CER}}_t)$

Work as Δ _k＜0, represent that current sir target value needs downward modulation; On the contrary, work as Δ _k＞0, represent that current sir target value needs to raise.Adjusted sir target value is SIR _k+ Δ _kFrom the SIR computing formula as can be known, under continuous reception condition, because statistical window length is once determining that the TPC symbol numbers of statistics is identical, the CER value will converge on CER like this _t, reach the purpose of external circule power control.

Owing to be subjected to the restriction of DL SIR adjusting range in the adjusted sir target value reality, carry out following processing here:

SIR _k+1＝max(SIR _min，min(SIR _k+1，SIR _max))

The SIR of initial setting up can adopt the mapping table of formulating between SIR and the true CER.Because under the various channel circumstances, the mapping of table there are differences, and can adopt the mean value of asking under the multiple channel circumstance to finish.

Synchronous/asynchronous discrimination module, be used for by detecting the quality of Radio Link, judge whether data sync, thereby whether decision keeps Internet resources, wherein, synchronous/asynchronous discrimination module calculates the quality indication of the synchronous/asynchronous differentiation of F-DPCH earlier, again according to synchronous/asynchronous differentiation quality indication, stage by stage with the threshold value Q of prior setting _InAnd Q _OutCompare, judge whether synchronously.

This module can be calculated the quality indication of the synchronous/asynchronous differentiation of F-DPCH based on dual mode, first kind of mode is to utilize average in synchronous/asynchronous statistical window of signal power S after SIR merges in the inner-loop power control module and interference power I, tries to achieve the quality indication of total sir value as the synchronous/asynchronous differentiation of F-DPCH; Particularly, calculate according to following formula earlier:

$S_{\mathrm{total}}=\underset{j=0}{\overset{L-1}{\mathrm{\Σ}}}\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{S}_{\mathrm{ij}}$

$I_{\mathrm{total}}=\underset{i=0}{\overset{L-1}{\mathrm{\Σ}}}\underset{j=0}{\overset{M-1}{\mathrm{\Σ}}}{I}_{\mathrm{ij}}$

Wherein, S _IjBe the signal power estimated value in i time slot j footpath, I _IjBe the signal interference power estimated value in i time slot j footpath, M is the effective diameter number of the configuration rake receiver of F-DPCH Serving cell, and L is a measurement window length.The 3GPP agreement has been made concrete regulation to synchronous/asynchronous, needs to support the measurement window of 40ms and 160ms, and every time slot upgrades, so adopt sliding window method, the SIR merge cells includes combined signal power and merges the interference power output function simultaneously;

Another kind of mode is the result who makes full use of the CER statistical module, directly utilize the correction CER in the protocol requirement statistical window to indicate the CER that directly utilizes in the statistic window of revising as quality evaluation as the quality of the synchronous/asynchronous differentiation of F-DPCH, same statistical window also need be supported 40ms and 160ms on original external circule power control CER statistical window basis.

Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of claim of the present invention.

Claims (10)

1. A part of dedicated physical channel F-DPCH processing device, comprising F-DPCH receiving processing module, transmission power control TPC command error rate CER statistics module, inner loop power control module and outer loop power control module, it is characterized in that, The outer loop power control module includes a signal-to-interference ratio SIR adjustment step calculation unit, an SIR target value calculation unit and a comparison unit, wherein: The SIR adjustment step calculation unit is used to calculate the adjustment step of the SIR target value according to the CER value measured and estimated by the CER statistical module, the TPC instruction accuracy target value, and the power control step; The SIR target value calculation unit is used to calculate the SIR target value according to the adjustment step of the SIR target value calculated by the SIR adjustment step calculation unit; The comparison unit is used to compare the SIR target value calculated by the SIR target value calculation unit with the maximum value and the minimum value in the SIR setting value, determine the SIR target value of the outer loop power control module according to the comparison result, and Send to the inner loop power control module. 2. The apparatus of claim 1, wherein The SIR adjustment step calculation unit includes an adder, a divider and a multiplier, wherein: The adder is used to process the CER value measured and estimated by the CER statistical module and the inversion of the target CER value, and input the processed data to the divider; The divider is used to process the data input by the adder and the TPC instruction accuracy target value, and input the processed data to the multiplier; The multiplier is used to process the data input by the divider and the power control step size to obtain the adjustment step size of the SIR target value, and input the adjustment step size of the SIR target value into the SIR target value calculation unit. 3. The device according to claim 1, wherein the SIR target value calculation unit comprises an adder, a time delay device and an SIR target value calculator, wherein: The delayer is used to feed back the adjustment step size of the last SIR target value to the adder; The adder is used to add the SIR adjustment step input by the SIR adjustment step calculation unit and the adjustment step of the last SIR target value fed back by the delayer, and input the processed data to the SIR target value calculator; The SIR target value calculator calculates the current SIR target value according to the adjustment step size of the SIR target value processed by the adder, and inputs it into the comparison unit. 4. The device according to claim 1, wherein the comparison unit comprises a first comparator and a second comparator, wherein: The first comparator is used to compare the SIR target value input by the SIR target value calculation unit with the maximum value in the SIR set value, if the SIR target value input by the SIR target value calculation unit is greater than the SIR set value The maximum value in the SIR setting value is input to the inner loop power control module as the SIR target value of the outer loop power control, if the SIR target value input by the SIR target value calculation unit is less than the SIR setting value In the maximum value, the SIR target value input by the SIR target value calculation unit is input to the second comparator; The second comparator is used to compare the SIR target value input by the SIR target value calculation unit with the minimum value of the SIR set value, if the SIR target value input by the SIR target value calculation unit is greater than the SIR set value If the minimum value in the SIR target value calculation unit is input to the inner loop power control module as the SIR target value of the outer loop power control, if the SIR target value input by the SIR target value calculation unit is less than the SIR setting value, then the minimum value in the SIR setting value is input to the inner loop power control module as the SIR target value of the outer loop power control. 5. Apparatus as claimed in claim 1, 2, 3 or 4, characterized in that, The inner loop power control module includes N SIR estimating units, SIR merging units and uplink power control instruction generating units, and the N SIR estimating units input the processed data to the SIR merging unit for processing, the The SIR merging unit inputs the processed data to the uplink power control command generation unit. 6. The device according to claim 5, wherein each SIR estimation unit further comprises a first power calculator, a second power calculator, a third power calculator, a first cumulative averager, a second cumulative average adders, adders, SIR calculators and filters, where: The first power calculator processes the common pilot channel CPICH symbol processed by the F-DPCH receiving processing module, and inputs the processing result to the first cumulative averager, and the first cumulative averager The input information is processed and then input to the adder; The second cumulative averager processes the CPICH symbol processed by the F-DPCH receiving processing module, and inputs the processing result to the second power calculator, and the second power calculator processes the input information After input to the adder; The adder reverses the information input by the first accumulative averager and the information input by the second power calculator for processing and then inputs it to the filter for processing, and the filter converts the processed result input to said SIR calculator; The third power calculator processes the F-DPCH symbol processed by the F-DPCH receiving processing module, and inputs the processing result to the SIR calculator; The SIR calculator calculates an SIR estimate based on the received information, and inputs the SIR estimate to the SIR combining unit. 7. The apparatus of claim 5, wherein each SIR estimation unit further comprises a power calculator, an adder, a squarer, an accumulative averager, an SIR calculator, and a filter, wherein: The adder processes the real part and the imaginary part of the CPICH symbol processed by the F-DPCH receiving processing module, and processes the processed result, and inputs the processed result to the squarer for processing, and the squarer processes the processed The result of the process is input to the cumulative averager for processing, the filter performs filtering processing on the processed result of the cumulative averager, and the processed result is input to the SIR calculator; The power calculator processes the F-DPCH symbol processed by the F-DPCH receiving processing module, and inputs the processing result to the SIR calculator; The SIR calculator calculates an SIR estimate based on the received information, and inputs the SIR estimate to the SIR combining unit. 8. The device according to claim 5, wherein the CER statistics module comprises a comparison unit, an initial BER statistics unit and a BER and CER mapping unit, wherein: The comparison unit compares the TPC real part and the TPC imaginary part of the F-DPCH symbol processed by the F-DPCH reception processing module, and inputs the comparison result to the initial BER statistics unit, and the initial BER statistics unit according to The comparison result of the comparison unit and the statistical window length are processed, and the processed result is input to the BER and CER mapping unit for processing, and the BER and CER mapping unit inputs the processed result to the outer loop function control module. 9 . The device according to claim 5 , wherein the F-DPCH receiving processing module comprises N channel processing units, and a symbol combiner connected to each of the N channel processing units. 10. The device according to claim 9, wherein each channel processing unit further comprises a first descrambler, a first despreader, a second descrambler, a second despreader, a channel estimation device and channel compensator, where: The first descrambler and the first despreader process the received single-path signal through CPICH descrambling information and despreading information, and the second descrambler and second despreader use F-DPCH descrambling information Process the received single-path signal with the despreading information. Based on the descrambled and despreaded CPICH symbols, the channel estimator completes channel estimation, and the descrambled and despreaded CPICH symbols, F-DPCH symbols and channel estimation values pass through the channel compensator After processing, output to the symbol combiner. the

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