CN201751855U - Testing device and testing control device of transmission chip - Google Patents

Abstract

The utility model discloses a testing device of a transmission chip, comprising a programmable device used for generating test data sent to a chip to be tested according to the construction of a test case, processing the test data according to the chip to be tested and offering a test report according to a returned result. The utility model also discloses a testing control device of the transmission chip. In the utility model, without relying on a meter, the programmable device can generate the test data according to the construction of the test case; the tested result is transmitted back to the programmable device and then judged to be correct or not by the programmable device, thus realizing the universal test on the chip; and the control on the testing process enables the testing implementation to be fully automatic, thus improving the testing efficiency and lowering the testing cost.

Description

A test device and test control device for transmitting chips

technical field

The utility model relates to testing technology, in particular to a testing device and a testing control device for a transmission chip. the

Background technique

Verification and testing play an important role in chip development and have become an integral part of the development process. At present, the difficulties and problems in chip design, testing and manufacturing are gradually increasing, and some are becoming increasingly acute. With the continuous improvement of the performance and complexity of current chips, various defects that have never appeared before pose new challenges to traditional testing methods, and manufacturers need to formulate new testing strategies; at the same time, due to the continuous decline in the average price of integrated circuit devices, profits Rates are also declining, manufacturers must fully consider the test cost and economics. the

In the prior art, the test signal is generated by specific equipment and instruments, and the verification of the results often depends on the instrument, or is only converted into the signal required by the test chip through the programmable device. This test device has low versatility. One test device corresponds to one instrument and can only test one chip, which increases the test cost and makes the test less flexible. the

Utility model content

The main technical problem to be solved by the utility model is to provide a general testing device for transmission chips;

The technical problem to be solved by the utility model is to provide an automatic test control device. the

In order to solve the above technical problems, the utility model provides a test device for transmission chips, including:

The programmable device is used to generate test data sent to the chip under test according to the test case configuration, and give a test report according to the result of the chip under test processing the test data and returning it. the

The test case includes configuration items of the programmable device, working configuration parameters of the chip to be tested, test function items, and expected output values corresponding to the test function items of the chip to be tested. the

Wherein the programmable device includes FPGA, and the FPGA is used to receive test data and convert the test data according to test cases. the

Wherein the programmable device also includes a processor, configured to configure the FPGA according to the configuration items of the programmable device in the test case; the FPGA is also used to receive the configuration of the processor and perform The working configuration parameters and test function items of the chip under test construct the test data. the

The device also includes a pull-off clock signal unit connected to the chip under test for testing the clock pull-off performance of the chip under test. the

The bias-pull clock signal unit is also used to input a bias-pull clock signal to the chip under test, and the device is also used to test whether the service operation of the chip to be tested is normal through the programmable device, and if it is normal, continue to increase the clock The frequency deviation of the signal until the operation of the chip under test is abnormal. the

The device also includes an adjustable voltage power supply module connected to the chip under test for providing the required voltage to the chip under test, and the programmable device is also used for testing the current corresponding to the voltage , to obtain the power consumption of the chip under test. the

The device is also used for testing the interface capability between the chip under test and the processor. the

The control interface of the processor is docked with the chip to be tested through the FPGA, and the FPGA is also used to construct/convert the interface timing of the processor according to the interface timing of the chip to be tested, and the processor is also used to The registers of the chip under test are read and written repeatedly, and it is verified whether the timing of the interface between the chip under test and the processor is normal. the

In order to solve the above technical problems, the utility model also provides a test control device for transmission chips, which is used to automatically complete the test according to the test case using the above test device;

Read the test case, the test case includes the configuration item of the programmable device, the working configuration parameters of the chip to be tested, the test function item, the output expected value corresponding to the test function item of the chip to be tested;

Configure the programmable device according to the configuration items of the programmable device in the test case;

Issue the working configuration parameters and test function items of the chip to be tested;

Configure the chip to be tested according to the working configuration parameters of the obtained test chip;

Start the test according to the test function item;

Generate test case test report. the

The beneficial effects of the utility model are:

(1) The utility model can construct the test data according to the test case by the programmable device without relying on the instrument, and the test result is sent back to the programmable device to judge the correctness of the result, thereby realizing the universal test of the chip . the

(2) The utility model adopts FPGA, which can further improve the flexibility of testing. the

(3) The utility model realizes the test of the chip performance through the test of the working range of the chip voltage, the power consumption and the offset of the clock, thereby improving the comprehensiveness of the test. the

(4) The control of the test process by the utility model makes the test execution fully automatic, improves the test efficiency, and reduces the test cost. the

(5) The utility model is easy to implement and convenient to expand. the

Description of drawings

Fig. 1 is a schematic structural view of the testing device according to an embodiment of the utility model testing device;

Fig. 2 is the structural representation of the testing device according to another embodiment of the utility model testing device;

Fig. 3 is a schematic structural view of the testing device according to another embodiment of the testing device of the present invention;

Fig. 4 is a schematic structural view of the test device according to another embodiment of the test device of the present invention;

Fig. 5 is the flow chart that carries out performance test based on an embodiment of the utility model test device;

Fig. 6 is a schematic structural view of the testing device according to yet another embodiment of the testing device of the present invention;

Fig. 7 is the flow chart that carries out function test based on another embodiment of the utility model test device;

Fig. 8 is the flow chart that tests based on the utility model testing device;

Fig. 9 is a schematic structural view according to an embodiment of the utility model test control device;

Fig. 10 is a flow chart of testing based on another embodiment of the test control device of the present invention. the

Detailed ways

The utility model will be described in further detail below through specific embodiments in conjunction with the accompanying drawings. the

The utility model takes the improvement of the traditional verification test process as a breakthrough, and by designing a method and device for testing transmission chips in an all-round way, a complete and detailed test plan is formulated, and effective test cases are designed to make it a universal tester for transmission chips. The test environment platform uses the versatility of the test environment platform to ensure the automatic verification and testing of transmission chips in various application environments. the

A kind of specific implementation of the test device of the utility model transmission chip, as shown in Figure 1, comprises programmable equipment 101, is used for generating the test data that sends to the chip to be tested according to the test case structure, according to the chip to be tested to described The test data is processed and returned to give a test report. the

According to an embodiment of the test device of the present invention, the test case includes configuration items of the programmable device, working configuration parameters of the chip to be tested, test function items, and expected output values corresponding to the test function items of the chip to be tested. the

According to an embodiment of the utility model testing device, as shown in Figure 2, programmable device 201 comprises FPGA202 and memory 203; Wherein, FPGA202 is used for receiving test case and constructs described test data; Memory 203 is used for storing large-capacity data . According to an alternative embodiment of the present invention, the programmable device may include other programmable devices. the

According to an embodiment of the utility model testing device, the programmable device also includes a processor 204, which is used to configure the FPGA202 according to the configuration items of the programmable device in the test case; The working configuration parameters and test function items of the chip under test 207 in the test data are constructed. the

According to an embodiment of the utility model testing device, it also includes a pull-off clock signal unit 205 connected to the chip to be tested 207, which is used to input the clock signal of pull-off to the chip to be tested, and the device 200 is also used to pass the programmable device 201 Test whether the operation of the chip under test 207 is normal, and if it is normal, continue to increase the frequency deviation of the clock signal until the operation of the chip under test 207 is not normal. the

According to one embodiment of the utility model testing device, it also includes an adjustable voltage power supply module 206 connected to the chip to be tested 207, which is used to provide the required voltage to the chip to be tested separately, and the programmable device 201 is also used to Corresponding to the measured current, the power consumption of the chip under test is obtained. In this embodiment, the adjustable voltage source 206 can output various adjustable voltages to the chip under test, such as 1V, 1.2V, 1.8V, 2.5V and 3.3V, or any other required voltage value. the

According to an embodiment of the utility model testing device, the control interface of the processor 204 is docked with the chip to be tested 207 by the FPGA202, and the FPGA202 is also used for constructing/converting the timing of the processor according to the interface timing of the chip to be tested 207, processing The device 204 is also used for repeatedly reading and writing the registers of the chip under test 207, and verifying whether the timing of the interface between the chip under test 207 and the processor is normal. the

Fig. 3 shows the module schematic diagram of the test device 300 according to an embodiment of the present utility model, which comprises: the pull-bias clock module 302 required by the chip 311 to be tested, which can realize the pull-bias test of the chip clock; The adjustable power supply module 301 required by the chip 311, which can realize the test of the working range and power consumption of the chip power supply voltage; the clock/reset module 304 required by other chips of the entire device; the power supply 303; 307 required by other chips of the entire device The data signal source that may be used; 307 is managed and driven PC305; FPGA (field programmable logic array) 309; the storage unit 310 that hangs under FPGA309; Multiple processors of the same type or different types adapted to the test chip interface. The FPGA309 is connected to the relevant interface of the chip to be tested 300, and the timing of each interface of the chip to be tested is tested. In addition, the function of the chip to be tested 311 is tested by the FPGA309. the

According to an embodiment of the present invention, the testing device 300 can be used to perform comprehensive testing on the transmission chip, including performance testing. The performance test in this embodiment includes accurately testing the voltage working range and power consumption of the chip to be tested; flexibly testing the clock offset range of the chip to be tested; and accurately testing the interface timing of the chip. the

Fig. 4 shows a block diagram of a test device 400 for performance testing according to an embodiment of the present invention. The precision clock source can be a voltage-controlled constant temperature crystal oscillator, the nominal frequency is 77.76MHZ, and the initial frequency deviation is ±0.1ppm; the clock frequency multiplier/jitter attenuator 404 is SI5326, which can realize any frequency output from 2k-945M; the control is realized through 411, 411 is the processor MPC8321E; in this embodiment, the clock needs to be pulled between 76.76M and 78.76M, and the granularity is 100Hz. In this embodiment, 1V (406), 1.2V (407), 1.8V (408), and 2.5V (409) DC-DC power modules use AXH016A0X3-SRZ//BSM16A-3SXG, the input voltage is 3.0-5.5V, and the output voltage 0.75～3.3V, output current 16A, 3.3V (410) DC-DC power module selection PMM4218TWP//PTH04040WAD, input voltage 2.95～5.5VDC, output voltage 0.8～2.5VDC, output current 60A, power inductor (413-417) Choose DHC-5121-R33R-LF1, rated current 16A. By adjusting the voltage divider resistance of the DC-DC power module, the voltage can be biased. By measuring the current at the power inductor, the power consumption of each voltage of the chip can be accurately obtained. the

Fig. 5 shows the flow chart based on the performance test of testing device 400 according to one embodiment of the present utility model, comprises:

Step 502: Determine the appropriate test case according to the test requirements. The following content needs to be specified in the test case: working configuration parameters of the chip 418 to be tested and possible parameter updates during the test process, supporting data streams, and output data from the chip 418 to be tested. The reference result and the expected value output by the chip 418 to be tested are prepared before implementing the test, and each content is specified in the test case;

Step 504: apply performance test conditions, start performance test;

Step 506: According to the characteristics of the current chip design in the direction of low voltage development, as shown in module 401: 1V, 1.2V, 1.8V, 2.5V, 3.3V cover all the working voltages required for the current transmission chip work, in order to accurately test The voltage working range and power consumption of the chip adopts the way of power supply for the chip under test; in view of the characteristics of high power consumption of the current transmission chip, special attention is paid to the output current index in the selection of the adjustable voltage module, and a compatible design is made on the circuit , both the adjustable voltage module and the regulated power supply can be selected, and each power supply voltage of the chip to be tested is set to a typical value;

Step 508: In order to test the interface capability between the chip to be tested and multiple processors of the same type or different types, the control interface of the processor on the board is connected to the chip to be tested through the FPGA402, and the FPGA402 is connected to the chip to be tested according to the interface timing given by the chip to be tested through the FPGA The internal module 412 constructs/converts the timing, the processor completes repeated reading and writing of the registers of the chip to be tested, and verifies whether the timing of the interface between the chip to be tested and different types of processors is normal;

Step 510: the processor 419 configures the programmable logic array FPGA402, and the FPGA402 completely constructs a data flow according to the test case to the chip to be tested 418, and the chip to be tested 418 performs processing according to the configuration parameters and the input data flow, and the output processing result is sent back to the FPGA402, FPGA402 generates the expected reference result according to the test case, and the verification module compares the returned result with the expected value, and if the result is determined to be correct, go to step 506; otherwise, the chip cannot work normally, go to step 518;

Step 512: Test the current of each power supply voltage at the test power consumption node, so as to accurately obtain the power consumption of each power supply voltage;

Step 514: A voltage-controlled constant temperature crystal oscillator 403 is selected in view of the transmission chip's high requirement on clock accuracy, and the clock bias is realized by the multi-rate clock frequency multiplier/jitter attenuator 404, and the clock bias control module 411 can be used to achieve Realize 2k-945M arbitrary frequency output with an accuracy of 100Hz; Pull the clock signal source to check whether the business is running normally. After running for a period of time, if it is still normal, continue to increase the frequency deviation. In this way, the chip clock frequency can be found. Boundary value of deviation;

Step 516: The clock is set to a typical value, and each power supply is sequentially adjusted to work at a minimum value, a typical value, and a maximum value. Check whether the business is running normally, run for a long time, and check whether the business is running stably within the test time;

Step 518: end. the

This embodiment can accurately test the operating voltage range of the chip and the power consumption of each voltage; it can also accurately test the clock offset to confirm the chip's requirement on the clock offset. the

Fig. 6 shows the block diagram according to the test device 600 of the utility model embodiment, wherein FPGA601 can select the Virtex-5 series XC5VTX240T of Xilinx for use, realize the generation of control signal, the transformation of LocalBus interface timing, the complete structure/transformation of SDH data source , automatic verification of the output results; the chip to be tested is 618, which realizes 20G tributary processing (pointer leakage and tributary overhead processing) and time-division crossover in a single chip, 4-chip stacking realizes 80G capacity, and supports 2.5G bus 1+1 and AU4 Level 2:4 protection, and provide branch 1+1 automatic protection switching function; processor 615 adopts MPC8321E, a cost-effective and highly integrated communication processor newly launched by FREESCALE, to realize FPGA601, the chip under test 618 working parameter configuration, automatic acquisition and generation of test results. Fig. 7 shows the flow chart based on the function test of testing device 600 according to the utility model embodiment, comprises:

Step 702: Determine the appropriate test case according to the test requirement;

Step 704: apply functional test conditions, start functional test;

Step 706: The processor 615 configures the programmable logic array FPGA601, and the data source is completely constructed by the FPGA601, and the data flow is generated according to the test case to the chip 618 to be tested;

Step 708: The processor 615 correctly configures the chip to be tested 618 according to the working parameters specified by the test case;

Step 710: The chip 618 to be tested performs processing according to the configuration parameters and the input data stream, and the output processing result is sent back to FPGA601;

Step 712: The processing result output by the chip to be tested 618 is sent back to FPGA 601, and automatically processed by the verification module inside FPGA 601. The verification module compares the returned result with the expected value, and judges the correctness of the result. the

The FPGA601 can completely construct the test signal, and the result can be verified by the FPGA601, while the existing test device is limited to using an instrument to generate the test signal and verify it. the

Utilize the testing process of the test control device of the transmission chip of the present invention, as shown in Figure 8, including:

Step 802: read the test case, the test case includes the configuration item of the programmable device, the work configuration parameter of the chip to be tested, and the test function item;

Step 804: configure the programmable device according to the configuration items of the programmable device in the test case;

Step 806: Issue the work configuration parameters and test function items of the chip to be tested;

Step 808: Configure the chip to be tested according to the obtained working configuration parameters of the test chip;

Step 810: start the test according to the test function item;

Step 812: Generate a test case test report. the

According to an embodiment of the present invention, 810 further includes: controlling the programmable device to construct a test data flow; monitoring the status of the chip through chip alarm interruption and bit error monitoring; and statistically processing the monitoring status. the

A specific implementation of the test control device of the transmission chip of the utility model is used to automatically complete the test according to the test case; read the test case, and the test case includes configuration items of the programmable device, working configuration parameters of the chip to be tested, Test function items, expected output values corresponding to the test function items of the chip to be tested; configure the programmable device according to the configuration items of the programmable device in the test case; issue the working configuration parameters and test function items of the chip to be tested;

Configure the chip to be tested according to the obtained working configuration parameters of the test chip; start the test according to the test function item; generate a test case test report. the

Figure 9 shows a block diagram of a test control device 900 according to an embodiment of the present invention, and Figure 10 shows a flow chart based on a test control device 900 according to an embodiment of the present invention, which includes:

Step 1002: The test case starts to execute, and the configuration items of the instrument 902 and the test function items and configuration parameters of the chip 914 to be tested are read from the test case configuration file 901. The instrument 902 can be a measuring instrument of the prior art or the aforementioned test device;

Step 1004: The automation cooperative control part 905 calls the instrument driver 903 to configure the instrument setting items according to the instrument configuration items;

Step 1006: The automated cooperative control part 905 sends 907 to the test single board through commands according to the function item to be tested and the configuration parameters;

Step 1008; After the test single board receives the command, obtain the test function item and parameters through the command analysis item 910;

Step 1010: the test function configuration part 912 configures the chip 914 to be tested according to the obtained parameters;

Step 1012: the automatic cooperative control part 905 starts the test;

Step 1014: During the test process, the automated collaborative control part 905 can call the instrument driver 903 to construct various test data streams;

Step 1016: During the test, the test board monitors the state of the chip through the chip alarm interruption, bit error monitoring and statistical processing part 913;

Step 1018: The state of the chip can be reported to the automation system control part 905 of the console through the reporting part 911 of alarm and bit error statistics information;

Step 1020: After the test is completed, the test result report automatic generation part 906 automatically generates a test case execution result report. the

In this way, the comprehensive automation of functional testing can be realized: the automation of constructing source data, the automation of the configuration of the chip under test, the automation of obtaining state information of the chip under test, the automatic obtaining of test results, the automatic generation of test reports, and the automatic switching of test cases. the

The above content is a further detailed description of the utility model in conjunction with specific implementation methods, and it cannot be determined that the specific implementation of the utility model is only limited to these descriptions. For a person of ordinary skill in the technical field to which the utility model belongs, without departing from the concept of the utility model, some simple deduction or substitutions can also be made, which should be regarded as belonging to the protection scope of the utility model. the

Claims (7)

1. A test device for transmission chip, characterized in that, comprising: The programmable device is used to generate test data sent to the chip under test according to the test case configuration, and give a test report according to the result of the chip under test processing the test data and returning it. 2. The apparatus according to claim 1, wherein the programmable device comprises an FPGA, and the FPGA is used to receive test data and convert the test data according to test cases. 3. The apparatus according to claim 2, wherein the programmable device further comprises a processor configured to configure the FPGA according to configuration items of the programmable device in the test case; the FPGA also It is used for receiving the configuration of the processor and constructing the test data according to the working configuration parameters and test function items of the chip under test in the test case. 4. The device according to any one of claims 1 to 3, further comprising a pull-off clock signal unit connected to the chip under test for testing the clock pull-off performance of the chip under test. 5. The device according to any one of claims 1 to 3, further comprising an adjustable voltage power supply module connected to the chip under test for providing the required voltage to the chip under test, the adjustable The programming device is also used to obtain the power consumption of the chip under test according to the measured current corresponding to the voltage. 6. The device according to claim 5, wherein the control interface of the processor is docked with the chip to be tested by the FPGA, and the FPGA is also used for controlling the processor's control interface according to the interface timing of the chip to be tested. The interface timing is constructed/transformed, and the processor is also used to repeatedly read and write the registers of the chip to be tested, and verify whether the timing of the interface between the chip to be tested and the processor is normal. 7. A test control device for transmitting chips, characterized in that, it is used to automatically complete the test according to the test case using the test device according to any one of claims 1 to 6; Read the test case, the test case includes the configuration item of the programmable device, the working configuration parameter of the chip to be tested, the test function item, and the expected output value corresponding to the test function item of the chip to be tested; configuring the programmable device according to the configuration items of the programmable device in the test case; Issue the working configuration parameters and test function items of the chip to be tested; Configuring the chip to be tested according to the obtained working configuration parameters of the test chip; Start the test according to the test function item; Generate test case test report. the

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