CN201708797U - Digital frequency-selecting device for multi-carrier mobile communication relay equipment - Google Patents

Abstract

Digital frequency selection device for multi-carrier mobile communication relay equipment, including frequency mixing subsystem, ADC subsystem, DCA subsystem, microcontroller subsystem, clock subsystem, and digital intermediate frequency processing subsystem; digital intermediate frequency processing subsystem The system adopts field programmable logic array, and includes digital down-conversion unit including DDS unit and filter, which is used for digital mixing and modulation to eliminate the spectrum shift generated during analog-to-digital conversion, and extracts and filters the signal ; The gain control adjustment unit is used to receive the output signal of the digital down-conversion unit, and adjust the gain of the entire bandwidth according to the in-band fluctuation of the relay equipment; the digital up-conversion unit, including a filter and a DDS unit, is used to adjust the The signal is interpolated, filtered, and digitally mixed and modulated to restore the digital intermediate frequency signal; the interface unit is respectively connected with the microcontroller subsystem, the DDS unit, and the gain control adjustment unit.

Description

Digital frequency selection device for multi-carrier mobile communication relay equipment

technical field

The utility model relates to a digital frequency selection device used in a multi-carrier mobile communication system.

Background technique

With the gradual increase in the number of mobile users and the proportion of data services, the number of carriers carried by the mobile communication system has increased sharply. The increase in the number of carriers has caused many intermodulation signals between adjacent carriers. These intermodulation signals will not only cause noise interference to the communication system , reduce the quality of communication, and even cause the communication system to be paralyzed, and the harmonics of the intermodulation signal may become a source of interference for other communications. On the other hand, since users and operators put forward higher and higher requirements on the quality and coverage effect of mobile communication networks, relay devices are widely used. In a multi-carrier communication system, in order to reduce the influence of intermodulation signals, the relay equipment generally adopts the method of channel frequency selection, that is, after receiving the signal, according to the frequency of each channel, let each channel pass through its own bandpass Filters to filter out the noise outside the band of each channel before transmitting the signal.

In the traditional analog signal field, the signal frequency selection of the communication system is generally completed by using the intermediate frequency surface acoustic filter. Since the radio frequency signal is transmitted in the mobile communication system, it is necessary to convert the radio frequency signal to an intermediate frequency for processing when this implementation method is adopted. For narrowband signals in communication systems, such as GSM signals and CDMA2000EVDO signals, the surface acoustic filter used to realize the frequency selection function is large in size, and the peripheral circuits are complex, requiring impedance matching circuits, gain compensation circuits, etc., and each signal The processing channels also require their own mixing units, each of which needs to be controlled independently. In the case of a sharp increase in the number of carriers, such as 8 carriers, 12 carriers or even 16 carriers, the volume of the frequency selection device designed and manufactured based on traditional technology is getting larger and larger, and the complexity of the circuit is doubled, which is very important for troubleshooting and mass production. Very unfavorable.

In recent years, digital signal processing technology has been applied to the relay equipment of the mobile communication system. With the development of semiconductor technology, the price of ASICs continues to drop, and some ASICs originally used in base stations are also used in frequency selection devices of relay equipment. Compared with the traditional analog implementation, this implementation method solves the problem of complex circuit and large volume, but there are problems such as complex configuration of ASICs registers, chip performance restricts device performance improvement, and is not conducive to system expansion.

Utility model content

The main purpose of the utility model is to overcome the shortcomings of the prior art and provide a digital frequency selection device for multi-carrier mobile communication relay equipment.

The utility model adopts the following technical scheme: a digital frequency selection device for multi-carrier mobile communication relay equipment, including a frequency mixing subsystem, an analog-to-digital converter subsystem, a digital-to-analog converter subsystem, a microcontroller subsystem, a clock A subsystem, and a digital intermediate frequency processing subsystem respectively connected to the analog-to-digital converter subsystem, the digital-to-analog converter subsystem, the microcontroller subsystem, and the clock subsystem;

The digital intermediate frequency processing subsystem adopts a field programmable logic array, and includes a digital down-conversion unit, a gain control adjustment unit, a digital up-conversion unit, and an interface unit connected in sequence; the digital down-conversion unit includes a direct digital frequency synthesizer unit for Perform digital frequency mixing and modulation to eliminate the spectrum shift generated during analog-to-digital conversion; and a filter for extracting and filtering the signal; a gain control adjustment unit for receiving the output signal of the digital down-conversion unit, and Adjust the gain of the entire bandwidth according to the in-band fluctuation of the relay equipment; the digital up-conversion unit, including a filter, is used to interpolate and filter the signal; the direct digital frequency synthesizer unit is used for digital mixing , modulation, and restore the digital intermediate frequency signal; the interface unit is respectively connected with the microcontroller subsystem, the direct digital frequency synthesizer unit, and the gain control adjustment unit.

Direct Digital Frequency Synthesizer unit, comprising a Direct Digital Frequency Synthesizer, which processes the corresponding discrete sine/cosine signals generated according to the input frequency word, which is set correspondingly by the microcontroller subsystem according to each channel frequency, and passed through the interface unit obtained from the microcontroller subsystem; and a multiplier for multiplying the output signal of the analog-to-digital converter subsystem/the output signal of the digital down-conversion unit with the discrete sine/cosine signals output by the direct digital frequency synthesizer.

The gain control adjustment unit attenuates/compensates the gain of the entire bandwidth according to the gain adjustment parameter, the adjustment parameter is generated by the microcontroller subsystem according to the in-band fluctuation of the relay device, and is obtained from the microcontroller subsystem through the interface unit .

The gain adjustment parameters include a gain adjustment step size and a gain adjustment range.

The digital down-conversion unit and the digital up-conversion unit adopt a two-stage cascade structure including filters.

The frequency mixing subsystem includes an upper mixer, which is used to convert the high-frequency signal into a radio frequency output signal; a down-mixer, which is used to convert the radio frequency signal into a high-frequency signal; a compensation gain amplifier, which is used to compensate the frequency generated during mixing The attenuation of the band-pass filter, which is used to suppress the harmonics of the input analog-to-digital converter subsystem signal; and the local oscillator module, which is used to generate the local oscillator signal of the mixer.

The clock subsystem includes a reference clock module, used to generate a reference clock signal; and a clock distribution module, used to distribute the reference clock to each subsystem.

The analog-to-digital converter subsystem, including the analog-to-digital converter, is used to realize signal analog-to-digital conversion; the power detection and control module is used to perform signal detection on the signal input to the analog-to-digital converter, and control the analog-to-digital conversion according to the input signal power The working status of the device subsystem.

As can be seen from the above description of the utility model, compared with the prior art, the beneficial effects of the utility model are:

The digital frequency selection device for multi-carrier mobile communication relay equipment provided by the utility model adopts software radio technology, and utilizes FPGA to realize digital filtering to complete multi-carrier frequency selection, which is different from the traditional analog implementation mode and the digital implementation mode using ASICs It has the advantages of small size, simple circuit, low power consumption, simple debugging, and convenient mass production; this device has good applicability, scalability and flexibility, and only needs to modify the software program of the device to Transplanted to different mobile communication systems, only need to choose FPGAs with the same package but different capacities to adapt to communication systems with different carrier numbers, without redesigning the PCB board, enabling rapid product design and implementation, and effectively reducing costs ;This device has a gain adjustment function in the digital domain, which can be used to offset and compensate the in-band fluctuations in the communication system to ensure consistent gain within the entire working bandwidth; the design of RF input and RF output can well replace the original analog method frequency selection device.

Description of drawings

Fig. 1 is a functional block diagram of a digital frequency selection device for multi-carrier mobile communication relay equipment.

Fig. 2 is a functional block diagram of the direct digital frequency synthesizer in the digital intermediate frequency processing subsystem.

Fig. 3 is a functional block diagram of the direct digital frequency synthesizer unit and the digital down-conversion unit in the digital intermediate frequency processing subsystem.

Fig. 4 is a functional block diagram of the direct digital frequency synthesizer unit and the digital up-conversion unit in the digital intermediate frequency processing subsystem.

Detailed ways

The utility model will be further described below through specific embodiments.

The utility model provides a digital narrowband frequency selection device for multi-carrier mobile communication relay equipment, which can support digital frequency selection with any number of carriers, and the number of carriers can be increased or decreased arbitrarily according to actual design requirements. The basic principle of this device is: After analog-to-digital conversion of the received radio frequency signal, use the digital intermediate frequency processing system to perform frequency selection processing on the signal in the digital domain, and then restore the signal to the analog domain through digital-to-analog conversion and transmit it.

Referring to Figure 1, the digital frequency selection device includes a frequency mixing subsystem, an analog-to-digital converter (ADC) subsystem, a digital-to-analog converter (DAC) subsystem, a digital intermediate frequency processing subsystem, a microcontroller subsystem, and a clock subsystem. The digital intermediate frequency processing subsystem is respectively connected with the ADC subsystem, the DCA subsystem, the microcontroller subsystem, and the clock subsystem. The microcontroller subsystem is also connected with the ADC subsystem, the digital-to-analog converter subsystem, the clock subsystem, and the frequency mixing subsystem respectively.

The frequency mixing subsystem includes an up-mixer, a down-mixer, a compensation gain amplifier, a band-pass filter, and a local oscillator module. The analog-to-digital converter subsystem includes an analog-to-digital converter and a power detection block. The clock subsystem includes a reference clock module and a clock distribution module CLOCK, the reference clock module is used to generate a reference clock signal, and the clock distribution module CLOCK is used to distribute clocks to the ADC subsystem, DCA subsystem, digital intermediate frequency processing subsystem, microcontroller Subsystems and frequency mixing subsystems provide driving clock signals for each subsystem. The digital intermediate frequency processing subsystem includes a direct digital frequency synthesizer unit, a digital down-conversion unit, a gain control adjustment unit, a digital up-conversion unit, and an interface unit. Among them, the interface unit is used to connect with the microcontroller subsystem. The digital intermediate frequency processing subsystem is realized by Field Programmable Logic Array (FPGA). Using FPGA chip and program control to complete the digital frequency selection function, it can adapt to various communication standards, such as GSM, CDMA1X-EVDO, WCDMA, etc.

The specific composition and working principle of each subsystem of the digital frequency selection device are described in detail below:

First of all, after the system is powered on, the microcontroller subsystem completes the initialization of the local oscillator module, ADC subsystem, DAC subsystem, and clock subsystem of the clock subsystem, and completes the initialization of these ASICs according to the design Assignment of internal registers, so as to complete the setting of the working state of ASICs.

After receiving the input RF signal, the digital frequency selection device uses the down-mixer of the mixing subsystem to transform the RF signal into an intermediate frequency signal. Since there will be a certain attenuation during frequency mixing, a compensation gain amplifier is placed after the down-mixer to compensate for the attenuation during frequency mixing. And because the ADC is wideband during sampling, in order to prevent the harmonics of the input signal from being mixed into the band during the sampling stage, an LC bandpass filter is set at the input of the ADC subsystem to suppress the harmonics of the input signal. The order of the LC bandpass filter is preferably 5th or 7th order, and try to suppress the harmonics of the input signal to the level of the bottom noise of the equipment.

The local oscillator module of the mixing subsystem adopts the local oscillator chip of semiconductor manufacturers such as NS or TI, and the internal oscillator chip includes a PLL and a VCO. The local oscillator chip includes a series of products covering all frequency points from 500MHz to 2.9GHz. For different communication standards, you can choose to use the corresponding chip in the series of products. The up-mixer and down-mixer of the mixing subsystem are broadband devices, which can be applied to various communication systems.

The signal from the mixing subsystem enters the ADC subsystem. The ADC subsystem performs analog-to-digital conversion on the input analog signal and quantizes it into a digital signal. ADC adopts the working mode of band-pass sampling. According to the bandpass sampling theorem, the sampling rate of the ADC subsystem must be twice the signal bandwidth. According to the current domestic signal spectrum planning, the bandwidth of China Mobile's GSM communication system is 24MHz, the bandwidth of China Telecom's CDMA800 communication system is 25MHz, and the bandwidth of China Unicom's WCDMA system is 20MHz. Of course, there are some other communication systems, which are not listed here. The sampling rate of the ADC subsystem generally adopts some typical values such as 61.44MSPS, 92.16MSPS or 122.88MSPS. Of course, it can also use 70MSPS, 100MSPS, etc., which can be changed according to actual needs. The selection of IF frequency is related to the sampling rate. Generally, the selection of IF frequency follows the requirements of formulas (1) and (2). Assume that F0 is the center frequency of the IF signal, Fs is the sampling rate, and B is the bandwidth of the useful signal.

F0+B/2<3Fs/2 ...................(1)

F0-B/2＞Fs ...................(2)

The above requirements can place the useful signals in the positive interval of the Nyquist bandwidth, but in order to ensure the suppression of the local oscillator leakage of the IF part, it is generally required that the two edge points of the useful signal level are away from the positive interval of the Nyquist bandwidth There is still a distance of about 5MHz from the edge.

Since all ADCs have a certain range, for signals exceeding the range, the ADC cannot quantify correctly, which will cause signal distortion. Therefore, the ADC subsystem uses a power detection and control module to detect the input signal. When it is found that the input signal power exceeds the range of the ADC, the module sends an alarm signal and controls the signal output of the ADC to stop until the signal returns to normal. ADC returns to normal working condition.

During the bandpass sampling process of the ADC, the frequency spectrum will be shifted and the image frequency spectrum will be generated. Assuming that the signal frequency is F and the sampling rate is Fs, after band-pass sampling, the frequency of the signal is shifted from F to F-Fs, and an image spectrum is generated at -(F-Fs).

After receiving the signal from the ADC subsystem, the digital intermediate frequency processing subsystem performs the following operations:

Use the direct digital frequency synthesizer (DDS) unit to move the signal frequency to the zero intermediate frequency. Referring to FIG. 3, the DDS unit includes a direct digital frequency synthesizer (DDS) and a multiplier. Wherein, the functional block diagram of DDS is shown in Fig. 2, and DDS includes a phase accumulator and a sine and cosine ROM look-up table, and its working principle is well known, and will not be repeated here. The DDS can control the generated discrete sine/cosine signals according to the input frequency word, and the frequency word is obtained from the microcontroller subsystem by the interface unit in the digital intermediate frequency processing subsystem. The microcontroller subsystem sets up corresponding frequency words according to the frequency of each channel. The DDS unit multiplies the signal sent by the ADC subsystem and the discrete sine/cosine signal output by the DDS, moves the signal to zero intermediate frequency, and generates two IQ signals respectively.

The digital filter is used to extract and filter the IQ two-way signals respectively. Referring to Figure 3, the digital down-conversion subunit adopts a two-stage digital filter structure. The first stage is a 5th-order CIC decimation filter, which is used to perform digital extraction processing on the IQ two-way signal. The extraction multiple depends on different mobile communication The system is determined; the second stage is the FIR filter, which not only suppresses the channel out-of-band signal, but also realizes the shaping and filtering function of the signal. The digital filter is designed without attenuation, and signal attenuation may occur in the filter. When signal attenuation occurs, gain compensation needs to be performed after the digital filter.

The gain adjustment control unit receives the output signal of the digital down-conversion, and is used for canceling and compensating the in-band fluctuation occurring in the communication system. As is known, many passive devices are used in the relay system, such as cavity duplexers, dielectric duplexers, radio frequency acoustic meters and the like. In addition, it is difficult for the gain of the amplifier to be consistent in a relatively wide frequency band, so when the relay system is working, there will be an unbalanced gain within the entire working bandwidth, that is, in-band fluctuation. The amplitude of the in-band fluctuation can be reduced or even eliminated by using the gain adjustment control unit. The specific implementation method is: the microcontroller subsystem generates adjustment parameters according to the actual in-band fluctuation of the relay equipment, and the interface unit of the digital intermediate frequency processing subsystem obtains the adjustment parameters from the microcontroller subsystem and transmits them to the gain adjustment control unit. The adjustment control unit fine-tunes the gain of the entire bandwidth according to the adjustment parameters, that is, properly attenuates a frequency band with a larger gain, and performs gain compensation for a frequency with a smaller gain. The adjustment parameters include the step size of the gain adjustment and the range of the gain adjustment. Generally, the adjustment step size is 0.1dB, and the adjustment range is 2dB.

The digital up-conversion sub-unit realizes the inverse process of digital down-conversion. Since the digital down-conversion extracts the signal, it is necessary to interpolate the signal in order to restore the signal during the digital up-conversion. Referring to Fig. 4, the digital down-conversion sub-unit also adopts a two-stage digital filter structure, including an FIR filter for suppressing channel out-of-band signals and shaping filtering of signals; a CIC interpolation filter for IQ two Digital interpolation processing is performed on the channel signal. The process of interpolation will generate a signal image, which also needs to be mirrored by a filter. Use the DDS unit to mix and modulate to restore the signal. The structure of the DDS unit is the same as that described above, and will not be repeated here. Similarly, the digital filter is also designed with no attenuation, and signal attenuation may occur during filtering. When signal attenuation occurs, gain compensation needs to be performed after the digital filter.

After the digital up-conversion is completed, the digital signal is sent to the DAC subsystem to complete the digital-to-analog conversion, and then the high-frequency analog signal is converted into a radio frequency signal by the up-mixer of the mixing subsystem. During digital-to-analog conversion, the code rate of the discrete signal is usually required to be more than twice the conversion frequency, so a DAC with an interpolation function should be selected to ensure that the code rate of the discrete signal meets the requirements. In addition, the DAC has an optional quadrature modulation function. If the DAC uses the quadrature modulation function, its output is a single-ended signal, and the corresponding up-mixing frequency should choose a single-end conversion ASIC; if the DAC does not use the quadrature modulation function, Then you should choose an up-mixer with quadrature modulation function to complete the modulation and up-mixing operations. Similarly, the output of the DAC subsystem is connected to an LC bandpass filter. If the DAC output is a single-ended signal, then use a single-ended LC filter; if the DAC output is still an IQ signal, then the LC filter needs to be designed as a differential form. . After the output of the up-mixer, in order to compensate the attenuation generated by the previous link, a first-stage gain compensation circuit is also placed.

The above is only a specific embodiment of the present utility model, but the design concept of the present utility model is not limited thereto, any non-substantial modification of the utility model by using this concept should be an act of violating the protection scope of the present utility model .

Claims (8)

1. A digital frequency selection device for multi-carrier mobile communication relay equipment, including a frequency mixing subsystem, an analog-to-digital converter subsystem, a digital-to-analog converter subsystem, a microcontroller subsystem, a clock subsystem, and A digital intermediate frequency processing subsystem connected to an analog-to-digital converter subsystem, a digital-to-analog converter subsystem, a microcontroller subsystem, and a clock subsystem; its features are: The digital intermediate frequency processing subsystem adopts a field programmable logic array, and includes a digital down-conversion unit, a gain control adjustment unit, a digital up-conversion unit, and an interface unit connected in sequence; the digital down-conversion unit includes a direct digital frequency synthesizer unit for Perform digital frequency mixing and modulation to eliminate the spectrum shift generated during analog-to-digital conversion; and a filter for extracting and filtering the signal; a gain control adjustment unit for receiving the output signal of the digital down-conversion unit, and Adjust the gain of the entire bandwidth according to the in-band fluctuation of the relay equipment; the digital up-conversion unit, including a filter, is used to interpolate and filter the signal; the direct digital frequency synthesizer unit is used for digital mixing , modulation, and restore the digital intermediate frequency signal; the interface unit is respectively connected with the microcontroller subsystem, the direct digital frequency synthesizer unit, and the gain control adjustment unit. 2. digital frequency selection device according to claim 1, is characterized in that: direct digital frequency synthesizer unit, comprises direct digital frequency synthesizer, and it processes the corresponding discrete sine/cosine signal that produces according to input frequency word, and described frequency The word is set by the microcontroller subsystem according to the frequency of each channel, and is obtained from the microcontroller subsystem through the interface unit; and the multiplier is used to convert the output signal of the analog-to-digital converter subsystem / the output signal of the digital down-conversion unit Multiply with the discrete sine/cosine output from the direct digital synthesizer. 3. The digital frequency selection device according to claim 1, characterized in that: the gain control adjustment unit attenuates/compensates the gain of the entire bandwidth according to the gain adjustment parameter, and the adjustment parameter is determined by the microcontroller subsystem according to the relay device The in-band fluctuations are generated and acquired from the microcontroller subsystem through the interface unit. 4. The digital frequency selection device according to claim 3, characterized in that: said gain adjustment parameters include gain adjustment step size and gain adjustment range. 5. The digital frequency selection device according to claim 1, characterized in that: the digital down-conversion unit and the digital up-conversion unit adopt a two-stage cascade structure including filters. 6. The digital frequency selection device according to claim 1, characterized in that: the frequency mixing subsystem includes an upper mixer, which is used to transform the high-frequency signal into a radio frequency output signal; a lower mixer, which is used to convert the radio frequency The signal is converted into a high-frequency signal; the compensation gain amplifier is used to compensate the attenuation generated during frequency mixing; the band-pass filter is used to suppress the harmonics of the input analog-to-digital converter subsystem signal; and the local oscillator module is used to generate the mixed frequency. The local oscillator signal of the frequency converter. 7. The digital frequency selection device according to claim 1, wherein the clock subsystem includes a reference clock module for generating a reference clock signal; and a clock distribution module for distributing the reference clock to each subsystem. 8. The digital frequency selection device according to claim 1, characterized in that: the analog-to-digital converter subsystem includes an analog-to-digital converter for realizing signal analog-to-digital conversion; a power detection and control module is used for input analog The signal of the digital converter is detected, and the working state of the analog-to-digital converter subsystem is controlled according to the input signal power.

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