CN201667037U - Current source circuit - Google Patents

Abstract

The utility model discloses a current source circuit, which comprises a first NMOS pipe source electrode, a second NMOS pipe source electrode, a third PMOS pipe source electrode, a fourth PMOS pipe source electrode, and a fifth PMOS pipe source electrode. The current source circuit is characterized in that: the drain electrode of the first NMOS pipe is connected with the grid electrode; the second NMOS pipe source electrode is grounded through resistance, the grid electrode of the second NMOS pipe is connected with the grid electrode of the first NMOS pipe, and the drain electrode of the second NMOS pipe is connected with the drain electrode of the third PMOS pipe; the third PMOS pipe source electrode is connected with a power supply, meanwhile, the grid electrode is connected with the drain electrode, and the drain electrode of the third PMOS pipe is connected with the drain electrode of the fourth PMOS pipe; the fourth PMOS pipe source electrode is connected with the power supply, meanwhile, the drain electrode of the fourth PMOS pipe is connected with the grid drain of the first NMOS pipe, and the grid electrode is connected with the grid electrode of the third PMOS pipe; the fifth PMOS pipe source electrode is connected with the power supply, meanwhile, the grid electrode of the fifth PMOS pipe is connected with the grid electrode of the third PMOS pipe, and the drain electrode is connected with the source electrode of the second NMOS pipe. The current source circuit is additionally provided with the PMOS pipe based on the traditional current source circuit, increases the current adjusting parameter of the current source, can well balance current, and reduces the area of the current source circuit.

Description

A kind of current source circuit

Technical field

The utility model belongs to field of analog integrated circuit, relates in particular to a kind of current source circuit.

Background technology

In traditional possible current source circuit designs, the current expression of current source circuit has only seldom Several Parameters decision electric current, and well balance and chip area are bigger to cause parameter.

As shown in Figure 1, be conventional current source circuit figure, the current source main part comprises 4 metal-oxide-semiconductors and a resistance.

Wherein, metal-oxide-semiconductor M11 is enhancement mode NMOS, source ground, and drain electrode links to each other with grid.Metal-oxide-semiconductor M12 is enhancement mode NMOS pipe, and source electrode passes through resistance R _SLink to each other with ground; Grid connects the grid of metal-oxide-semiconductor M11; Drain electrode connects the drain electrode of metal-oxide-semiconductor M13.Metal-oxide-semiconductor M13 links to each other with drain electrode for enhancement mode PMOS pipe, grid, and source electrode links to each other with power supply; Grid also links to each other with the grid of metal-oxide-semiconductor M14.Metal-oxide-semiconductor M14 is enhancement mode PMOS pipe, and drain electrode links to each other with the grid leak of metal-oxide-semiconductor M11, and grid links to each other with the grid of metal-oxide-semiconductor M13, and source electrode links to each other with power supply.

The reometer of metal-oxide-semiconductor M13 of flowing through is shown:

$I_{\mathrm{out}}=\frac{2}{u_n{c}_{\mathrm{ox}}{(W/L)}_N}\&times;\frac{1}{{{\mathrm{<figure-callout\; id="2"\; label="R\; S"\; filenames="HSA00000052084500011.png"\; state="\{\{state\}\}">R</figure-callout>}}_S}^2}\&times;{(1-\frac{1}{\sqrt{K}})}^2;$

I wherein _OutFor flowing through the electric current of metal-oxide-semiconductor M13; u _nElectron mobility for metal-oxide-semiconductor M11; c _OxBe metal-oxide-semiconductor M11 unit area gate capacitance; (W/L) _NBreadth length ratio for metal-oxide-semiconductor M11; K is the multiple that metal-oxide-semiconductor M12 breadth length ratio is compared with the breadth length ratio of metal-oxide-semiconductor M11; R _SBe resistance.

As can be seen, the current expression of current source circuit has only seldom Several Parameters decision electric current, causes well balance of parameter from above-mentioned formula.For example, when reference current that will be very little, resistance R _SJust bigger, it is many to allow chip area increase, and causes output to reduce.

The utility model content

The utility model can not fine balance and the bigger technical matters of current source circuit chip for solving current source circuit, provide a kind of balance better, chip area less current source circuit.

A kind of current source circuit comprises:

The one NMOS pipe, the 2nd NMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe and resistance;

The source ground of the one NMOS pipe, drain electrode links to each other with grid; The source electrode of the 2nd NMOS pipe links to each other with ground by resistance, and grid links to each other with the grid of a NMOS pipe, and drain electrode links to each other with the drain electrode of the 3rd PMOS; The source electrode of the 3rd PMOS pipe links to each other with power supply, and grid links to each other with drain electrode, and grid also links to each other with the grid of the 4th PMOS pipe; The source electrode of the 4th PMOS pipe links to each other with power supply, and drain electrode links to each other with the grid leak of a NMOS pipe, and grid links to each other with the grid of the 3rd PMOS pipe; The 5th PMOS pipe; The source electrode of the 5th PMOS pipe connects power supply, and grid connects the grid of the 3rd PMOS pipe, and drain electrode connects the source electrode of the 2nd NMOS pipe.

Further preferred, described NMOS pipe, the 2nd NMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe are the enhancement mode metal-oxide-semiconductor.

Further preferred, the breadth length ratio of the 2nd NMOS pipe be a NMOS pipe breadth length ratio K doubly, K gets the round values more than or equal to 1.

Further preferred, the breadth length ratio of the 5th PMOS pipe be the 3rd PMOS pipe breadth length ratio M doubly, M gets the round values more than or equal to 1.

Further preferred, the reometer of this current source is shown:

$I_{\mathrm{out}}=\frac{2}{u_n{c}_{\mathrm{ox}}{(W/L)}_N}\&times;\frac{1}{{(1+M)}^2{{\mathrm{<figure-callout\; id="2"\; label="R\; S"\; filenames="HSA00000052084500011.png"\; state="\{\{state\}\}">R</figure-callout>}}_S}^2}\&times;{(1-\frac{1}{\sqrt{K}})}^2;$

Wherein: I _OutFor flowing through the electric current of the 3rd PMOS pipe; u _nIt is the electron mobility of a NMOS pipe; c _OxIt is NMOS pipe unit area gate capacitance; (W/L) _NIt is the breadth length ratio of a NMOS pipe; K is the multiple of the breadth length ratio of the 2nd a NMOS pipe breadth length ratio and a NMOS pipe; M is the multiple of the breadth length ratio of the 5th PMOS pipe breadth length ratio and the 3rd PMOS pipe; R _SBe resistance.

The utility model current source circuit has added PMOS pipe on conventional current source circuit part, increased the Current Regulation parameter of current source, and well balanced balanced current is regulated, and has also reduced the current source circuit area of chip simultaneously.

Description of drawings

Fig. 1 is the current source circuit figure that prior art provides;

Fig. 2 is the current source circuit figure that the utility model embodiment 1 provides;

Fig. 3 is the current source circuit figure that the utility model embodiment 2 provides.

Embodiment

Clearer for technical matters, technical scheme and beneficial effect that the utility model is solved, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.

As shown in Figure 2, the circuit diagram for the utility model embodiment 1 comprises: a NMOS pipe M21, the 2nd NMOS pipe M22, the 3rd PMOS pipe M23, the 4th PMOS pipe M24, the 5th PMOS pipe M25 and resistance R _S

The source ground of the one NMOS pipe M21, drain electrode links to each other with grid.The source electrode of the 2nd NMOS pipe M22 passes through resistance R _SLink to each other with ground, grid links to each other with the grid of NMOS pipe M21, and drain electrode links to each other with the drain electrode of the 3rd PMOS pipe M23.The source electrode of the 3rd PMOS pipe M23 links to each other with power supply, and grid links to each other with drain electrode, and grid also links to each other with the grid of the 4th PMOS pipe M24.The source electrode of the 4th PMOS pipe M24 links to each other with power supply, and drain electrode links to each other with the grid leak of NMOS pipe M21, and grid links to each other with the grid of the 3rd PMOS pipe M23.The source electrode of the 5th PMOS pipe M25 connects power supply, and grid connects the grid of the 3rd PMOS pipe M23, and drain electrode connects the source electrode of the 2nd NMOS pipe M22.

A described NMOS pipe M21, the 2nd NMOS pipe M22, the 3rd PMOS pipe M23, the 4th PMOS pipe M24, the 5th PMOS pipe M25 is the enhancement mode metal-oxide-semiconductor.

The breadth length ratio of above-mentioned the 2nd NMOS pipe M22 be NMOS pipe M21 breadth length ratio K doubly, K gets the round values more than or equal to 1.

The breadth length ratio of above-mentioned the 5th PMOS pipe M25 be the 3rd PMOS pipe M23 breadth length ratio M doubly, M gets the round values more than or equal to 1.

The reometer of this current source is shown:

$I_{\mathrm{out}}=\frac{2}{u_n{c}_{\mathrm{ox}}{(W/L)}_N}\&times;\frac{1}{{(1+M)}^2{{\mathrm{<figure-callout\; id="2"\; label="R\; S"\; filenames="HSA00000052084500011.png"\; state="\{\{state\}\}">R</figure-callout>}}_S}^2}\&times;{(1-\frac{1}{\sqrt{K}})}^2;---\left(1\right)$

In the formula (1): I _OutFor flowing through the electric current of the 3rd PMOS pipe M23; u _nIt is the electron mobility of NMOS pipe M21; c _OxIt is NMOS pipe M21 unit area gate capacitance; (W/L) _NIt is the breadth length ratio of NMOS pipe M21; K is the multiple of the breadth length ratio of the 2nd NMOS pipe M22 breadth length ratio and NMOS pipe M21; M is the multiple of the breadth length ratio of the 5th PMOS pipe M25 breadth length ratio and the 3rd PMOS pipe; R _SBe resistance.

I _OutDerivation is as follows, obtains following formula according to circuit diagram 2:

$\sqrt{\frac{{2I}_{\mathrm{out}}}{u_n{c}_{\mathrm{ox}}{(W/L)}_N}}+V_{\mathrm{TH}1}=\sqrt{\frac{{2I}_{\mathrm{out}}}{u_n{c}_{\mathrm{ox}}K{(W/L)}_N}}+{\mathrm{<figure-callout\; id="2"\; label="V\; TH"\; filenames="HSA00000052084500011.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{TH}}+I_{\mathrm{out}}(1+M)R_S;---\left(2\right)$

I _OutFor flowing through the electric current of the 3rd PMOS pipe M23; u _nIt is the electron mobility of NMOS pipe M21; c _OxIt is NMOS pipe M21 unit area gate capacitance; (W/L) _NIt is the breadth length ratio of NMOS pipe M21; V _TH1It is the threshold voltage of NMOS pipe M21; K is the multiple of the breadth length ratio of the 2nd NMOS pipe M22 breadth length ratio and NMOS pipe M21; M is the multiple of the breadth length ratio of the 5th PMOS pipe M25 breadth length ratio and the 3rd PMOS pipe; V _TH2It is the threshold voltage of the 2nd NMOS pipe M22; R _SBe resistance.

Ignore bulk effect, can think V _TH1With V _TH2Equate that equation (2) is transformed to:

$\sqrt{\frac{{2I}_{\mathrm{out}}}{u_n{c}_{\mathrm{ox}}{(W/L)}_N}}(1-\frac{1}{\sqrt{K}})=I_{\mathrm{out}}(1+M)R_S;---\left(3\right)$

Through converting, equation (3) is transformed to:

$I_{\mathrm{out}}=\frac{2}{u_n{c}_{\mathrm{ox}}{(W/L)}_N}\&times;\frac{1}{{(1+M)}^2{{\mathrm{<figure-callout\; id="2"\; label="R\; S"\; filenames="HSA00000052084500011.png"\; state="\{\{state\}\}">R</figure-callout>}}_S}^2}\&times;{(1-\frac{1}{\sqrt{K}})}^2;---\left(1\right)$

From formula (1) as can be seen, I _OutSize be subjected to resistance R _S, M and K influence, when the needs electric current I _OutWhen smaller, can regulate resistance R simultaneously _S, M and K size.

Compare with traditional current source, regulate electric current I together with regard to many one degree of freedom M _OutSize, better balanced balanced current I _OutWith resistance R _S, M and K value relation.

When the very little reference current of needs, in order not allow resistance R _SToo big, can strengthen the number that the 5th PMOS manages M25, promptly increase the M value.Make resistance R _SValue diminishes, and can reduce the current source area of chip.

According to the utility model principle, provide an embodiment 2, as shown in Figure 3.

This current source application circuit comprises 5 metal-oxide-semiconductors and three resistance.The annexation of the one NMOS pipe M31, the 2nd NMOS pipe M32, the 3rd PMOS pipe M33, the 4th PMOS pipe M34, the 5th PMOS pipe M35 is identical with embodiment 2, so not tired stating.First resistance R _S1, second resistance R _S2, the 3rd electronics R _S3One end is connected with the source electrode of the 2nd NMOS pipe M32, and an other end connects the first pad Pad1, the second pad Pad2, the 3rd pad Pad3 respectively.

Embodiment 2 needs a plurality of resistance to connect pad in order to solve the current deviation that the resistance process deviation is introduced, and present embodiment is an example with three resistance.Determine certain pad ground connection among the first pad Pad1, the second pad Pad2, the 3rd pad Pad3 during middle the survey, other two pads are unsettled, and resistor area will be bigger.In order to reduce the loss that the resistance chip area brings, can strengthen the M value.Like this, the value of single resistance reduces, and the total value of three resistance has just reduced much, and chip area has just reduced accordingly.

The utility model current source circuit has added PMOS pipe on the current source main part, increased the Current Regulation parameter of current source, and well balanced balanced current is regulated, and can also reduce the current source circuit area of chip.

The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection domain of the present utility model.

Claims (5)

1. a current source circuit comprises: NMOS pipe, the 2nd NMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe and resistance;

The source ground of the one NMOS pipe, drain electrode links to each other with grid;

The source electrode of the 2nd NMOS pipe links to each other with ground by resistance, and grid links to each other with the grid of a NMOS pipe, and drain electrode links to each other with the drain electrode of the 3rd PMOS;

The source electrode of the 3rd PMOS pipe links to each other with power supply, and grid links to each other with drain electrode, and grid also links to each other with the grid of the 4th PMOS pipe;

The source electrode of the 4th PMOS pipe links to each other with power supply, and drain electrode links to each other with the grid leak of a NMOS pipe, and grid links to each other with the grid of the 3rd PMOS pipe;

It is characterized in that: this current source circuit also comprises:

The 5th PMOS pipe; The source electrode of the 5th PMOS pipe connects power supply, and grid connects the grid of the 3rd PMOS pipe, and drain electrode connects the source electrode of the 2nd NMOS pipe.

2. current source circuit as claimed in claim 1 is characterized in that: described NMOS pipe, the 2nd NMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe are the enhancement mode metal-oxide-semiconductor.

3. current source circuit as claimed in claim 1 is characterized in that: the breadth length ratio of the 2nd NMOS pipe be a NMOS pipe breadth length ratio K doubly, K gets the round values more than or equal to 1.

4. current source circuit as claimed in claim 1 is characterized in that: the breadth length ratio of the 5th PMOS pipe be the 3rd PMOS pipe breadth length ratio M doubly, M gets the round values more than or equal to 1.

5. current source circuit as claimed in claim 1 is characterized in that: the reometer of this current source is shown:

$I_{\mathrm{out}}=\frac{2}{u_n{c}_{\mathrm{ox}}{(W/L)}_N}\&times;\frac{1}{{(1+M)}^2{R_S}^2}\&times;{(1-\frac{1}{\sqrt{K}})}^2;$

Wherein: I _OutFor flowing through the electric current of the 3rd PMOS pipe; u _nIt is the electron mobility of a NMOS pipe; c _OxIt is NMOS pipe unit area gate capacitance; (W/L) _NIt is the breadth length ratio of a NMOS pipe; K is the multiple of the breadth length ratio of the 2nd a NMOS pipe breadth length ratio and a NMOS pipe; M is the multiple of the breadth length ratio of the 5th PMOS pipe breadth length ratio and the 3rd PMOS pipe; R _SBe resistance.

Images