CN201608172U - Packaging carrier plate structure - Google Patents
Packaging carrier plate structure Download PDFInfo
- Publication number
- CN201608172U CN201608172U CN2010201150200U CN201020115020U CN201608172U CN 201608172 U CN201608172 U CN 201608172U CN 2010201150200 U CN2010201150200 U CN 2010201150200U CN 201020115020 U CN201020115020 U CN 201020115020U CN 201608172 U CN201608172 U CN 201608172U
- Authority
- CN
- China
- Prior art keywords
- support plate
- layer
- carrier plate
- line layer
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 20
- 238000002161 passivation Methods 0.000 claims abstract description 29
- 239000010410 layer Substances 0.000 claims description 81
- 239000011241 protective layer Substances 0.000 claims description 41
- 239000011159 matrix material Substances 0.000 claims description 14
- 230000005611 electricity Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000007769 metal material Substances 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- -1 comprises pottery Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to a packaging carrier plate structure. The structure comprises a carrier plate base body (1), a carrier plate passivation layer (2), a line layer (3), a carrier plate upper protecting layer (4) and a carrier plate bump (6), wherein the carrier plate passivation layer (2) covers the upper and the lower surfaces of the carrier plate base body (1) as well as the inner wall of a through hole; the line layer (3) covers the upper and the lower surfaces of the carrier plate passivation layer (2) selectively and fills the through hole; and the line layer (3) is exposed from partial areas on the upper and the lower surfaces of the carrier plate passivation layer (2); the carrier plate upper protecting layer (4) selectively covers the upper surface of the line layer (3) and the areas of the upper surface of the circuit layer(3) which is exposed from the surface of carrier plate passivation layer (2), and the partial areas of the upper surface of the line layer(3) is exposed from the carried upper protecting layer (4); and the carrier plate bump (6) is arranged on the lower surface of the line surface (3). The packaging carrier plate structure provided by the utility model has the advantages of good heat and electricity conducting performance and strong applicability.
Description
(1) technical field
The utility model relates to a kind of packaging carrier plate structure.Belong to the chip encapsulation technology field.
(2) background technology
Along with the development of chip encapsulation technology, encapsulating carrier plate is used and come more generally, and is also more and more higher to the requirement of encapsulating carrier plate.Have the strong encapsulating carrier plate of good conductive heat conductivility, applicability and have the favor that technology is simple, production cost is low corresponding implementation method more and more is subjected to the semiconductor packages industry.
Traditional encapsulating carrier plate is not directly to be arranged at the support plate top and bottom or is not directly to connect by through hole owing to line layer, often do not have and improve electric current uniformity, effectively loose heat, requirement that applicability is strong, perhaps can not take into account the requirement of above three aspects, cause current chip performance and design application problem.The implementation method of simultaneously traditional encapsulating carrier plate need be used multiple work steps such as lamination, etching, rubbing down usually, has increased the complexity and the production cost of whole technology.
(3) summary of the invention
The purpose of this utility model is to overcome the deficiency of said chip encapsulating carrier plate and its implementation, provide a kind of and have good conductive heat conductivility, packaging carrier plate structure that applicability is strong, and realize this packaging carrier plate structure have technology simply, implementation method cheaply.
The purpose of this utility model is achieved in that a kind of packaging carrier plate structure, comprises protective layer and support plate projection on support plate matrix, support plate passivation layer, line layer, the support plate, and described support plate passivation layer is covered in support plate matrix upper and lower surface and through hole inwall; Described line layer optionally is covered in support plate passivation layer upper and lower surface and is filled in the described through hole, and support plate passivation layer upper and lower surface regional area exposes line layer; Protective layer optionally is covered in the zone that line layer upper surface and support plate passivation layer surface are exposed the line layer upper surface on the described support plate, and line layer upper surface regional area exposes protective layer on the support plate; Described support plate projection is arranged at the line layer lower surface.
The utility model packaging carrier plate structure can also be coated with the support plate lower protective layer, and line layer lower surface regional area expose described support plate lower protective layer in the zone that described line layer lower surface and support plate passivation layer surface are exposed the line layer lower surface; Described support plate projection is arranged at the zone that the line layer lower surface exposes the support plate lower protective layer.
The beneficial effects of the utility model are:
The line layer of the packaging carrier plate structure that 1, the utility model proposes by through hole through encapsulating carrier plate matrix upper and lower surface, make this packaging carrier plate structure can improve the electric current uniformity, reduce the local current problems of too that the electric current plug manufactures, thereby improved big current carrying capacity; Simultaneously by through the line layer of encapsulating carrier plate upper and lower surface, the heat that produces in the time of can be with chip operation looses, thereby has increased heat-sinking capability.
The line layer through encapsulating carrier plate matrix upper and lower surface of the packaging carrier plate structure that 2, the utility model proposes can redistribute chip input and output end position, and input/output terminal spacing on the chip can be amplified or dwindles, multiple or a plurality of chips can also be arranged on the encapsulating carrier plate simultaneously simultaneously, so just use the condition of having created for whole encapsulation flexible design.
The realization of the packaging carrier plate structure that 3, the utility model proposes mainly is processes such as recycling deposition or growth, photoetching, etching, has reduced whole process complexity, and condition is provided for reducing the cost.
(4) description of drawings
Fig. 1 is the utility model packaging carrier plate structure (the support plate lower protective layer exists under the situation, and the support plate projection is arranged at the zone that the line layer lower surface exposes the support plate lower protective layer) tangent plane schematic diagram.
Fig. 2 is the utility model packaging carrier plate structure (the support plate lower protective layer does not exist under the situation, and the support plate projection is arranged at the line layer lower surface) tangent plane schematic diagram.
Fig. 3 for flip-chip in encapsulating carrier plate (the support plate lower protective layer exists under the situation, and the support plate projection is arranged at the line layer lower surface, chip expose the zone of protective layer is connected on the support plate) tangent plane schematic diagram by chip lug and line layer upper surface.
Fig. 4 for flip-chip in encapsulating carrier plate (the support plate lower protective layer does not exist under the situation, and the support plate projection is arranged at the line layer lower surface, chip expose the zone of protective layer is connected on the support plate) tangent plane schematic diagram by chip lug and line layer upper surface.
Among the figure: protective layer 4, support plate lower protective layer 5, support plate projection 6, chip 7, chip lug 8 on support plate matrix 1, support plate passivation layer 2, line layer 3, the support plate.
(5) embodiment
Referring to Fig. 1, Fig. 1 is the utility model packaging carrier plate structure (the support plate lower protective layer exists under the situation, and the support plate projection is arranged at the zone that the line layer lower surface exposes the support plate lower protective layer) tangent plane schematic diagram.As seen from Figure 1, the utility model packaging carrier plate structure, comprise protective layer 4, support plate lower protective layer 5 and support plate projection 6 on support plate matrix 1, support plate passivation layer 2, line layer 3, the support plate, described support plate passivation layer 2 is covered in support plate matrix 1 upper and lower surface and through hole inwall; Described line layer 3 optionally is covered in support plate passivation layer 2 upper and lower surfaces and is filled in the described through hole, and support plate passivation layer 2 upper and lower surface regional areas expose line layer 3; Protective layer 4 optionally is covered in the zone that line layer 3 upper surfaces are exposed on line layer 3 upper surfaces and support plate passivation layer 2 surfaces on the described support plate, and line layer 3 upper surface regional areas expose protective layer 4 on the support plate; Described support plate lower protective layer 5 is covered in the zone that line layer 3 lower surfaces are exposed on line layer 3 lower surfaces and support plate passivation layer 2 surfaces, and line layer 3 lower surface regional areas expose support plate lower protective layer 5; Described support plate projection 6 is arranged at the zone that line layer 3 lower surfaces expose support plate lower protective layer 5, as Fig. 1 and Fig. 3, does not have at described support plate lower protective layer 5 perhaps that support plate projection 6 is arranged at line layer 3 lower surfaces under the situation, as Fig. 2 and Fig. 4.
Fig. 3 is that flip-chip is in encapsulating carrier plate tangent plane schematic diagram.Among Fig. 3, exist under the situation at the support plate lower protective layer, the support plate projection is arranged at the line layer lower surface, and chip 7 exposes by chip lug 8 and line layer upper surface that the zone of protective layer is connected on the support plate.
Fig. 4 is that flip-chip is in another tangent plane schematic diagram of encapsulating carrier plate.Among Fig. 4, do not exist under the situation at the support plate lower protective layer, the support plate projection is arranged at the line layer lower surface, and chip 7 exposes by chip lug 8 and line layer upper surface that the zone of protective layer is connected on the support plate.
The support plate matrix that described support plate matrix 1 is coherent perforation, and the through hole shape is unrestricted.
Described support plate matrix 1 material is an Inorganic Non-metallic Materials, comprises pottery, glass or silicon materials etc.
Described support plate passivation layer 2 can be Inorganic Non-metallic Materials or the macromolecular material with support plate matrix 1 excellent bonding performance and good insulation preformance, as silicon dioxide, silicon nitride, polyimides or benzocyclobutene etc.
Described line layer 3 materials are electric conducting materials, as metal or metal alloy or conductivity ceramics or conductive carbon material.
Inorganic Non-metallic Materials or macromolecular material that described support plate lower protective layer 5 can be a good insulation preformance are as silicon dioxide, silicon nitride, polyimides or benzocyclobutene etc.
Described support plate projection 6 materials are metal material or metal alloy compositions.
The implementation of described packaging carrier plate structure is:
1) by the method for deposition or growth, forms the support plate passivation layer in support plate matrix upper and lower surface and through hole inwall;
2) by deposition or growth,, in support plate passivation layer upper and lower surface and described through hole, form line layer in conjunction with photoetching and etching method;
3) method by photoetching optionally forms protective layer on the support plate in the zone that line layer upper surface and support plate passivation layer surface are exposed the line layer upper surface;
4) method by photoetching optionally forms the support plate lower protective layer in the zone that line layer lower surface and support plate passivation layer surface are exposed the line layer lower surface; Perhaps be arranged at the line layer lower surface and not occurrence positions skew and flowing out under the join domain prerequisite at the support plate projection, the support plate lower protective layer can not exist.
5) by printing solder or electroplate scolder or plant and put soldered ball, and the method that refluxes, the zone of exposing the support plate lower protective layer at the line layer lower surface forms the support plate projection.
Claims (2)
1. packaging carrier plate structure, comprise protective layer (4) and support plate projection (6) on support plate matrix (1), support plate passivation layer (2), line layer (3), the support plate, it is characterized in that: described support plate passivation layer (2) is covered in support plate matrix (1) upper and lower surface and through hole inwall; Described line layer (3) optionally is covered in support plate passivation layer (2) upper and lower surface and is filled in the described through hole, and support plate passivation layer (2) upper and lower surface regional area exposes line layer (3); Protective layer on the described support plate (4) optionally is covered in the zone that line layer (3) upper surface is exposed on line layer (3) upper surface and support plate passivation layer (2) surface, and line layer (3) upper surface regional area exposes protective layer on the support plate (4); Described support plate projection (6) is arranged at line layer (3) lower surface.
2. a kind of packaging carrier plate structure according to claim 1, it is characterized in that: the zone of exposing line layer (3) lower surface on described line layer (3) lower surface and support plate passivation layer (2) surface, be coated with support plate lower protective layer (5), and line layer (3) lower surface regional area exposes described support plate lower protective layer (5); Described support plate projection (6) is arranged at the zone that line layer (3) lower surface exposes support plate lower protective layer (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201150200U CN201608172U (en) | 2010-02-08 | 2010-02-08 | Packaging carrier plate structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201150200U CN201608172U (en) | 2010-02-08 | 2010-02-08 | Packaging carrier plate structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201608172U true CN201608172U (en) | 2010-10-13 |
Family
ID=42952875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010201150200U Expired - Lifetime CN201608172U (en) | 2010-02-08 | 2010-02-08 | Packaging carrier plate structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201608172U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623426A (en) * | 2012-03-31 | 2012-08-01 | 苏州晶方半导体科技股份有限公司 | Semiconductor packaging structure and packaging method thereof |
-
2010
- 2010-02-08 CN CN2010201150200U patent/CN201608172U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623426A (en) * | 2012-03-31 | 2012-08-01 | 苏州晶方半导体科技股份有限公司 | Semiconductor packaging structure and packaging method thereof |
| CN102623426B (en) * | 2012-03-31 | 2015-04-22 | 苏州晶方半导体科技股份有限公司 | Semiconductor packaging method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20101013 |
|
| CX01 | Expiry of patent term |