CN201549510U - Integrated inductance structure - Google Patents

Abstract

The utility model provides an integrated inductance structure, this integrated inductance structure contain a coil, and this coil is including being located an aluminium lamination on the passivation layer, and wherein, inside this aluminium lamination did not extend to this passivation layer, the thickness of this aluminium lamination was not less than 2.0 microns. The utility model provides an integrated inductance structure has higher quality factor Q.

Description

Integrated Inductor Structure

technical field

The utility model relates to semiconductor IC design, in particular to an integrated inductor (integrated inductor) structure.

Background technique

The rapidly growing wireless communication market is increasingly demanding small and inexpensive handheld devices with more functions. A major trend in circuit design is to integrate as many circuits as possible in order to reduce the cost per wafer.

Inductors on semiconductor chips are widely used in complementary metal-oxide-semiconductor (CMOS)-based radio frequency (Radio Frequency, RF) circuits, such as low-noise amplifiers, voltage-controlled oscillators, and power amplifiers. An inductor is a passive electronic component that stores energy in the form of a magnetic field. The inductor can resist changes in the current flowing through the inductor.

An important characteristic of inductors is the quality factor Q, which is related to the performance of RF circuits or other circuits and systems. The quality factor Q of IC (Integrated Circuit) is limited by the parasitic loss of the substrate itself. These losses include the high impedance presented by the metal layers of the inductor. Therefore, in order to achieve a high quality factor Q, the impedance of the inductor should be kept at a minimum. One way to minimize the impedance of an inductor is to increase the thickness of the metal used to make the inductor.

Therefore, the impedance of the integrated inductor structure is reduced due to the thicker uppermost metal layer (eg, the uppermost layer of the damascene copper interconnect structure) of the integrated inductor structure made by the RF baseline method. For those skilled in the art, it is easier to thicken the metal layer on the uppermost metal layer than other metal layers. Taking the 0.13 μm RF baseline approach as an example, it is not uncommon for the uppermost metal layer to have a thickness of 3 μm. However, excessively thick metal layers often result in complex processing and relatively high costs.

Utility model content

In view of this, it is necessary to provide an integrated inductor structure with a higher quality factor Q.

The utility model provides an integrated inductance structure, which includes a coil, and the coil includes an aluminum layer on a passivation layer, wherein the aluminum layer does not extend into the passivation layer, and the thickness of the aluminum layer is not less than 2.0 microns.

The integrated inductance structure provided by the utility model has a higher quality factor Q.

Description of drawings

1 is a schematic top view of an integrated inductance structure 10 with multiple coils according to an embodiment of the present invention;

Fig. 2 is a schematic cross-sectional perspective view along the I-I' line of Fig. 1;

3 is a schematic cross-sectional view of an integrated inductor structure with further improved quality factor Q and reduced substrate coupling according to another embodiment of the present invention.

Detailed ways

Certain terms are used throughout the specification to refer to particular components. Those skilled in the art should understand that manufacturers may use different terms to refer to the same component. This specification does not use the difference in names as a scheme to distinguish components, but uses the difference in functions of components as a criterion for distinguishing. "Includes" and "comprising" mentioned throughout the specification and subsequent claims are open-ended terms, so they should be interpreted as "including but not limited to". In addition, the term "coupled" includes any direct and indirect electrical connection means. Indirect means of electrical connection include connection through other means.

The utility model belongs to the improvement of an integrated inductance structure or a transformer structure, so that it has a better quality factor Q, reduces unnecessary substrate coupling, and can also reduce process costs. On the one hand, the present invention adopts a line-shaped via structure instead of a hole-shaped via structure to electrically connect the upper layer metal with the lower layer metal. Traditionally, many via plugs arranged in the conductive layer of semiconductor devices are used to electrically connect these conductive layers. For the uniformity of the process, the traditional hole-shaped via plugs have a uniform shape And size, therefore, in order to reduce the impedance, need to utilize a group (array) Via plug.

In another aspect of the present invention, a metal layer (for example, aluminum) is used on the passivation layer of the IC chip to form an integrated inductor structure, so that the thickness of the uppermost copper layer of the IC chip can be reduced.

The aluminum layer placed over the passivation layer is typically used to provide a bonding interface on the copper bond pads formed in the uppermost copper layer of the IC chip to prevent oxidation of the underlying copper material .

Embodiments of the utility model will be described in detail below in conjunction with the accompanying drawings. The label “M _n ” in the description and the drawings indicates the uppermost metal layer, such as the copper layer in an IC chip; “M _n-1 ” indicates that the copper layer M _n-1 is only one level lower than the uppermost copper layer M _n layers, and so on; wherein, preferably, n ranges from 4 to 8, but the present invention is not limited thereto. The designation "V" denotes a via plug layer between two adjacent copper layers. For example, V ₅ represents a via plug layer V ₅ interconnecting the metal layer M ₅ with the metal layer M ₆ .

FIG. 1 is a schematic top view of an integrated inductor structure 10 with multi-turn winding according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional perspective view along line I-I' of Fig. 1 according to a preferred embodiment of the present invention. For simplicity, only differential pairs of two adjacent coils 12 are shown in FIG. 2 .

It should be understood that the integrated inductor structure 10 in the embodiment of the present invention adopts an octagonal shape, but the integrated inductor structure 10 may also adopt other suitable shapes, such as a spiral shape. The shape or style of the inductor is not limited thereto. The utility model is also applicable to single-ended inductors.

As shown in FIG. 1 and FIG. 2 , each coil 12 of the integrated inductor structure 10 has a vertical metal stack (metal stack) layer, and the metal stack layer includes in the following order: metal layer M _n-1 , via plug layer V _n−1 , the metal layer M _n , the via plug layer V _n and the aluminum layer 20 (simply labeled as “aluminum” in FIG. 2 ). The metal layer Mn _-1 can be electrically connected to the metal layer _Mn through the via plug layer Vn _-1 , and the metal layer _Mn can be electrically connected to the aluminum layer 20 through the via plug layer _Vn . According to a preferred embodiment of the present invention, the coil 12 of the integrated inductor structure 10 does not include the lower metal layers M ₁ -M _n-2 , so as to reduce the parasitic coupling loss of the substrate 100 . According to another preferred embodiment of the present invention, the coil 12 does not include the lower metal layers M ₁ -M ₂ .

In one embodiment of the present invention, the via plug layers V _n-1 and V _n are both linear structures. In a preferred embodiment, the linear structure via plug layers V _n-1 and V _n have substantially the same pattern as the metal layer M _n-1 , the metal layer M _n and the aluminum layer 20, and the linear structure is over The line widths of the plug layers V _n-1 and V _n are substantially smaller than the line widths of the metal layer M _n-1 or the metal layer M _n . The impedance value of the integrated inductor structure 10 can be reduced by using the via plug layers V _n-1 and V _n in a linear structure.

In this embodiment, the via plug layer with a smaller line width is not a limitation of the present invention. In other embodiments, the line width of the via plug layer may be the same as or greater than the line width of the metal layer. Further, the shape of the aforementioned linear via holes with substantially the same pattern is not a limitation of the present invention. In other embodiments, the pattern of the line-shaped via plug layer may also include multiple segmented line-shaped vias in each coil.

According to a preferred embodiment of the present invention, the metal layer M _n-1 , the via plug layer V _n-1 and the metal layer M _n are formed by a traditional copper damascene method, such as a single damascene structure method (single damascene method). damascene) or dual damascene structure method (dual damascene). For example, the metal layer M _n-1 is formed by a single damascene structure method, and the metal layer M _n and the integral via plug layer V _n-1 are realized by a dual damascene structure method. In this way, the metal layer _Mn and the via plug layer Vn _-1 become a unitary.

As known to those skilled in the art, the copper damascene method provides a solution to form a wire coupled to an entire via plug without dry etching copper. Both single damascene and dual damascene structures can be used to connect devices and/or wires in an IC.

Generally speaking, the dual damascene structure can be divided into trench-first structure, via-first structure, partial-via-first structure and self-aligned (self-aligned) structure. aligned) structure. For example, a traditional dual damascene process is to first etch trenches and via holes on a dielectric layer. The vias and trenches are aligned with a barrier layer such as Ta or TaN, and then filled with copper. A planarization process such as chemical mechanical polishing (CMP) is then used to form damascene metal interconnects.

Multiple insulating layers 102 - 108 and a passivation layer 110 are located on the substrate 100 . According to a preferred embodiment of the present invention, the integrated inductor structure 10 is basically fabricated on the insulating layer 102 between the insulating layer 104 and the substrate 100 . The metal layer M _n−1 is inlaid to the insulating layer 104 . The metal layer M _n and the entire via plug layer V _n−1 are embedded in the insulating layer 108 and the insulating layer 106 respectively.

The insulating layers 102-108 can be made of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low dielectric constant (low-k) material or ultra-low dielectric constant (ultra low-k) material such as organic (SILK) or inorganic (HSQ).

According to a preferred embodiment of the present invention, the via plug layer V _n is metal aluminum, and the via plug layer V _n is combined with the aluminum layer 20 as a whole. That is to say, the via plug layer V _n is integrated with the aluminum layer 20 . Structurally speaking, the via plug layer V _n is embedded into a corresponding via hole (not shown in the figure), the via hole is formed in the passivation layer 110 , and the aluminum layer 20 is patterned on the passivation layer 110 . The via plug layer V _n and the aluminum layer 20 can be formed simultaneously with a conventional re-distribution layer (not shown). Preferably, the thickness h1 of the aluminum layer 20 may range from 1 micron to 1.5 microns, and the thickness h1 may generally be less than 1.5 microns.

The passivation layer 110 may be silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, polymer, and the like. According to this embodiment, the thickness t1 of the passivation layer 110 may be about 0.8-1.2 microns, but the present invention is not limited thereto.

The integrated inductor structure 10 is fully compatible with the standard logic manufacturing process, and since the entire via plug layer V _n is integrated with the aluminum layer 20 , the integrated inductor structure 10 does not contain an excessively thick copper layer.

In other embodiments of the present invention, the impedance of the integrated inductor structure is reduced by using a linear via structure. An integrated inductor structure with a high quality factor Q can be realized by a vertical metal stack, wherein the metal stack has the following order: metal layer M _n-1 , via plug layer V _n-1 and metal layer M _n , or, the metal stack The following sequence is also possible: top copper layer M _n , via plug layer V _n and aluminum layer.

With the continuous development of semiconductor technology, the thickness of each insulating layer of IC is getting thinner and thinner. This results in a reduced distance between the bottom surface of the inductive structure and the main surface of the semiconductor substrate, thus deteriorating the quality factor Q by undesired substrate coupling across the inductance. The thickness of the inter-layer insulating layer of advanced IC is inevitably reduced, which leads to the deterioration of the quality factor Q. To solve this problem, another embodiment of the present invention provides a new integrated inductor structure.

Fig. 3 is a schematic cross-sectional view of an integrated inductor structure with a further improved quality factor Q and a smaller parasitic substrate coupling according to another embodiment of the present invention, wherein the same symbols as those in Figs. 1 and 2 represent the same components, layers or area. As shown in FIG. 3 , the integrated inductor structure is also formed in the inductor region 10 a, and the integrated inductor structure includes multiple coils. For the sake of brevity, FIG. 3 only shows the differential pairs of two adjacent coils 12 . Viewed from above the integrated inductor structure, the form of the integrated inductor structure in this embodiment may be octagonal, spiral or any other suitable shape. An exemplary shape of an integrated inductor structure according to this embodiment is similar to that shown in FIG. 1 .

A copper interconnect structure 202 may be provided outside the inductor region 10a. The copper interconnect structure 202 can be fabricated in any one of the metal layers M ₁ -M _n and any one of the via plugs V ₁ -V _n-1 , and the copper interconnect structure 202 is embedded into the corresponding insulating layers 102 - 108 . According to this embodiment, no copper interconnect structure is formed in the inductor region 10a. The copper interconnect structure 202 can be fabricated by conventional copper damascene methods. The insulating layers 102-108 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low dielectric constant (low-k) material or ultra low dielectric constant (ultra low-k) material such as organic (SILK) or inorganic (HSQ).

According to this embodiment, each of the two adjacent coils 12 in the integrated inductor structure can be made of aluminum layer 20' instead of using copper material. That is, the integrated inductor structure can be defined only by the aluminum layer 20' having a larger thickness h2, wherein the thickness h2 of the aluminum layer 20' is greater than the thickness h1 of the aluminum layer 20. For example, the thickness h2 may be greater than 2.0 microns, for example, 3.0 microns or thicker. Thicker aluminum layer 20' can help reduce the impedance value of the inductor.

In one embodiment, the aluminum layer 20' may be a redistribution layer. Redistribution layers may also contain I/O pads and wire traces. An integrated inductor structure can be formed in an IC device having a substrate and a plurality of metal layers, at least one of which includes copper. It is also possible that no metal layer is formed between the integrated inductor structure and the substrate. At least one of the upper two layers of the plurality of metal layers may comprise copper. The distance between the bottom surface 12a of the integrated inductor structure and the main surface 100a of the substrate 100 is called distance D. Preferably, the distance D is not less than the distance between the bottom surface of the uppermost metal layer and the main surface 100 a of the substrate 100 .

The integrated inductor structure includes a coil 12 including an aluminum layer 20' on a passivation layer 110', wherein the aluminum layer 20' does not extend into the passivation layer 110', and the thickness of the aluminum layer 20' is about Less than 2.0 microns. The integrated inductor structure is formed on the passivation layer 110', and the thickness t2 of the passivation layer 110' is about not less than 0.8 microns. According to this embodiment, the thickness t2 of the passivation layer 110' is greater than the thickness t1 of the passivation layer 110 shown in FIG. 2 . And it is one of the characteristics of the present invention that the passivation layer 110' has a greater thickness. According to this embodiment, the passivation layer 110' may be silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, polyimide, and the like.

By removing copper from the integrated inductive structure and increasing the thickness of the passivation layer 110', the distance D between the bottom surface 12a of the inductive structure and the main surface 100a of the semiconductor substrate 100 becomes larger, thereby reducing parasitic substrate coupling and, moreover, increasing The thickness of the aluminum layer also helps to improve the quality factor Q. According to an embodiment of the present invention, preferably, in order to obtain better quality factor performance, the distance D between the bottom surface 12a of the inductor structure in the advanced IC chip and the main surface 100a of the semiconductor substrate 100 is approximately greater than 3.0 microns. According to another embodiment, the distance D between the bottom surface 12 a of the integrated inductor structure and the main surface 100 a of the substrate 100 may be no greater than 10 micrometers.

Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present utility model, so the protection scope of the present utility model shall prevail as defined in the claims.

Claims (10)

1. An integrated inductance structure, characterized in that the integrated inductance structure comprises a coil, and the coil comprises an aluminum layer positioned above the passivation layer, wherein the aluminum layer does not extend into the passivation layer , the thickness of the aluminum layer is not less than 2.0 microns. 2. The integrated inductor structure according to claim 1, wherein the thickness of the passivation layer is not less than 0.8 microns. 3 . The integrated inductor structure according to claim 1 , wherein the integrated inductor structure is formed in the inductor region, and no copper interconnection structure is formed in the inductor region. 4 . 4. The integrated inductor structure of claim 1, wherein the aluminum layer is a redistribution layer. 5. The integrated inductor structure of claim 1, wherein the coil comprises aluminum. 6. The integrated inductor structure of claim 1, wherein the integrated inductor structure is formed in an integrated circuit device having a substrate and a plurality of metal layers, at least one of the plurality of metal layers comprising copper. 7. The integrated inductor structure of claim 6, wherein none of the plurality of metal layers is formed between the integrated inductor structure and the substrate. 8. The integrated inductance structure according to claim 6, wherein the distance between the bottom surface of the integrated inductance structure and the main surface of the substrate is not less than the bottom surface of the uppermost metal layer in the plurality of metal layers distance from the major surface of the substrate. 9. The integrated inductor structure according to claim 6, wherein the distance between the bottom surface of the integrated inductor structure and the main surface of the substrate is not less than 3 microns. 10. The integrated inductor structure of claim 6, wherein at least one of the upper two layers of the plurality of metal layers is a copper layer.

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