[go: up one dir, main page]

CN201122597Y - Light emitting diode chip packaging structure with thick guide pins - Google Patents

Light emitting diode chip packaging structure with thick guide pins Download PDF

Info

Publication number
CN201122597Y
CN201122597Y CNU2007201285579U CN200720128557U CN201122597Y CN 201122597 Y CN201122597 Y CN 201122597Y CN U2007201285579 U CNU2007201285579 U CN U2007201285579U CN 200720128557 U CN200720128557 U CN 200720128557U CN 201122597 Y CN201122597 Y CN 201122597Y
Authority
CN
China
Prior art keywords
emitting diode
conductive
diode chip
light
packaging structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNU2007201285579U
Other languages
Chinese (zh)
Inventor
汪秉龙
庄峰辉
黄惠燕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harvatek Corp
Original Assignee
Harvatek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harvatek Corp filed Critical Harvatek Corp
Priority to CNU2007201285579U priority Critical patent/CN201122597Y/en
Application granted granted Critical
Publication of CN201122597Y publication Critical patent/CN201122597Y/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

A light emitting diode chip package structure with thick leads, comprising: the LED package comprises a plurality of mutually separated conductive pins, an insulating shell, a plurality of LED chips and a packaging colloid. The insulating shell covers the lower surfaces of the conductive pins to form an ejection groove for exposing the upper surface of each conductive pin, and two sides of the conductive pins extend out of the insulating shell; the plurality of light emitting diode chips are respectively arranged in the ejection groove, and the positive electrode end and the negative electrode end of each light emitting diode chip are respectively and electrically connected with different conductive pins; the packaging colloid is filled in the ejection groove so as to cover the plurality of light emitting diode chips.

Description

具有厚导脚的发光二极管芯片封装结构 Light emitting diode chip packaging structure with thick leads

技术领域 technical field

本实用新型涉及一种发光二极管芯片封装结构,尤指一种具有厚导脚并且不需要弯折导脚的发光二极管芯片封装结构。The utility model relates to a packaging structure of a light-emitting diode chip, in particular to a packaging structure of a light-emitting diode chip which has thick guide pins and does not need to bend the guide pins.

背景技术 Background technique

请参阅图1所示,其为公知直立式发光二极管芯片封装结构的剖面示意图。由图中可知,公知的直立式发光二极管芯片封装结构包括:一绝缘基底1a、一导电架2a、一发光二极管芯片3a及一荧光胶体4a。Please refer to FIG. 1 , which is a schematic cross-sectional view of a conventional vertical LED chip packaging structure. It can be seen from the figure that the known vertical LED chip packaging structure includes: an insulating substrate 1a, a conductive frame 2a, a LED chip 3a and a fluorescent colloid 4a.

其中,该导电架2a具有两个分别沿该绝缘基底1a的两相反侧边弯折两次的导电接脚20a、21a,以使得所述多个导电接脚20a、21a的下端面可与一电路板5a产生电性接触,并且该导电接脚20a、21a分别具有一正电极区域200a及一负电极区域210a。Wherein, the conductive frame 2a has two conductive pins 20a, 21a respectively bent twice along two opposite sides of the insulating base 1a, so that the lower end surfaces of the plurality of conductive pins 20a, 21a can be connected with a The circuit board 5a is electrically contacted, and the conductive pins 20a, 21a respectively have a positive electrode area 200a and a negative electrode area 210a.

再者,该发光二极管芯片3a具有一正电极端300a及一负电极端310a,并且该发光二极管芯片3a直接设置在该导电接脚20a上,以使得该正电极端300a直接与该导电接脚20a的正电极区域200a产生电性接触,而该发光二极管芯片3a的负电极端310a通过一导线6a与该导电接脚21a的负电极区域210a产生电性连接。Furthermore, the LED chip 3a has a positive electrode terminal 300a and a negative electrode terminal 310a, and the LED chip 3a is directly disposed on the conductive pin 20a, so that the positive electrode terminal 300a is directly connected to the conductive pin 20a The positive electrode region 200a of the light-emitting diode chip 3a is electrically connected to the positive electrode region 200a, and the negative electrode terminal 310a of the LED chip 3a is electrically connected to the negative electrode region 210a of the conductive pin 21a through a wire 6a.

最后,该荧光胶体4a覆盖在该发光二极管芯片3a上,以保护该发光二极管芯片3a。藉此,公知的直立式发光二极管芯片封装结构可产生向上投光(如箭头所示)的发光效果。Finally, the fluorescent colloid 4a covers the LED chip 3a to protect the LED chip 3a. In this way, the known vertical LED chip packaging structure can produce a luminous effect of projecting light upward (as indicated by the arrow).

然而,上述直立式发光二极管芯片封装结构仍有下列几项缺点:However, the above vertical light emitting diode chip packaging structure still has the following disadvantages:

1、所述多个导电接脚20a、21a必须经过弯折才能与电路板5a产生接触,因此增加制造工艺的复杂度。1. The plurality of conductive pins 20a, 21a must be bent to make contact with the circuit board 5a, thus increasing the complexity of the manufacturing process.

2、由于所述多个导电接脚20a、21a的厚度太薄,因此散热面积过小,而无法达到高散热的优点。2. Since the plurality of conductive pins 20a, 21a are too thin, the heat dissipation area is too small to achieve the advantage of high heat dissipation.

3、由于所述多个导电接脚20a、21a的厚度太薄,因此无法提高电源的供应量,而使得该发光二极管芯片3a无法产生较高的发光效能。3. Since the plurality of conductive pins 20a, 21a are too thin, the supply of power cannot be increased, so that the LED chip 3a cannot produce high luminous efficacy.

因此,由上可知,目前公知的不管是直立式或侧式的发光二极管芯片封装结构,显然具有不便与缺点存在,而有待加以改善。Therefore, it can be seen from the above that the currently known LED chip packaging structures, whether vertical or side, obviously have inconvenience and disadvantages, and need to be improved.

实用新型内容Utility model content

本实用新型所要解决的技术问题,在于提供一种具有厚导脚的发光二极管芯片封装结构,其制造简单,并具有较好的散热性和较高的发光效能。The technical problem to be solved by the utility model is to provide a light-emitting diode chip packaging structure with thick leads, which is easy to manufacture, and has better heat dissipation and higher luminous efficiency.

为了解决上述技术问题,根据本实用新型的其中一种方案,提供一种具有厚导脚的发光二极管芯片封装结构,其包括:一金属基材;多个彼此分离的导电脚,其自该金属基材延伸;一绝缘壳体,其包覆所述多个导电脚的下表面,以形成一用于曝露出每一个导电脚的上表面的射出凹槽;多个发光二极管芯片,其分别电性连接于所述多个导电脚;以及一封装胶体,其填充于该射出凹槽内,以覆盖所述多个发光二极管芯片。In order to solve the above technical problems, according to one solution of the present utility model, a light-emitting diode chip packaging structure with thick leads is provided, which includes: a metal substrate; The base material is extended; an insulating shell, which covers the lower surface of the plurality of conductive feet, to form an injection groove for exposing the upper surface of each conductive foot; a plurality of light-emitting diode chips, which are respectively electrically Sexually connected to the plurality of conductive pins; and an encapsulant, which is filled in the emitting groove to cover the plurality of LED chips.

因此本实用新型具有下列的优点:Therefore the utility model has the following advantages:

1、本实用新型的厚导脚不需经过弯折,而能直接与电路板产生接触,因此本实用新型能简化制造工艺的复杂度。1. The thick guide pin of the present invention does not need to be bent, but can directly contact the circuit board, so the present invention can simplify the complexity of the manufacturing process.

2、由于采用厚导脚,因此本实用新型可增加散热面积,而达到高散热的优点。2. Due to the use of thick guide feet, the utility model can increase the heat dissipation area and achieve the advantage of high heat dissipation.

3、由于采用厚导脚,因此本实用新型可提高电源的供应量,而使得发光二极管芯片可产生较高的发光效能。3. Due to the use of thick guide pins, the utility model can increase the supply of power supply, so that the LED chip can produce higher luminous efficiency.

为了能更进一步了解本实用新型为达成预定目的所采取的技术、手段及功效,请参阅以下有关本实用新型的详细说明与附图,相信本实用新型的目的、特征与特点当可由此得一深入且具体的了解,然而所附图仅为提供参考与说明用,并非用来对本实用新型加以限制。In order to further understand the technology, means and effects that the utility model adopts to achieve the predetermined purpose, please refer to the following detailed description and accompanying drawings of the utility model, and believe that the purpose, characteristics and characteristics of the utility model should be obtained from this In-depth and specific understanding, however, the accompanying drawings are only for reference and illustration, and are not intended to limit the utility model.

附图说明 Description of drawings

图1为公知的直立式发光二极管芯片封装结构的剖面示意图;1 is a schematic cross-sectional view of a known vertical light-emitting diode chip packaging structure;

图2为本实用新型具有厚导脚的发光二极管芯片封装结构的制造方法的第一实施例的流程图;Fig. 2 is the flow chart of the first embodiment of the manufacturing method of the light emitting diode chip packaging structure with thick guide pins of the present invention;

图3为本实用新型第一实施例的金属基材的立体示意图;Fig. 3 is a three-dimensional schematic diagram of the metal substrate of the first embodiment of the present invention;

图4为本实用新型第一实施例的金属基材的俯视图;Fig. 4 is a top view of the metal base material of the first embodiment of the present invention;

图5为图3的5-5剖视图;Fig. 5 is a 5-5 sectional view of Fig. 3;

图6为本实用新型第一实施例的金属基材与绝缘壳体相结合的立体示意图;Fig. 6 is a three-dimensional schematic diagram of the combination of the metal base material and the insulating casing according to the first embodiment of the present invention;

图7为本实用新型第一实施例的发光二极管芯片电性连接于导电脚的立体示意图;FIG. 7 is a three-dimensional schematic diagram of the light-emitting diode chip electrically connected to the conductive pin according to the first embodiment of the present invention;

图8为本实用新型第一实施例的发光二极管芯片的第一种设置方式的侧视示意图;Fig. 8 is a schematic side view of the first arrangement mode of the light-emitting diode chip in the first embodiment of the present invention;

图9为本实用新型第一实施例的封装胶体填充于射出凹槽内的立体示意图;FIG. 9 is a schematic perspective view of the encapsulant filling the injection groove according to the first embodiment of the present invention;

图10为本实用新型第一实施例的所述多个导电脚被切除后的立体示意图;Fig. 10 is a schematic perspective view of the plurality of conductive feet cut off according to the first embodiment of the present invention;

图11为本实用新型第一实施例的所述多个导电脚被切除后的另一角度立体示意图;Fig. 11 is a schematic perspective view of another angle after the plurality of conductive feet are cut off according to the first embodiment of the present invention;

图12为本实用新型第一实施例的发光二极管芯片的第二种设置方式的侧视示意图;Fig. 12 is a schematic side view of a second arrangement of light emitting diode chips in the first embodiment of the present invention;

图13为本实用新型第一实施例的发光二极管芯片的第三种设置方式的侧视示意图;Fig. 13 is a schematic side view of a third arrangement of light-emitting diode chips according to the first embodiment of the present invention;

图14为本实用新型发光二极管芯片的第四种设置方式的侧视示意图;Fig. 14 is a schematic side view of the fourth arrangement mode of the light emitting diode chip of the present invention;

图15为本实用新型具有厚导脚的发光二极管芯片封装结构的制造方法的第二实施例的流程图;Fig. 15 is a flow chart of the second embodiment of the manufacturing method of the light-emitting diode chip packaging structure with thick guide pins of the present invention;

图16为本实用新型第二实施例的金属基材与绝缘壳体相结合的立体示意图;Fig. 16 is a three-dimensional schematic diagram of the combination of the metal base material and the insulating casing according to the second embodiment of the present invention;

图17为本实用新型具有厚导脚的发光二极管芯片封装结构的制造方法的第三实施例的流程图;17 is a flow chart of the third embodiment of the manufacturing method of the light-emitting diode chip package structure with thick guide pins of the present invention;

图18为本实用新型第三实施例的金属基材与绝缘壳体相结合的立体示意图;Fig. 18 is a three-dimensional schematic diagram of the combination of the metal base material and the insulating casing according to the third embodiment of the present invention;

图19为本实用新型第一实施例的金属基材与绝缘壳体相结合的立体示意图;Fig. 19 is a three-dimensional schematic diagram of the combination of the metal base material and the insulating casing according to the first embodiment of the present invention;

图20为本实用新型第二实施例的金属基材与绝缘壳体相结合的立体示意图;以及Fig. 20 is a schematic perspective view of the combination of the metal base material and the insulating casing according to the second embodiment of the present invention; and

图21为本实用新型第三实施例的金属基材与绝缘壳体相结合的立体示意图。FIG. 21 is a schematic perspective view of the combination of the metal substrate and the insulating casing according to the third embodiment of the present invention.

其中,附图标记说明如下:Wherein, the reference signs are explained as follows:

绝缘基底       1a          导电架        2aInsulation base 1a Conductive frame 2a

导电接脚       20a、21a    电极区域      200aConductive pins 20a, 21a Electrode area 200a

负电极区域     210a        发光二极管芯片3aNegative electrode area 210a Light-emitting diode chip 3a

正电极端       300a        负电极端      310aPositive terminal 300a Negative terminal 310a

荧光胶体       4a          电路板        5aFluorescent colloid 4a circuit board 5a

导线           6a          金属基材      1Conductor 6a Metal Base 1

导电脚         11          凹槽          111Conductive foot 11 groove 111

正极导电部     1100        负极导电部    1101Positive conductive part 1100 Negative conductive part 1101

电镀保护层     110         绝缘壳体      2Electroplating protection layer 110 insulation shell 2

射出凹槽       20          非导电区域    21Exit groove 20 Non-conductive area 21

发光二极管芯片 3           正、负电极端  30、31Light-emitting diode chip 3 Positive and negative electrode terminals 30, 31

导线           4           封装胶体      5Wire 4 4 Encapsulant 5

金属基材       1′         导电脚        11′Metal Base 1′ Conductive Feet 11′

凹槽           111′       绝缘壳体      2′Groove 111′ insulation shell 2′

射出凹槽       20′        非导电区域    21′Exit Groove 20′ Non-conductive Area 21′

发光二极管芯片 3′         正、负电极端  30′、31′Light-emitting diode chip 3' Positive and negative electrode terminals 30', 31'

导线           4′         金属基材      1″Lead wire 4′ metal substrate 1″

导电脚         11″        凹槽          111″Conductive foot 11″ groove 111″

正极导电部     1100″      负极导电部    1101″Positive conductive part 1100″ Negative conductive part 1101″

加强助         12″        绝缘壳体      2″Reinforcement 12″ Insulation shell 2″

射出凹槽       20″        非导电区域    21″Exit groove 20″ Non-conductive area 21″

发光二极管芯片 3″         正、负电极端  30″、31″Light-emitting diode chip 3″ Positive and negative electrode terminals 30″, 31″

锡球           4″Solder ball 4″

具体实施方式 Detailed ways

请参阅图2至图5所示,其分别为本实用新型具有厚导脚的发光二极管芯片封装结构的制造方法的第一实施例的流程图、本实用新型第一实施例的金属基材的立体示意图、本实用新型第一实施例的金属基材的俯视图、以及图3的5-5剖视图。Please refer to Fig. 2 to Fig. 5, which are the flow chart of the first embodiment of the manufacturing method of the LED chip packaging structure with thick guide pins of the present invention and the metal base material of the first embodiment of the present invention respectively. A three-dimensional schematic diagram, a top view of the metal base material of the first embodiment of the present invention, and a 5-5 sectional view of FIG. 3 .

由图2的流程图中可知,本实用新型第一实施例所提供的具有厚导脚的发光二极管芯片封装结构的制造方法,其包括:首先,配合图3所示,提供一金属基材1,其具有多个延伸出且悬空的导电脚11,并且每一个导电脚11的下表面具有凹槽111(步骤S100),其中该凹槽111为一半蚀凹槽(halfetching concave groove)。其中,该金属基材1及所述多个导电脚11藉由蚀刻技术、冲压或任何成形方式成形出来的。再者,通过电镀的方式,该金属基材1及所述多个导电脚11的表面成形一层电镀保护层110。此外,每一个导电脚11的厚度界于0.4~3mm之间,因此每一个导电脚11具有一介于0.4~3mm的厚度。当然,每一个导电脚11的厚度亦可随着使用者的需求,而设计成超过3mm的厚度。It can be seen from the flow chart in FIG. 2 that the manufacturing method of the light-emitting diode chip packaging structure with thick leads provided by the first embodiment of the present invention includes: first, as shown in FIG. 3 , a metal substrate 1 is provided. , which has a plurality of extended and suspended conductive pins 11, and the lower surface of each conductive pin 11 has a groove 111 (step S100), wherein the groove 111 is a halfetching concave groove. Wherein, the metal substrate 1 and the plurality of conductive pins 11 are formed by etching, stamping or any other forming method. Furthermore, by means of electroplating, an electroplating protective layer 110 is formed on the surface of the metal substrate 1 and the plurality of conductive pins 11 . In addition, the thickness of each conductive pin 11 is between 0.4-3 mm, so each conductive pin 11 has a thickness between 0.4-3 mm. Of course, the thickness of each conductive pin 11 can also be designed to exceed 3mm according to the needs of users.

然后,请参阅图6所示,其为本实用新型第一实施例的金属基材与绝缘壳体相结合的立体示意图。由图6可知,该步骤S100之后,通过一绝缘壳体2包覆所述多个导电脚11的下表面,以形成一用于曝露出每一个导电脚11的上表面的射出凹槽20(步骤S102)。其中,该绝缘壳体2填充于所述多个导电脚11之间的非导电区域21。此外,在该步骤S102中,该绝缘壳体2可通过射出成形或任何的成形方式,以包覆所述多个导电脚11的下表面。Then, please refer to FIG. 6 , which is a three-dimensional schematic view of the combination of the metal base material and the insulating casing according to the first embodiment of the present invention. It can be seen from FIG. 6 that after the step S100, the lower surface of the plurality of conductive pins 11 is covered by an insulating shell 2 to form an injection groove 20 for exposing the upper surface of each conductive pin 11 ( Step S102). Wherein, the insulating shell 2 is filled in the non-conductive area 21 between the plurality of conductive pins 11 . In addition, in the step S102 , the insulating shell 2 can cover the lower surface of the plurality of conductive pins 11 by injection molding or any other molding method.

请参阅图7及图8所示,其分别为本实用新型第一实施例的发光二极管芯片电性连接于导电脚的立体示意图、及本实用新型第一实施例的发光二极管芯片的第一种设置方式的侧视示意图。由图7及图8可知,该步骤S102之后,承载多个发光二极管芯片3于该射出凹槽20内,并且每一个发光二极管芯片3的正、负电极端30、31分别电性连接于不同的导电脚11(步骤S104)。Please refer to FIG. 7 and FIG. 8, which are respectively a three-dimensional schematic diagram of the LED chip electrically connected to the conductive pin in the first embodiment of the utility model, and the first type of LED chip in the first embodiment of the utility model. Schematic side view of the setup. It can be seen from FIG. 7 and FIG. 8 that after the step S102, a plurality of light emitting diode chips 3 are placed in the emitting groove 20, and the positive and negative electrode terminals 30, 31 of each light emitting diode chip 3 are respectively electrically connected to different The conductive pin 11 (step S104).

亦即,该发光二极管芯片3的正、负电极端30、31分别设置于每一个发光二极管芯片3的下表面与上表面,并且每一个发光二极管芯片3选择性地设置于相对应的正极导电部1100上,以使得每一个发光二极管芯片3的正电极端30直接电性连接于相对应的正极导电部1100,并且每一个发光二极管芯片3的负电极端31则通过一导线4而电性连接于相对应的负极导电部1101。That is, the positive and negative electrode terminals 30, 31 of the light emitting diode chip 3 are respectively arranged on the lower surface and the upper surface of each light emitting diode chip 3, and each light emitting diode chip 3 is selectively arranged on the corresponding positive electrode conductive part 1100, so that the positive electrode terminal 30 of each light emitting diode chip 3 is directly electrically connected to the corresponding positive electrode conductive portion 1100, and the negative electrode terminal 31 of each light emitting diode chip 3 is electrically connected to the The corresponding negative electrode conductive part 1101 .

紧接着,请参阅图9所示,其为本实用新型第一实施例的封装胶体填充于射出凹槽内的立体示意图。由图9可知,该步骤S104之后,将一封装胶体5填充于该射出凹槽20内,以覆盖所述多个发光二极管芯片3(步骤S106)。其中,该封装胶体5的材质可为环氧树脂或硅胶(silicone)材料。Next, please refer to FIG. 9 , which is a three-dimensional schematic view of the encapsulant filling the injection groove according to the first embodiment of the present invention. As can be seen from FIG. 9 , after the step S104 , an encapsulant 5 is filled in the injection groove 20 to cover the plurality of LED chips 3 (step S106 ). Wherein, the material of the packaging colloid 5 can be epoxy resin or silicone material.

最后,请参阅图10至图11所示,其分别为本实用新型第一实施例的所述多个导电脚被切除后的立体示意图、及本实用新型第一实施例的所述多个导电脚被切除后的另一角度立体示意图。由图10及图11可知,该步骤S106之后,切割所述多个导电脚11,以完成该具有厚导脚的发光二极管芯片封装结构的制作(步骤S108)。其中,每一个导电脚11的两端外露于该绝缘壳体2的两侧,以利后续的焊锡步骤。Finally, please refer to FIG. 10 to FIG. 11 , which are the three-dimensional schematic diagrams of the plurality of conductive legs cut off in the first embodiment of the utility model, and the plurality of conductive pins in the first embodiment of the utility model. A three-dimensional schematic diagram of another angle after the foot is cut off. It can be seen from FIG. 10 and FIG. 11 that after the step S106, the plurality of conductive pins 11 are cut to complete the fabrication of the LED chip packaging structure with thick conductive pins (step S108). Wherein, the two ends of each conductive pin 11 are exposed on both sides of the insulating casing 2, so as to facilitate the subsequent soldering process.

请参阅图12所示,其为本实用新型第一实施例的发光二极管芯片的第二种设置方式的侧视示意图。由图中可知,该发光二极管芯片3的正、负电极端30、31分别设置于每一个发光二极管芯片3的下表面与上表面,并且每一个发光二极管芯片3依序地设置于相对应的正极导电部1100′上,以使得每一个发光二极管芯片3的正电极端30直接电性连接于相对应的正极导电部1100′,并且每一个发光二极管芯片3的负电极端31则通过一导线4而电性连接于相对应的负极导电部1101′。Please refer to FIG. 12 , which is a schematic side view of the second arrangement of the LED chips in the first embodiment of the present invention. It can be seen from the figure that the positive and negative electrode terminals 30, 31 of the light emitting diode chip 3 are respectively arranged on the lower surface and the upper surface of each light emitting diode chip 3, and each light emitting diode chip 3 is sequentially arranged on the corresponding anode conductive part 1100', so that the positive electrode terminal 30 of each light emitting diode chip 3 is directly electrically connected to the corresponding positive electrode conductive part 1100', and the negative electrode terminal 31 of each light emitting diode chip 3 is connected through a wire 4. It is electrically connected to the corresponding negative electrode conductive part 1101'.

请参阅图13所示,其为本实用新型第一实施例的发光二极管芯片的第三种设置方式的侧视示意图。由图中可知,该绝缘壳体2还进一步包括:多个分别成形于每两个导电脚11之间的非导电区域21′。再者,该发光二极管芯片3′的正、负电极端30′、31′分别设置于每一个发光二极管芯片3′的上表面,并且每一个发光二极管芯片3′间隔地设置于每一个非导电区域21′上;藉此,通过打线(wire-bounding)的方式,使得每一个发光二极管芯片3′的正、负电极端30′、31′分别通过两导线4′而电性连接于相邻的正极导电部1100′及负极导电部1101′。Please refer to FIG. 13 , which is a schematic side view of a third arrangement of LED chips in the first embodiment of the present invention. It can be seen from the figure that the insulating casing 2 further includes: a plurality of non-conductive regions 21 ′ respectively formed between every two conductive pins 11 . Furthermore, the positive and negative electrode terminals 30', 31' of the light emitting diode chip 3' are respectively arranged on the upper surface of each light emitting diode chip 3', and each light emitting diode chip 3' is arranged at intervals in each non-conductive area 21'; thereby, through wire-bounding, the positive and negative electrode terminals 30' and 31' of each light-emitting diode chip 3' are electrically connected to the adjacent LED chip 3' through two wires 4' respectively. The positive conductive part 1100' and the negative conductive part 1101'.

请参阅图14所示,其为本实用新型发光二极管芯片的第四种设置方式的侧视示意图。由图中可知,该发光二极管芯片3″的正、负电极端30″、31″分别设置于每一个发光二极管芯片3″的下表面,并且每一个发光二极管芯片3′横跨相对应的非导电区域21″;藉此,通过倒装芯片的方式,使得每一个发光二极管芯片3″的正、负电极端30″、31″分别通过多个相对应的锡球4″而电性连接于相邻的正极导电部1100″及负极导电部1101″。Please refer to FIG. 14 , which is a schematic side view of the fourth arrangement of the light emitting diode chips of the present invention. It can be seen from the figure that the positive and negative electrode terminals 30 ″ and 31 ″ of the light emitting diode chip 3 ″ are respectively arranged on the lower surface of each light emitting diode chip 3 ″, and each light emitting diode chip 3 ′ straddles the corresponding non-conductive region 21"; thereby, through flip-chip, the positive and negative electrode terminals 30", 31" of each light-emitting diode chip 3" are electrically connected to the adjacent The positive electrode conductive part 1100" and the negative electrode conductive part 1101".

请参阅图15及图16所示,其分别为本实用新型具有厚导脚的发光二极管芯片封装结构的制造方法的第二实施例的流程图、及第二实施例的金属基材与绝缘壳体相结合的立体示意图。由图15的流程图中可知,本实用新型第二实施例所提供的具有厚导脚的发光二极管芯片封装结构的制造方法,其包括:首先,配合图16所示,提供一金属基材1′,其具有多个延伸出且两端固定的导电脚11′,并且每一个导电脚11′的下表面具有凹槽111′(步骤S200),其中该凹槽111′为一半蚀凹槽。接着,通过一绝缘壳体2′包覆所述多个导电脚11′的下表面,以形成一用于曝露出每一个导电脚11′的上表面的射出凹槽20′(步骤S202)。并且,该绝缘壳体2′填充于所述多个导电脚11′之间的非导电区域21′。Please refer to Fig. 15 and Fig. 16, which are respectively the flow chart of the second embodiment of the manufacturing method of the light-emitting diode chip packaging structure with thick leads of the present invention, and the metal substrate and the insulating case of the second embodiment A three-dimensional schematic diagram of the combination of bodies. It can be seen from the flow chart in FIG. 15 that the manufacturing method of the light-emitting diode chip packaging structure with thick leads provided by the second embodiment of the present invention includes: first, as shown in FIG. 16 , a metal substrate 1 is provided. ', which has a plurality of extended conductive pins 11' fixed at both ends, and the lower surface of each conductive pin 11' has a groove 111' (step S200), wherein the groove 111' is a half-etched groove. Next, the lower surfaces of the plurality of conductive pins 11' are covered by an insulating casing 2' to form an injection groove 20' for exposing the upper surface of each conductive pin 11' (step S202). Moreover, the insulating shell 2' fills the non-conductive area 21' between the plurality of conductive pins 11'.

接下来,与第一实施例的步骤S104及S108相同,承载多个发光二极管芯片(未图示)于该射出凹槽内,并且每一个发光二极管芯片的正、负电极端分别电性连接于不同的导电脚11′(步骤S204)。然后,将一封装胶体(未图示)填充于该射出凹槽20′内,以覆盖所述多个发光二极管芯片(步骤S206)。最后,切割所述多个导电脚11′,以完成该具有厚导脚的发光二极管芯片封装结构的制作(步骤S208)。Next, same as steps S104 and S108 of the first embodiment, load a plurality of light emitting diode chips (not shown) in the emitting groove, and the positive and negative electrodes of each light emitting diode chip are respectively electrically connected to different The conductive pin 11' (step S204). Then, an encapsulant (not shown) is filled into the emitting groove 20 ′ to cover the plurality of LED chips (step S206 ). Finally, the plurality of conductive pins 11' are cut to complete the fabrication of the LED chip packaging structure with thick conductive pins (step S208).

请参阅图17及图18所示,其分别为本实用新型具有厚导脚的发光二极管芯片封装结构的制造方法的第三实施例的流程图、及第三实施例的金属基材与绝缘壳体相结合的立体示意图。由图17的流程图中可知,本实用新型第三实施例所提供的具有厚导脚的发光二极管芯片封装结构的制造方法,其包括:首先,配合图18所示,提供一金属基材1″,其具有多个延伸出且悬空的导电脚11″及多个延伸出且连结于每二个导电脚11″之间的加强肋12″,并且每一个导电脚11″的下表面具有凹槽111″(步骤S300),其中该凹槽111″为一半蚀凹槽。然后,通过一绝缘壳体2″包覆所述多个导电脚11″的下表面,以形成一用于曝露出每一个导电脚11″的上表面的射出凹槽20″(步骤S302)。并且,该绝缘壳体2″填充于所述多个导电脚11″之间的非导电区域21″。Please refer to Fig. 17 and Fig. 18, which are respectively the flow chart of the third embodiment of the manufacturing method of the light-emitting diode chip packaging structure with thick leads of the present invention, and the metal base material and the insulating shell of the third embodiment A three-dimensional schematic diagram of the combination of bodies. It can be known from the flow chart in FIG. 17 that the manufacturing method of the light-emitting diode chip packaging structure with thick leads provided by the third embodiment of the present invention includes: first, as shown in FIG. 18 , a metal substrate 1 is provided. ", which has a plurality of extended and suspended conductive feet 11" and a plurality of reinforcing ribs 12" extended and connected between every two conductive feet 11", and the lower surface of each conductive foot 11" has a concave Groove 111" (step S300), wherein the groove 111" is a half-etched groove. Then, an insulating shell 2" is used to cover the lower surface of the plurality of conductive pins 11", so as to form a hole for exposing The ejection groove 20" on the upper surface of each conductive pin 11" (step S302). Moreover, the insulating shell 2" fills the non-conductive area 21" between the plurality of conductive pins 11".

接下来,与第二实施例的步骤S204及S206相同,承载多个发光二极管芯片(未图示)于该射出凹槽20″内,并且每一个发光二极管芯片的正、负电极端分别电性连接于不同的导电脚11″(步骤S304);然后,将一封装胶体(未图示)填充于该射出凹槽内,以覆盖所述多个发光二极管芯片(步骤S306)。最后,切割所述多个导电脚11″及所述多个加强肋12″,以完成该具有厚导脚的发光二极管芯片封装结构的制作(步骤S308)。Next, same as steps S204 and S206 of the second embodiment, load a plurality of light emitting diode chips (not shown) in the injection groove 20″, and the positive and negative terminals of each light emitting diode chip are electrically connected respectively different conductive pins 11" (step S304); then, fill an encapsulant (not shown) in the injection groove to cover the plurality of LED chips (step S306). Finally, cutting the plurality of conductive pins 11 ″ and the plurality of reinforcing ribs 12 ″ to complete the fabrication of the LED chip packaging structure with thick conductive pins (step S308 ).

请参阅图19至图21所示,其分别为本实用新型第一、二、三实施例的金属基材与绝缘壳体相结合的立体示意图。由图19可知,多个第一实施例的具有金属基材1与导电脚11的、金属基材1与绝缘壳体2相结合的结构串联成三排;此外,由图20可知,多个第二实施例的具有金属基材1′与导电脚11′的、金属基材1′与绝缘壳体2′相结合的结构串联成三排;并且,由图21可知,多个第三实施例的具有金属基材1″与导电脚11″的、金属基材1″与绝缘壳体2″相结合的结构串联成三排。藉此,上述三种不同实施例的导电脚11、11′、11″与绝缘壳体2、2′、2″的组合可以整片(all-in-one)的方式制造出来。Please refer to FIG. 19 to FIG. 21 , which are three-dimensional schematic diagrams of the combination of the metal substrate and the insulating housing in the first, second, and third embodiments of the present invention, respectively. It can be seen from FIG. 19 that multiple structures of the first embodiment having the metal base material 1 and the conductive pin 11 and combining the metal base material 1 and the insulating housing 2 are connected in series in three rows; in addition, it can be seen from FIG. 20 that multiple In the second embodiment, the metal substrate 1' and the conductive pin 11', and the metal substrate 1' and the insulating shell 2' are connected in series in three rows; and, as can be seen from FIG. 21, multiple third implementations In the example, the metal substrate 1" and the conductive pin 11" are combined with the structure of the metal substrate 1" and the insulating shell 2" to form three rows in series. Thereby, the combination of the conductive feet 11 , 11 ′, 11 ″ and the insulating casing 2 , 2 ′, 2 ″ in the above three different embodiments can be manufactured in an all-in-one manner.

综上所述,本实用新型所提供的具有厚导脚的发光二极管芯片封装结构,具有下列的优点:To sum up, the light-emitting diode chip packaging structure with thick leads provided by the utility model has the following advantages:

1、本实用新型的厚导脚不需经过弯折,而能直接与电路板产生接触,因此本实用新型能简化制造工艺的复杂度。1. The thick guide pin of the present invention does not need to be bent, but can directly contact the circuit board, so the present invention can simplify the complexity of the manufacturing process.

2、由于采用厚导脚,因此本实用新型可增加散热面积,而达到高散热的优点。2. Due to the use of thick guide feet, the utility model can increase the heat dissipation area and achieve the advantage of high heat dissipation.

3、由于采用厚导脚,因此本实用新型可提高电源的供应量,而使得发光二极管芯片可产生较高的发光效能。3. Due to the use of thick guide pins, the utility model can increase the supply of power supply, so that the LED chip can produce higher luminous efficiency.

注意,以上所述,仅为本实用新型最佳之一的具体实施例的详细说明与附图,但本实用新型的特征并不局限于此,并非用以限制本实用新型,本实用新型的所有范围应以下述的权利要求为准,所有符合于本实用新型申请专利范围的精神与其类似变化的实施例,皆应包含于本实用新型的范畴中,任何熟悉该项技术的人员在本实用新型的领域内,可轻易想到的变化或修饰皆可涵盖在以下本申请的专利范围内。Note that the above description is only a detailed description and drawings of one of the best specific embodiments of the utility model, but the features of the utility model are not limited thereto, and are not intended to limit the utility model. All scopes should be based on the following claims, and all embodiments that conform to the spirit of the patent scope of the utility model and its similar changes should be included in the scope of the utility model. In the field of novelty, easily conceivable changes or modifications can all be covered within the scope of the following patents of this application.

Claims (7)

1. 一种具有厚导脚的发光二极管芯片封装结构,其特征在于,包括:1. A light-emitting diode chip packaging structure with thick guide pins, characterized in that it comprises: 一金属基材;a metal substrate; 多个彼此分离的导电脚,其自该金属基材延伸;a plurality of separate conductive feet extending from the metal base; 一绝缘壳体,其包覆所述多个导电脚的下表面,以形成一用于曝露出每一个导电脚的上表面的射出凹槽;An insulating shell, which covers the lower surface of the plurality of conductive feet, to form an injection groove for exposing the upper surface of each conductive foot; 多个发光二极管芯片,其分别电性连接于所述多个导电脚;以及a plurality of light emitting diode chips, which are respectively electrically connected to the plurality of conductive pins; and 一封装胶体,其填充于该射出凹槽内,以覆盖所述多个发光二极管芯片。An encapsulant is filled in the emitting groove to cover the plurality of LED chips. 2. 如权利要求1所述的具有厚导脚的发光二极管芯片封装结构,其特征在于:该金属基材及所述多个导电脚的表面电镀一层电镀保护层。2. The light-emitting diode chip packaging structure with thick leads as claimed in claim 1, characterized in that: the surface of the metal substrate and the plurality of conductive leads is electroplated with an electroplating protection layer. 3. 如权利要求1所述的具有厚导脚的发光二极管芯片封装结构,其特征在于:每一个导电脚的厚度介于0.4~3mm之间。3. The light-emitting diode chip packaging structure with thick leads as claimed in claim 1, wherein the thickness of each conductive lead is between 0.4-3mm. 4. 如权利要求1所述的具有厚导脚的发光二极管芯片封装结构,其特征在于:该绝缘壳体填充于所述多个导电脚之间的非导电区域,并且每一个导电脚的两端外露于该绝缘壳体的两侧。4. The light-emitting diode chip packaging structure with thick leads as claimed in claim 1, characterized in that: the insulating case is filled in the non-conductive area between the plurality of conductive leads, and two of each conductive lead The ends are exposed on both sides of the insulating shell. 5. 如权利要求1所述的具有厚导脚的发光二极管芯片封装结构,其特征在于:该封装胶体为环氧树脂材质的封装胶体或硅胶材质的封装胶体。5. The light-emitting diode chip packaging structure with thick leads as claimed in claim 1, wherein the packaging colloid is a packaging colloid made of epoxy resin or a packaging colloid made of silica gel. 6. 如权利要求1所述的具有厚导脚的发光二极管芯片封装结构,其特征在于:每一个发光二极管芯片具有分别电性连接于不同导电脚的一正极端与一负电极端。6. The light-emitting diode chip packaging structure with thick leads as claimed in claim 1, wherein each light-emitting diode chip has a positive terminal and a negative electrode terminal respectively electrically connected to different conductive leads. 7. 如权利要求1所述的具有厚导脚的发光二极管芯片封装结构,其特征在于:所述多个发光二极管芯片分别设置于该射出凹槽内。7. The LED chip packaging structure with thick leads as claimed in claim 1, wherein the plurality of LED chips are respectively disposed in the emitting groove.
CNU2007201285579U 2007-09-30 2007-09-30 Light emitting diode chip packaging structure with thick guide pins Expired - Fee Related CN201122597Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNU2007201285579U CN201122597Y (en) 2007-09-30 2007-09-30 Light emitting diode chip packaging structure with thick guide pins

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNU2007201285579U CN201122597Y (en) 2007-09-30 2007-09-30 Light emitting diode chip packaging structure with thick guide pins

Publications (1)

Publication Number Publication Date
CN201122597Y true CN201122597Y (en) 2008-09-24

Family

ID=40009837

Family Applications (1)

Application Number Title Priority Date Filing Date
CNU2007201285579U Expired - Fee Related CN201122597Y (en) 2007-09-30 2007-09-30 Light emitting diode chip packaging structure with thick guide pins

Country Status (1)

Country Link
CN (1) CN201122597Y (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101806439A (en) * 2009-02-18 2010-08-18 黄嘉宾 Heat dissipation structure of LED
CN102446909A (en) * 2010-09-30 2012-05-09 展晶科技(深圳)有限公司 Light-emitting diode combination

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101806439A (en) * 2009-02-18 2010-08-18 黄嘉宾 Heat dissipation structure of LED
CN101806439B (en) * 2009-02-18 2013-04-17 黄嘉宾 Heat dissipation structure of LED
CN102446909A (en) * 2010-09-30 2012-05-09 展晶科技(深圳)有限公司 Light-emitting diode combination
CN102446909B (en) * 2010-09-30 2015-03-11 赛恩倍吉科技顾问(深圳)有限公司 Light-emitting diode combination

Similar Documents

Publication Publication Date Title
US7671374B2 (en) LED chip package structure with a plurality of thick guiding pins and a method for manufacturing the same
CN105514249B (en) Light emitting diode package and carrier plate
KR101140961B1 (en) Package substrate for optical element and Manufacturing method thereof
US20090289274A1 (en) Package structure of light emitting diode and method of manufacturing the same
JP2011228671A (en) Package for housing light emitting diode chips and manufacturing method for substrate of the same
US20130099275A1 (en) Led package and method of making the same
JP2012124248A (en) Lead frame substrate for mounting led chip, method for manufacturing the same and led package
TWI509848B (en) Light-emitting diode package structure and manufacturing method thereof
CN103682018B (en) Light-emitting diode and manufacturing method thereof
US9502618B2 (en) LED module
CN201122597Y (en) Light emitting diode chip packaging structure with thick guide pins
WO2007013774A1 (en) Light emitting device package structure, method of manufacturing the light emitting device package structure, and method of manufacturing light emitting device adopting the same
CN212033002U (en) QFN packaging heat conduction bonding pad and QFN packaging structure with same
TW201409763A (en) Light-emitting diode package structure and manufacturing method thereof
TWI531096B (en) Side-emitting type light emitting diode package structure and manufacturing method thereof
TWI337783B (en) Through hole type led chip package structure using ceramic material as a substrate and method of the same
CN100552907C (en) Light emitting diode chip packaging structure with thick guide pins and manufacturing method thereof
TW201448286A (en) Light-emitting diode package structure and manufacturing method thereof
CN101477954A (en) Method and structure for packaging light-emitting diode chip with high-efficiency lateral light-emitting effect
CN101494173B (en) Light-emitting diode chip packaging structure with rough light-emitting surface and packaging method thereof
CN101246878A (en) Light emitting diode chip packaging structure with ceramic as substrate and manufacturing method thereof
CN201112386Y (en) Perforated LED chip packaging structure using ceramic as substrate
CN201087904Y (en) Light-emitting diode chip packaging structure with ceramic as substrate
TWI521745B (en) Light-emitting diode package structure and manufacturing method thereof
CN201122599Y (en) Light emitting diode chip packaging structure with high-efficiency light emitting effect

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080924

Termination date: 20100930