CN201122597Y - Light emitting diode chip packaging structure with thick guide pins - Google Patents
Light emitting diode chip packaging structure with thick guide pins Download PDFInfo
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- CN201122597Y CN201122597Y CNU2007201285579U CN200720128557U CN201122597Y CN 201122597 Y CN201122597 Y CN 201122597Y CN U2007201285579 U CNU2007201285579 U CN U2007201285579U CN 200720128557 U CN200720128557 U CN 200720128557U CN 201122597 Y CN201122597 Y CN 201122597Y
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 36
- 239000000084 colloidal system Substances 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 18
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 239000008393 encapsulating agent Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 239000000741 silica gel Substances 0.000 claims 1
- 229910002027 silica gel Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 16
- 239000000463 material Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 13
- 230000017525 heat dissipation Effects 0.000 description 7
- 238000009413 insulation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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Abstract
Description
技术领域 technical field
本实用新型涉及一种发光二极管芯片封装结构,尤指一种具有厚导脚并且不需要弯折导脚的发光二极管芯片封装结构。The utility model relates to a packaging structure of a light-emitting diode chip, in particular to a packaging structure of a light-emitting diode chip which has thick guide pins and does not need to bend the guide pins.
背景技术 Background technique
请参阅图1所示,其为公知直立式发光二极管芯片封装结构的剖面示意图。由图中可知,公知的直立式发光二极管芯片封装结构包括:一绝缘基底1a、一导电架2a、一发光二极管芯片3a及一荧光胶体4a。Please refer to FIG. 1 , which is a schematic cross-sectional view of a conventional vertical LED chip packaging structure. It can be seen from the figure that the known vertical LED chip packaging structure includes: an insulating substrate 1a, a
其中,该导电架2a具有两个分别沿该绝缘基底1a的两相反侧边弯折两次的导电接脚20a、21a,以使得所述多个导电接脚20a、21a的下端面可与一电路板5a产生电性接触,并且该导电接脚20a、21a分别具有一正电极区域200a及一负电极区域210a。Wherein, the
再者,该发光二极管芯片3a具有一正电极端300a及一负电极端310a,并且该发光二极管芯片3a直接设置在该导电接脚20a上,以使得该正电极端300a直接与该导电接脚20a的正电极区域200a产生电性接触,而该发光二极管芯片3a的负电极端310a通过一导线6a与该导电接脚21a的负电极区域210a产生电性连接。Furthermore, the
最后,该荧光胶体4a覆盖在该发光二极管芯片3a上,以保护该发光二极管芯片3a。藉此,公知的直立式发光二极管芯片封装结构可产生向上投光(如箭头所示)的发光效果。Finally, the
然而,上述直立式发光二极管芯片封装结构仍有下列几项缺点:However, the above vertical light emitting diode chip packaging structure still has the following disadvantages:
1、所述多个导电接脚20a、21a必须经过弯折才能与电路板5a产生接触,因此增加制造工艺的复杂度。1. The plurality of
2、由于所述多个导电接脚20a、21a的厚度太薄,因此散热面积过小,而无法达到高散热的优点。2. Since the plurality of
3、由于所述多个导电接脚20a、21a的厚度太薄,因此无法提高电源的供应量,而使得该发光二极管芯片3a无法产生较高的发光效能。3. Since the plurality of
因此,由上可知,目前公知的不管是直立式或侧式的发光二极管芯片封装结构,显然具有不便与缺点存在,而有待加以改善。Therefore, it can be seen from the above that the currently known LED chip packaging structures, whether vertical or side, obviously have inconvenience and disadvantages, and need to be improved.
实用新型内容Utility model content
本实用新型所要解决的技术问题,在于提供一种具有厚导脚的发光二极管芯片封装结构,其制造简单,并具有较好的散热性和较高的发光效能。The technical problem to be solved by the utility model is to provide a light-emitting diode chip packaging structure with thick leads, which is easy to manufacture, and has better heat dissipation and higher luminous efficiency.
为了解决上述技术问题,根据本实用新型的其中一种方案,提供一种具有厚导脚的发光二极管芯片封装结构,其包括:一金属基材;多个彼此分离的导电脚,其自该金属基材延伸;一绝缘壳体,其包覆所述多个导电脚的下表面,以形成一用于曝露出每一个导电脚的上表面的射出凹槽;多个发光二极管芯片,其分别电性连接于所述多个导电脚;以及一封装胶体,其填充于该射出凹槽内,以覆盖所述多个发光二极管芯片。In order to solve the above technical problems, according to one solution of the present utility model, a light-emitting diode chip packaging structure with thick leads is provided, which includes: a metal substrate; The base material is extended; an insulating shell, which covers the lower surface of the plurality of conductive feet, to form an injection groove for exposing the upper surface of each conductive foot; a plurality of light-emitting diode chips, which are respectively electrically Sexually connected to the plurality of conductive pins; and an encapsulant, which is filled in the emitting groove to cover the plurality of LED chips.
因此本实用新型具有下列的优点:Therefore the utility model has the following advantages:
1、本实用新型的厚导脚不需经过弯折,而能直接与电路板产生接触,因此本实用新型能简化制造工艺的复杂度。1. The thick guide pin of the present invention does not need to be bent, but can directly contact the circuit board, so the present invention can simplify the complexity of the manufacturing process.
2、由于采用厚导脚,因此本实用新型可增加散热面积,而达到高散热的优点。2. Due to the use of thick guide feet, the utility model can increase the heat dissipation area and achieve the advantage of high heat dissipation.
3、由于采用厚导脚,因此本实用新型可提高电源的供应量,而使得发光二极管芯片可产生较高的发光效能。3. Due to the use of thick guide pins, the utility model can increase the supply of power supply, so that the LED chip can produce higher luminous efficiency.
为了能更进一步了解本实用新型为达成预定目的所采取的技术、手段及功效,请参阅以下有关本实用新型的详细说明与附图,相信本实用新型的目的、特征与特点当可由此得一深入且具体的了解,然而所附图仅为提供参考与说明用,并非用来对本实用新型加以限制。In order to further understand the technology, means and effects that the utility model adopts to achieve the predetermined purpose, please refer to the following detailed description and accompanying drawings of the utility model, and believe that the purpose, characteristics and characteristics of the utility model should be obtained from this In-depth and specific understanding, however, the accompanying drawings are only for reference and illustration, and are not intended to limit the utility model.
附图说明 Description of drawings
图1为公知的直立式发光二极管芯片封装结构的剖面示意图;1 is a schematic cross-sectional view of a known vertical light-emitting diode chip packaging structure;
图2为本实用新型具有厚导脚的发光二极管芯片封装结构的制造方法的第一实施例的流程图;Fig. 2 is the flow chart of the first embodiment of the manufacturing method of the light emitting diode chip packaging structure with thick guide pins of the present invention;
图3为本实用新型第一实施例的金属基材的立体示意图;Fig. 3 is a three-dimensional schematic diagram of the metal substrate of the first embodiment of the present invention;
图4为本实用新型第一实施例的金属基材的俯视图;Fig. 4 is a top view of the metal base material of the first embodiment of the present invention;
图5为图3的5-5剖视图;Fig. 5 is a 5-5 sectional view of Fig. 3;
图6为本实用新型第一实施例的金属基材与绝缘壳体相结合的立体示意图;Fig. 6 is a three-dimensional schematic diagram of the combination of the metal base material and the insulating casing according to the first embodiment of the present invention;
图7为本实用新型第一实施例的发光二极管芯片电性连接于导电脚的立体示意图;FIG. 7 is a three-dimensional schematic diagram of the light-emitting diode chip electrically connected to the conductive pin according to the first embodiment of the present invention;
图8为本实用新型第一实施例的发光二极管芯片的第一种设置方式的侧视示意图;Fig. 8 is a schematic side view of the first arrangement mode of the light-emitting diode chip in the first embodiment of the present invention;
图9为本实用新型第一实施例的封装胶体填充于射出凹槽内的立体示意图;FIG. 9 is a schematic perspective view of the encapsulant filling the injection groove according to the first embodiment of the present invention;
图10为本实用新型第一实施例的所述多个导电脚被切除后的立体示意图;Fig. 10 is a schematic perspective view of the plurality of conductive feet cut off according to the first embodiment of the present invention;
图11为本实用新型第一实施例的所述多个导电脚被切除后的另一角度立体示意图;Fig. 11 is a schematic perspective view of another angle after the plurality of conductive feet are cut off according to the first embodiment of the present invention;
图12为本实用新型第一实施例的发光二极管芯片的第二种设置方式的侧视示意图;Fig. 12 is a schematic side view of a second arrangement of light emitting diode chips in the first embodiment of the present invention;
图13为本实用新型第一实施例的发光二极管芯片的第三种设置方式的侧视示意图;Fig. 13 is a schematic side view of a third arrangement of light-emitting diode chips according to the first embodiment of the present invention;
图14为本实用新型发光二极管芯片的第四种设置方式的侧视示意图;Fig. 14 is a schematic side view of the fourth arrangement mode of the light emitting diode chip of the present invention;
图15为本实用新型具有厚导脚的发光二极管芯片封装结构的制造方法的第二实施例的流程图;Fig. 15 is a flow chart of the second embodiment of the manufacturing method of the light-emitting diode chip packaging structure with thick guide pins of the present invention;
图16为本实用新型第二实施例的金属基材与绝缘壳体相结合的立体示意图;Fig. 16 is a three-dimensional schematic diagram of the combination of the metal base material and the insulating casing according to the second embodiment of the present invention;
图17为本实用新型具有厚导脚的发光二极管芯片封装结构的制造方法的第三实施例的流程图;17 is a flow chart of the third embodiment of the manufacturing method of the light-emitting diode chip package structure with thick guide pins of the present invention;
图18为本实用新型第三实施例的金属基材与绝缘壳体相结合的立体示意图;Fig. 18 is a three-dimensional schematic diagram of the combination of the metal base material and the insulating casing according to the third embodiment of the present invention;
图19为本实用新型第一实施例的金属基材与绝缘壳体相结合的立体示意图;Fig. 19 is a three-dimensional schematic diagram of the combination of the metal base material and the insulating casing according to the first embodiment of the present invention;
图20为本实用新型第二实施例的金属基材与绝缘壳体相结合的立体示意图;以及Fig. 20 is a schematic perspective view of the combination of the metal base material and the insulating casing according to the second embodiment of the present invention; and
图21为本实用新型第三实施例的金属基材与绝缘壳体相结合的立体示意图。FIG. 21 is a schematic perspective view of the combination of the metal substrate and the insulating casing according to the third embodiment of the present invention.
其中,附图标记说明如下:Wherein, the reference signs are explained as follows:
绝缘基底 1a 导电架 2aInsulation base 1a
导电接脚 20a、21a 电极区域 200a
负电极区域 210a 发光二极管芯片3a
正电极端 300a 负电极端 310a
荧光胶体 4a 电路板 5a
导线 6a 金属基材 1
导电脚 11 凹槽 111
正极导电部 1100 负极导电部 1101Positive
电镀保护层 110 绝缘壳体 2Electroplating
射出凹槽 20 非导电区域 21
发光二极管芯片 3 正、负电极端 30、31Light-
导线 4 封装胶体 5Wire 4 4 Encapsulant 5
金属基材 1′ 导电脚 11′
凹槽 111′ 绝缘壳体 2′Groove 111′
射出凹槽 20′ 非导电区域 21′
发光二极管芯片 3′ 正、负电极端 30′、31′Light-emitting diode chip 3' Positive and negative electrode terminals 30', 31'
导线 4′ 金属基材 1″Lead wire 4′
导电脚 11″ 凹槽 111″
正极导电部 1100″ 负极导电部 1101″Positive
加强助 12″ 绝缘壳体 2″
射出凹槽 20″ 非导电区域 21″
发光二极管芯片 3″ 正、负电极端 30″、31″Light-emitting
锡球 4″Solder ball 4″
具体实施方式 Detailed ways
请参阅图2至图5所示,其分别为本实用新型具有厚导脚的发光二极管芯片封装结构的制造方法的第一实施例的流程图、本实用新型第一实施例的金属基材的立体示意图、本实用新型第一实施例的金属基材的俯视图、以及图3的5-5剖视图。Please refer to Fig. 2 to Fig. 5, which are the flow chart of the first embodiment of the manufacturing method of the LED chip packaging structure with thick guide pins of the present invention and the metal base material of the first embodiment of the present invention respectively. A three-dimensional schematic diagram, a top view of the metal base material of the first embodiment of the present invention, and a 5-5 sectional view of FIG. 3 .
由图2的流程图中可知,本实用新型第一实施例所提供的具有厚导脚的发光二极管芯片封装结构的制造方法,其包括:首先,配合图3所示,提供一金属基材1,其具有多个延伸出且悬空的导电脚11,并且每一个导电脚11的下表面具有凹槽111(步骤S100),其中该凹槽111为一半蚀凹槽(halfetching concave groove)。其中,该金属基材1及所述多个导电脚11藉由蚀刻技术、冲压或任何成形方式成形出来的。再者,通过电镀的方式,该金属基材1及所述多个导电脚11的表面成形一层电镀保护层110。此外,每一个导电脚11的厚度界于0.4~3mm之间,因此每一个导电脚11具有一介于0.4~3mm的厚度。当然,每一个导电脚11的厚度亦可随着使用者的需求,而设计成超过3mm的厚度。It can be seen from the flow chart in FIG. 2 that the manufacturing method of the light-emitting diode chip packaging structure with thick leads provided by the first embodiment of the present invention includes: first, as shown in FIG. 3 , a
然后,请参阅图6所示,其为本实用新型第一实施例的金属基材与绝缘壳体相结合的立体示意图。由图6可知,该步骤S100之后,通过一绝缘壳体2包覆所述多个导电脚11的下表面,以形成一用于曝露出每一个导电脚11的上表面的射出凹槽20(步骤S102)。其中,该绝缘壳体2填充于所述多个导电脚11之间的非导电区域21。此外,在该步骤S102中,该绝缘壳体2可通过射出成形或任何的成形方式,以包覆所述多个导电脚11的下表面。Then, please refer to FIG. 6 , which is a three-dimensional schematic view of the combination of the metal base material and the insulating casing according to the first embodiment of the present invention. It can be seen from FIG. 6 that after the step S100, the lower surface of the plurality of
请参阅图7及图8所示,其分别为本实用新型第一实施例的发光二极管芯片电性连接于导电脚的立体示意图、及本实用新型第一实施例的发光二极管芯片的第一种设置方式的侧视示意图。由图7及图8可知,该步骤S102之后,承载多个发光二极管芯片3于该射出凹槽20内,并且每一个发光二极管芯片3的正、负电极端30、31分别电性连接于不同的导电脚11(步骤S104)。Please refer to FIG. 7 and FIG. 8, which are respectively a three-dimensional schematic diagram of the LED chip electrically connected to the conductive pin in the first embodiment of the utility model, and the first type of LED chip in the first embodiment of the utility model. Schematic side view of the setup. It can be seen from FIG. 7 and FIG. 8 that after the step S102, a plurality of light emitting
亦即,该发光二极管芯片3的正、负电极端30、31分别设置于每一个发光二极管芯片3的下表面与上表面,并且每一个发光二极管芯片3选择性地设置于相对应的正极导电部1100上,以使得每一个发光二极管芯片3的正电极端30直接电性连接于相对应的正极导电部1100,并且每一个发光二极管芯片3的负电极端31则通过一导线4而电性连接于相对应的负极导电部1101。That is, the positive and
紧接着,请参阅图9所示,其为本实用新型第一实施例的封装胶体填充于射出凹槽内的立体示意图。由图9可知,该步骤S104之后,将一封装胶体5填充于该射出凹槽20内,以覆盖所述多个发光二极管芯片3(步骤S106)。其中,该封装胶体5的材质可为环氧树脂或硅胶(silicone)材料。Next, please refer to FIG. 9 , which is a three-dimensional schematic view of the encapsulant filling the injection groove according to the first embodiment of the present invention. As can be seen from FIG. 9 , after the step S104 , an
最后,请参阅图10至图11所示,其分别为本实用新型第一实施例的所述多个导电脚被切除后的立体示意图、及本实用新型第一实施例的所述多个导电脚被切除后的另一角度立体示意图。由图10及图11可知,该步骤S106之后,切割所述多个导电脚11,以完成该具有厚导脚的发光二极管芯片封装结构的制作(步骤S108)。其中,每一个导电脚11的两端外露于该绝缘壳体2的两侧,以利后续的焊锡步骤。Finally, please refer to FIG. 10 to FIG. 11 , which are the three-dimensional schematic diagrams of the plurality of conductive legs cut off in the first embodiment of the utility model, and the plurality of conductive pins in the first embodiment of the utility model. A three-dimensional schematic diagram of another angle after the foot is cut off. It can be seen from FIG. 10 and FIG. 11 that after the step S106, the plurality of
请参阅图12所示,其为本实用新型第一实施例的发光二极管芯片的第二种设置方式的侧视示意图。由图中可知,该发光二极管芯片3的正、负电极端30、31分别设置于每一个发光二极管芯片3的下表面与上表面,并且每一个发光二极管芯片3依序地设置于相对应的正极导电部1100′上,以使得每一个发光二极管芯片3的正电极端30直接电性连接于相对应的正极导电部1100′,并且每一个发光二极管芯片3的负电极端31则通过一导线4而电性连接于相对应的负极导电部1101′。Please refer to FIG. 12 , which is a schematic side view of the second arrangement of the LED chips in the first embodiment of the present invention. It can be seen from the figure that the positive and
请参阅图13所示,其为本实用新型第一实施例的发光二极管芯片的第三种设置方式的侧视示意图。由图中可知,该绝缘壳体2还进一步包括:多个分别成形于每两个导电脚11之间的非导电区域21′。再者,该发光二极管芯片3′的正、负电极端30′、31′分别设置于每一个发光二极管芯片3′的上表面,并且每一个发光二极管芯片3′间隔地设置于每一个非导电区域21′上;藉此,通过打线(wire-bounding)的方式,使得每一个发光二极管芯片3′的正、负电极端30′、31′分别通过两导线4′而电性连接于相邻的正极导电部1100′及负极导电部1101′。Please refer to FIG. 13 , which is a schematic side view of a third arrangement of LED chips in the first embodiment of the present invention. It can be seen from the figure that the insulating
请参阅图14所示,其为本实用新型发光二极管芯片的第四种设置方式的侧视示意图。由图中可知,该发光二极管芯片3″的正、负电极端30″、31″分别设置于每一个发光二极管芯片3″的下表面,并且每一个发光二极管芯片3′横跨相对应的非导电区域21″;藉此,通过倒装芯片的方式,使得每一个发光二极管芯片3″的正、负电极端30″、31″分别通过多个相对应的锡球4″而电性连接于相邻的正极导电部1100″及负极导电部1101″。Please refer to FIG. 14 , which is a schematic side view of the fourth arrangement of the light emitting diode chips of the present invention. It can be seen from the figure that the positive and
请参阅图15及图16所示,其分别为本实用新型具有厚导脚的发光二极管芯片封装结构的制造方法的第二实施例的流程图、及第二实施例的金属基材与绝缘壳体相结合的立体示意图。由图15的流程图中可知,本实用新型第二实施例所提供的具有厚导脚的发光二极管芯片封装结构的制造方法,其包括:首先,配合图16所示,提供一金属基材1′,其具有多个延伸出且两端固定的导电脚11′,并且每一个导电脚11′的下表面具有凹槽111′(步骤S200),其中该凹槽111′为一半蚀凹槽。接着,通过一绝缘壳体2′包覆所述多个导电脚11′的下表面,以形成一用于曝露出每一个导电脚11′的上表面的射出凹槽20′(步骤S202)。并且,该绝缘壳体2′填充于所述多个导电脚11′之间的非导电区域21′。Please refer to Fig. 15 and Fig. 16, which are respectively the flow chart of the second embodiment of the manufacturing method of the light-emitting diode chip packaging structure with thick leads of the present invention, and the metal substrate and the insulating case of the second embodiment A three-dimensional schematic diagram of the combination of bodies. It can be seen from the flow chart in FIG. 15 that the manufacturing method of the light-emitting diode chip packaging structure with thick leads provided by the second embodiment of the present invention includes: first, as shown in FIG. 16 , a
接下来,与第一实施例的步骤S104及S108相同,承载多个发光二极管芯片(未图示)于该射出凹槽内,并且每一个发光二极管芯片的正、负电极端分别电性连接于不同的导电脚11′(步骤S204)。然后,将一封装胶体(未图示)填充于该射出凹槽20′内,以覆盖所述多个发光二极管芯片(步骤S206)。最后,切割所述多个导电脚11′,以完成该具有厚导脚的发光二极管芯片封装结构的制作(步骤S208)。Next, same as steps S104 and S108 of the first embodiment, load a plurality of light emitting diode chips (not shown) in the emitting groove, and the positive and negative electrodes of each light emitting diode chip are respectively electrically connected to different The conductive pin 11' (step S204). Then, an encapsulant (not shown) is filled into the emitting
请参阅图17及图18所示,其分别为本实用新型具有厚导脚的发光二极管芯片封装结构的制造方法的第三实施例的流程图、及第三实施例的金属基材与绝缘壳体相结合的立体示意图。由图17的流程图中可知,本实用新型第三实施例所提供的具有厚导脚的发光二极管芯片封装结构的制造方法,其包括:首先,配合图18所示,提供一金属基材1″,其具有多个延伸出且悬空的导电脚11″及多个延伸出且连结于每二个导电脚11″之间的加强肋12″,并且每一个导电脚11″的下表面具有凹槽111″(步骤S300),其中该凹槽111″为一半蚀凹槽。然后,通过一绝缘壳体2″包覆所述多个导电脚11″的下表面,以形成一用于曝露出每一个导电脚11″的上表面的射出凹槽20″(步骤S302)。并且,该绝缘壳体2″填充于所述多个导电脚11″之间的非导电区域21″。Please refer to Fig. 17 and Fig. 18, which are respectively the flow chart of the third embodiment of the manufacturing method of the light-emitting diode chip packaging structure with thick leads of the present invention, and the metal base material and the insulating shell of the third embodiment A three-dimensional schematic diagram of the combination of bodies. It can be known from the flow chart in FIG. 17 that the manufacturing method of the light-emitting diode chip packaging structure with thick leads provided by the third embodiment of the present invention includes: first, as shown in FIG. 18 , a
接下来,与第二实施例的步骤S204及S206相同,承载多个发光二极管芯片(未图示)于该射出凹槽20″内,并且每一个发光二极管芯片的正、负电极端分别电性连接于不同的导电脚11″(步骤S304);然后,将一封装胶体(未图示)填充于该射出凹槽内,以覆盖所述多个发光二极管芯片(步骤S306)。最后,切割所述多个导电脚11″及所述多个加强肋12″,以完成该具有厚导脚的发光二极管芯片封装结构的制作(步骤S308)。Next, same as steps S204 and S206 of the second embodiment, load a plurality of light emitting diode chips (not shown) in the
请参阅图19至图21所示,其分别为本实用新型第一、二、三实施例的金属基材与绝缘壳体相结合的立体示意图。由图19可知,多个第一实施例的具有金属基材1与导电脚11的、金属基材1与绝缘壳体2相结合的结构串联成三排;此外,由图20可知,多个第二实施例的具有金属基材1′与导电脚11′的、金属基材1′与绝缘壳体2′相结合的结构串联成三排;并且,由图21可知,多个第三实施例的具有金属基材1″与导电脚11″的、金属基材1″与绝缘壳体2″相结合的结构串联成三排。藉此,上述三种不同实施例的导电脚11、11′、11″与绝缘壳体2、2′、2″的组合可以整片(all-in-one)的方式制造出来。Please refer to FIG. 19 to FIG. 21 , which are three-dimensional schematic diagrams of the combination of the metal substrate and the insulating housing in the first, second, and third embodiments of the present invention, respectively. It can be seen from FIG. 19 that multiple structures of the first embodiment having the
综上所述,本实用新型所提供的具有厚导脚的发光二极管芯片封装结构,具有下列的优点:To sum up, the light-emitting diode chip packaging structure with thick leads provided by the utility model has the following advantages:
1、本实用新型的厚导脚不需经过弯折,而能直接与电路板产生接触,因此本实用新型能简化制造工艺的复杂度。1. The thick guide pin of the present invention does not need to be bent, but can directly contact the circuit board, so the present invention can simplify the complexity of the manufacturing process.
2、由于采用厚导脚,因此本实用新型可增加散热面积,而达到高散热的优点。2. Due to the use of thick guide feet, the utility model can increase the heat dissipation area and achieve the advantage of high heat dissipation.
3、由于采用厚导脚,因此本实用新型可提高电源的供应量,而使得发光二极管芯片可产生较高的发光效能。3. Due to the use of thick guide pins, the utility model can increase the supply of power supply, so that the LED chip can produce higher luminous efficiency.
注意,以上所述,仅为本实用新型最佳之一的具体实施例的详细说明与附图,但本实用新型的特征并不局限于此,并非用以限制本实用新型,本实用新型的所有范围应以下述的权利要求为准,所有符合于本实用新型申请专利范围的精神与其类似变化的实施例,皆应包含于本实用新型的范畴中,任何熟悉该项技术的人员在本实用新型的领域内,可轻易想到的变化或修饰皆可涵盖在以下本申请的专利范围内。Note that the above description is only a detailed description and drawings of one of the best specific embodiments of the utility model, but the features of the utility model are not limited thereto, and are not intended to limit the utility model. All scopes should be based on the following claims, and all embodiments that conform to the spirit of the patent scope of the utility model and its similar changes should be included in the scope of the utility model. In the field of novelty, easily conceivable changes or modifications can all be covered within the scope of the following patents of this application.
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101806439A (en) * | 2009-02-18 | 2010-08-18 | 黄嘉宾 | Heat dissipation structure of LED |
CN102446909A (en) * | 2010-09-30 | 2012-05-09 | 展晶科技(深圳)有限公司 | Light-emitting diode combination |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101806439A (en) * | 2009-02-18 | 2010-08-18 | 黄嘉宾 | Heat dissipation structure of LED |
CN101806439B (en) * | 2009-02-18 | 2013-04-17 | 黄嘉宾 | Heat dissipation structure of LED |
CN102446909A (en) * | 2010-09-30 | 2012-05-09 | 展晶科技(深圳)有限公司 | Light-emitting diode combination |
CN102446909B (en) * | 2010-09-30 | 2015-03-11 | 赛恩倍吉科技顾问(深圳)有限公司 | Light-emitting diode combination |
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